JPS6367055A - Code rule violation detection circuit - Google Patents

Abstract

PURPOSE:To constitute the circuit of a CMOS, etc., of a low power consumption, and to reduce the power consumption by dropping processing speed by converting a series data to a parallel data by a serial/parallel converter, and detecting a code rule violation. CONSTITUTION:The serial/parallel converter 1 of a code rule violation detection circuit converts a series data of a CMI code which is inputted, to a parallel data. A decoding circuit 2 decodes this parallel data and outputs the original data. Subsequently, a '1'-code information output means 3 obtains the code of '1' from the parallel data and the original data, inputs it to a code rule violation deciding circuit 5, and also, inputs and stores it in the information storage means 4 of '1'-code before by one. The code rule violation deciding circuit 5 inputs the information of '1'-code before by one, as well, and decides a code rule violation.

Description

[Detailed Description of the Invention] [Summary] CMI (Coded-Mark-Inversio
n) Detection of violation of code rules by serial/parallel converter
By converting to I-code parallel data at a lower speed, it is possible to configure it with a CMO3 or the like with low power consumption.

(Industrial Application Field) The present invention relates to an improvement in a code rule violation detection circuit that detects a code rule violation in a CMI code that suppresses consecutive zeros in digital transmission.

CMI code is a type of code that suppresses consecutive zeros in digital transmission, and as shown in Figure 8, it sets "0,1" for O in the input binary code and "0.0" for ■. ” and “1. 1
” are sent out alternately.

The CMI code rules are "0.o" and '1.1 for 1.
'', but in violation of this, for example, as shown in Figure 9, "1.1" is given consecutively, and this code rule violation (
Code・Ru1e・■i.

For example, there is a method of performing frame synchronization every time a l a t i on = CRV) is detected.

It is desirable that the code rule violation detection circuit that detects this code rule violation has low power consumption even when the transmission speed becomes high.

In the following explanation, two codes of the CMI code, for example “
The 1 of 0,1'' is expressed as the latter part.

[Conventional technology]

A conventional example will be explained below using figures.

FIG. 5 is a block diagram of the conventional example, FIG. 6 is a tie J chart showing the binary codes of each part in the case of FIG. 5, and FIG. 7 is a S,
It is a figure which shows the truth value of R flip-flop.

The truth values of the S and R Frisopf l"j knobs 46 in FIG. 5 are shown in FIG. 7. When 0 is input to both S and R, the output Q maintains the previous value, and S is set to 0. When 1 is input to .1?, the output Q is 0, and when 1 is input to S, 1 or O is input to R.
is input and '(also outputs Q kl: ).

At the (CRV) point of the data shown in (A) of Figure 6, (
As shown in 3), a CRV of '0° (B) is given to the <CMI code, and the flip-flop 4 of the phase matching circuit 40 in FIG.
2.43) In the case of the flip-flop 42, it is struck by the clock shown in (C), and the part after the CMI code shown in (B) (A2.B2.C2, . . . ) is outputted from the output Q and inputted to the S and AND circuit 48 of the S, R flip-flop 46 in binary code as shown by S in FIG. 6(C).

In the case of the flip-flop 43, it is clocked by the clock shown in (D) which is inverted by the NOT circuit 44, and the part before the CMI code shown in (B) (A1°B1.CI, ・
) is output from the output Q and input to the flip-flop 45. By being hit by the clock shown in C), the part after the CMI code (A2.B2.C2,...
) and S in binary code as shown at R in FIG. 6(C).

It is input to the R of the R flip-flop 46 and the AND circuit 49 .

Therefore, as shown in Q in FIG. 6(C), the output Q of the S, R flip-flop 46 is outputted according to the truth value in FIG. 7 and inputted to the flip-flop 47, as shown in FIG. When clock C hits, binary codes as shown in FIG. 6(D) are outputted from outputs Q and Q, and inputted to tent circuits 48 and 49, respectively.

In this case, from the AND circuit 48.49, Fig. 6 (E
)(F), binary number 71 is output, and the OR circuit 5
0, and 1 at the CRVO location as shown in Figure 6 (G).
A binary code corresponding to the code is output, and a code rule violation is detected.

Note that the OR circuit 51 outputs original data as shown in FIG. 6 (11).

[Problem that the invention seeks to solve]

However, since this code rule violation detection circuit detects a violation of the serial data code rule, when the transmission speed becomes high, each part has an emitter-coupled logic (E
There is a problem that the power consumption increases because the "C" configuration is used for the CL).

[Means for solving problems]

” The principle block diagram of the present invention that solves the problem described in 1.
As shown in the figure.

The serial/parallel converter 1 converts input serial data of Ctl code into parallel data. The decoding circuit 2 decodes the parallel data and outputs the original data. The code information output means 3 of 1 obtains the code of 1 from the parallel data and the original data, inputs it to the code rule violation determination circuit 5, and inputs and stores it in the code information storage means 4 of the previous 1. The code rule violation determination circuit 5 also inputs the code information of the previous one, and determines whether the code rule is violated.

[Effect]

According to the present invention, even if the transmission speed is high, the serial data is converted into parallel data of CMI code in the serial/parallel converter 1 to reduce the processing speed and detect code rule violations. Therefore, the circuit can be configured using a low power consumption CMO3 or the like, and power consumption can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 2 is a block diagram of the embodiment of the present invention, and FIG. 3 is a block diagram showing the binary codes of each part in FIG. 2.
The figure is a circuit diagram of the selector.

The circuits of the selectors 20 to 23 in FIG. 2 are as shown in FIG. When the signal input to terminal S is 1, the newsletter input to terminal 1 is m IJ< and output via the OR circuit 33, and when the signal input to terminal S is 0, , the signal input to terminal 0 is selected and output via the OR circuit 33.

Figure 2 shows four pieces of CMI-encoded data, and Figure 3 (B
), the signals are expanded in parallel and input to the flip-flop 6 to detect a violation of the code rule, and the part surrounded by the dotted line in FIG. 3(B) is the part where the code rule is violated.

The CM shown in FIG. 3 (B) input to the flip-flop 6
The I code is input to the decoding circuit 2 at the clock shown in FIG.
The data is decoded into original data as shown by D1 to D4 in FIG.

Also, the output Q2 of the flip-flop 6. Q4. Q6゜The part after the CMI code from Q8 is the code information output means 3 of ■.
input to terminal 1 of selectors 20-23.

The outputs of SL, S2, and 33 of the selectors 20 to 22 are input to the terminals 0 of the selectors 21 to 23, and the output of the selector 84 of the selector 23 is input to the flip-flop 4 of the previous code information storage means 1. , the output Q is input to the terminal O of the selector 20.

Here, to explain the human output relationship between the code information output means 3 of 1 and the code information storage means flip-flop 4 of the previous 1 using the data shown in FIG.
The terminals S from 0 to 23 are connected to DI (C), D2. D3. I
) The decoded data of 1, 0, 1.0 in the first column shown in 4 is input 7.

Therefore, from the output of 5l-34 of selectors 20-23,
As shown in the first column of (D), 0°Sl of Q2. Q6
1. 1 of S3 is output.

In other words, since the data of DI and D2 are 1.0, the outputs Sl and S2 of the selectors 20.21 output 0, which is the part after the data 1 of DI, and D3. Since the data of D4 is 1.0, the output S3 of selector 22.23
．． From S4, code information of 1 is output by outputting 1 in the part after data 1 in 1) 3.

At this time, the 1 after the data 1, which is the output of 84 of the selector 23, is input to the flip-flop 4, which is the code information storage means for the previous 1, and is stored, and the SO is output at the next clock. From the output, 1 is output as shown in the second column of (1 勺), but the decoded data in the second column is (C)
Since they are all 0 as shown in , the 1 in the subsequent part slides up the selectors 20 to 23, outputs 1 as shown in (D> from the outputs 81 to S4, and this is input to the flip-flop 4. .

In this case, the output of the negative exclusive OR circuits 15 to 18 is 1 as shown in the second column of F1 to F4 in (F), but the decoded data is O, so the AND circuit 24
The output of ~27 is (G) V], -V 0 as shown in 4.
becomes.

At the next clock, 1 is output from the SO output of flip-flop 4 as shown in the third column of (E), and the decoded data in the third column is as shown in D1 to D4 of (C). <
0.1, 1.1, SO output 1 is output from the output S1 of the selector 20, and Q, which is the part after the CMI code 1, is output from the outputs S2 to S4 of the selectors 21 to 23.
4's 0° Q6's 1. The O of Q8 is played.

That is, the part O after the 1 data of D2, which is the output of 82 of the selector 21, and the output of S1 of the selector 20,
The part l after the previous 1 data is input to the negative exclusive OR circuit 16, and since it is different, it is assumed to be alternated and 0 is written as shown in F2 in the third column of (1"). Output.

Therefore, the AND circuit 25 outputs O.

Also, the 0 after the 1 of the data D2 which is the output of the selector 21, and the 1 of the next data D3 which is the output of the selector 22.
The 1's in the latter part are both input to the negative exclusive OR circuit 17, and since they are different, they are assumed to be alternated and O is output as shown in do 3 of the third column 1-1 of (I?).

Therefore, the ant circuit 26 outputs 0.

If the part after l in the CMI code is alternate in this way, the code rule violation determination circuit 5 outputs 0.

However, for example, Q 3 of the CMI code of data 1, as shown in the part surrounded by the dotted line in column 6 of FIG.

Is Q4 the CM I of data 1 in front of the 5th column? Q'
Regardless of whether Ql and Q2 of 4J are “0, 0”, “0”
If there is a sign rule violation in ゜0'', 1 is added to the 6th column of (1]).
As shown, the flip-flop 4 outputs 0 after the 1 data in the fifth column, and since the data DI is O, 0 is output from the output of Sl of the selector 20, and the negative exclusive logic is output. It is input to the sum circuit 16.

On the other hand, from the output of 82 of the selector 21, O of the part after the CMI code of 1 of the data D2 is outputted and inputted to the negative exclusive OR circuit 16, but since both are 0, ■ is outputted and the AND circuit 25.

The tent circuit 25 receives D2 from the negative exclusive OR circuit 12.
Since data 1 is input, a violation of the sign rule is detected by outputting 1 from the output.

In this way, it is possible to reduce the operating speed through parallel expansion and detect code rule violations, so even if the transmission speed becomes high, the CM
The circuit can be constructed using a device with low power consumption such as O3, and the power consumption of the code rule violation detection circuit can be reduced.

〔Effect of the invention〕

As explained in detail above, according to the present invention, it is possible to perform parallel expansion to reduce the operating speed and detect code rule violations, so even if the transmission speed becomes high, the circuit configuration can be configured using a device with low power consumption such as a CM S. This has the effect of reducing the power consumption of the code rule violation detection circuit.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a time chart of each part in Fig. The figure is a circuit diagram of the selector, Figure 5 is a block diagram of a conventional example, Figure 6 is a time chart showing the binary sign months of each part in the case of Figure 5, and Figure 7 is the truth value of S and R flip-flops. 8 is a diagram showing a CMI code, and FIG. 9 is a diagram showing a code in which a code rule violation is given to a CMI code. In the figure, l is a serial-to-parallel converter, 2 is a decoding circuit, 3 is a code information output means of I, 4 is a code information storage means of the previous 1, 5 is a code rule violation judgment circuit, 6 is a flip-flop, 11 to 1B are negative exclusive OR circuits, 20 to 23 Selectors 24 to 27 indicate AND circuits.

Claims (1)

[Claims] CMI (Coded/Mark/Inversion)
When detecting code code violation, a serial-to-parallel converter (
1) is converted into CMI code parallel data, inputted to the code information output means (3) of 1 along with the original data decoded by the decoding circuit (2), and outputs the code of 1 to conform to the code rules. The code information of the previous 1 is inputted to the violation determination circuit (5), and code information of the previous 1 is generated, and the code information of the previous 1 is input and stored in the code information storage means (4) of the previous 1. A code rule violation detection circuit characterized in that a code rule violation detection circuit is configured to input an input to a code rule violation determination circuit (5) to determine a code rule violation and detect a code rule violation.