JPS63226142A - C-bit error counter - Google Patents

Abstract

PURPOSE:To detect an error of C-bit for the mBIC code rule by constituting the titled counter of an exclusive OR circuit, a seriesparallel converting circuit, a selector circuit and a counter circuit. CONSTITUTION:The titled counter is provided with a circuit 1 for bringing a signal bit and a bit immediately before said bit, to exclusive OR, a series- parallel converting circuit 2 for brining a signal which is brought to exclusive OR, to a series-parallel conversion, a selector circuit 3 for selecting one of output parallel signals of said series-parallel converting circuit 2, and a counter circuit 4 for counting a pulse output of this selector circuit 3. In such a way, with respect to a digital signal for using an mBIC code for a transmission line code rule, an error of its C-bit can be detected and counted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a code error detection circuit for a digital relay device, and in particular detects a code error in the C bit of the mBIC code rule.
Concerning the counting C-bit error counter.

[Conventional technology]

Conventional C-bit error counters of this type are comprised of a clock frequency divider circuit, an error detection circuit, a block synchronization circuit, and the like.

[Problem that the invention seeks to solve]

As mentioned above, the conventional C-bit error counter described above is composed of a clock frequency dividing circuit, an error detection circuit, a block synchronization circuit, etc., and the circuit structure is complicated and the scale is large. There was a problem. Furthermore, there is a problem that it is not economical due to the complexity of the structure.

[Means for solving problems]

The C-bit error counter of the present invention is a circuit that detects and counts C-bit errors in a digital signal using an mBIC code for the transmission line coding rule, and detects and counts errors in the C-bit and a circuit for exclusive-ORing bits, a serial-to-parallel conversion circuit for serial-to-parallel conversion of the exclusive-OR signal, a selector circuit for selecting one of the output parallel signals of this serial-to-parallel conversion circuit, and this selector. A counter circuit that counts the pulse output of the circuit is provided.

[For production]

In the present invention, C-bit errors are detected and counted for digital signals that use mBIC codes as transmission path coding rules.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which mBIC coding rules are used, especially when m = 4, that is, 4
This shows the case of BIC.

In the figure, 1 is an exclusive OR circuit that exclusively ORs a signal bit and its immediately preceding bit, and is a flip-flop circuit that receives a data signal from a data input terminal 5 and a clock signal from a clock input terminal 6. (Hereinafter, abbreviated as FF) l-1 and FF1-2 which receives the output of this FFl-1 as inputs, and an exclusive OR circuit 1-3 which receives the outputs of FFl-1 and FFl-2 as inputs. It is configured. Reference numeral 2 denotes a serial-to-parallel conversion circuit for serial-to-parallel conversion of the exclusive ORed signal by this exclusive OR circuit 1, which receives the output of the exclusive OR circuits 1-3 and the clock signal from the clock input terminal 6. FF2-1 and 0FF2-1
FF2-2.2-3@...U2-5 and each output of the above FF2-1 to 2-5 and 5 frequency divider circuit 2 connected in cascade to
-FF2-6.2- with each output of 11m as input
7...2-10.

The 5 frequency divider circuit 2-11a receives the clock signal from the clock input terminal 6 and is configured to divide the clock signal according to a set division ratio.03 is the output of the serial-parallel converter circuit 2 A selector circuit that selects one of the parallel signals, inverting OR circuit 3-1.3-2@...
-3-6, inversion circuit 3-7 and cascade-connected FF3
-8.3-9...3-12 and these FF3-8
04 is a pulse counter that receives the output of FF 3-12 as input, and this pulse counter 4 counts the pulse output of the selector circuit 3. It constitutes a counter circuit.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, before explaining the operation, the mBIC coding rule will be explained to facilitate understanding of the present invention.

The mBIC coding rule is such that (m+1) bits are used as a basic block, and the complementary code of the m-th bit code is the (m-1-1)-th bit code.

If the mth bit is 1ON, the (m+1)th bit is l, and if the mth bit is vAIN, it is (m
+1) bit becomes 0.

This (m+1)th bit is called the C hit.

Now, FIG. 1 is shown assuming that m=4.

The data of 4BIC is input to the first FF 1-1, and its output is branched into two, one is input to the second OFF 1-2, and the other of the output of this first FF'l-1 and the The output of 2OFFI-2 is input to exclusive OR circuit 1-3.

The outputs of the exclusive ORs 1-3 are input to the serial/parallel conversion circuit 2, and five parallel signals are output.

Then, one of these five parallel signals is the 4th bit and the 5th bit.
This is an exclusive OR signal with the th bit (C bit).

However, it is unclear where this is located.

Next, among the five parallel signals, selector circuit 3)
One signal is selected. When the output of the selector circuit 3 changes from i=%1# to %o, the selector operates based on the output and sequentially selects the next parallel signal.

Then, the output of the exclusive OR of the 4th and 5th bits is always vk unless there is an error ρ in the C bit (5th bit).
l#, the selector retains its position. Also, if there is an error in the C bit, the selector circuit 3 will operate,
The signals are sequentially selected and held again at the output position of the exclusive OR of the 4th and 5th bits.

Therefore, by counting the operation of this selector with the counter circuit 4, errors in the C bit can be detected and counted.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.
This indicates when.

In FIG. 2, parts that are the same as those in FIG. 1 are given the same reference numerals and explanations will be omitted. 2-11b is a (m+1) branch circuit.

The operation of the mBIC shown in FIG. 2 is similar to that of the 4BIC shown in FIG. 1, so
The explanation here will be omitted.

〔Effect of the invention〕

As explained above, according to the present invention, errors in the C bit of the mBIC coding rule can be detected and counted using a simple configuration of an exclusive OR circuit, a serial/parallel conversion circuit, a selector circuit, and a counter circuit. Therefore, the practical effect is extremely large. Further, it is extremely effective in that it is economical due to the simplification of the configuration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the invention, and FIG. 2 is a circuit diagram showing another embodiment of the invention. 1: fist exclusive OR circuit, 2: serial-to-parallel conversion circuit, 3: selector circuit, 4: counter circuit.

Claims (1)

[Claims] A circuit for detecting and counting errors in C bits of a digital signal using an mBIC code as a transmission line coding rule, the circuit performing exclusive OR of the signal bit and its immediately preceding bit; A serial-to-parallel conversion circuit for serial-to-parallel conversion of the exclusive ORed signal, a selector circuit for selecting one of the output parallel signals of the serial-to-parallel conversion circuit, and a counter circuit for counting the pulse output of this selector circuit. A C-bit error counter comprising: