JPH05135187A - Digital signal processor - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a digital signal processor. CONSTITUTION:Code converters 3 and 4 which generate codes for shortening a humming distance according to the statistical characteristics of a signal so as to decrease the frequency of inversion between binary values 0 and 1, are connected to a coupling part of at least one of digital signal processing means 1 (processor 1, memory 9, input/output circuit 10, etc.) which are coupled by an address bus 7, a data bus 8, etc. The frequency of the polarity inversion of 0 and 1 when a load is drive can be decreased to reduce power consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing apparatus, and more specifically, a digital signal processing apparatus suitable for equipment such as a notebook personal computer, a pager, a pocket phone, a small TV camera, etc. The present invention relates to a signal processing device.

[0002]

2. Description of the Related Art With the spread of small information terminals such as notebook type personal computers and pagers, there is an increasing demand for low power consumption of microprocessors, digital signal processing circuits, memory circuits and the like. In order to meet these demands, reduction of drive power voltage has been conventionally promoted. In general, the power consumption W of a CMOS circuit and a device composed thereof is

[Equation 1] Given in. Here, Cn is the capacity of the gate n, V is the power supply voltage, N is the total number of gates, and Pn is the ON rate of each gate (the probability that the input / output of the gate is inverted within a unit time). In the conventional technology, attention has been paid to the fact that the power supply voltage has a squared effect with respect to the consumption voltage, and the power consumption has been reduced by lowering the power supply voltage. A typical example of this is
The low-voltage operating microprocessor described in Nikkei Microdevice, October 1990, pp. 90-91.

[0003]

As shown in FIG. 2, the general configuration of a microcomputer is such that a digital signal processing circuit such as a microprocessor 1, a memory 9 and an input / output circuit 10 has an address bus 7 and a data bus 8. It is configured to be connected to each other via. When the processor 1 sequentially reads instructions from the memory 9, the address on the address bus 7 is increased by one address in most cases. For example 01
100 from address 111111B (B indicates a binary number)
When the address changes to the address 00000B, since the address is expressed in the binary number in the conventional technique, the polarities of the binary values in all the lines of the eight address buses,
That is, 0 and 1 are inverted. Usually, an address bus, a data bus, and the like have large parasitic capacitances, and thus driving them requires a large amount of power as compared with the case of driving other gates. Frequent inversion of 1 and 0 in a portion that consumes a large amount of power increases power consumption, which is not desirable. It is an object of the present invention to realize a digital signal processing device that reduces power consumption in a large power consumption portion of the digital signal processing device.

[0004]

In order to achieve the above object, the present invention provides a digital signal processing device in which a plurality of digital signal processing circuits are connected by a line for transmitting a digital signal. Circuit means for reducing the number of polarity inversions of the transmitted digital signal is provided in a portion which is coupled to at least one of the plurality of digital circuits and a line for transmitting the digital signal.

As a form in which the plurality of digital signal processing circuits are connected by a line for transmitting digital signals, there are two types.
When the arithmetic circuit based on the evolution code and the storage device are connected by an address bus, when the arithmetic circuit based on the binary code and the input / output control circuit are connected by the data bus, when the input / output control circuit and the storage device are connected by the data bus, There are a case where the A / D converter and the memory are connected by a line, a case where the delay circuit and the arithmetic circuit are connected by a line, and the like.

The circuit means for reducing the number of polarity inversions of the digital signal transmitted by the line for transmitting the digital signal is a code conversion circuit for performing code conversion according to the characteristics of the code structure of the digital data, and an address code. There is a circuit means, etc., in which a counter is provided in the transmission circuit, the clock signal of the counter is normally transmitted, and the address code is transmitted through the address bus only when a specific address code is transmitted. The above code conversion circuit is a circuit for performing code conversion based on the principle of the present invention so that the Hamming distance of a digital code is shortened. A conversion circuit for converting the binary code into the Gray code is typical, but not limited to this.

[0007]

Since the digital signal processing apparatus of the present invention is provided with a circuit for performing code conversion so that the Hamming distance of the digital code becomes shorter according to the property of the signal to be processed, the polarity inversion of 1 and 0 of the digital code is performed. The number of times is reduced and the power consumption due to stray capacitance and load due to polarity reversal is reduced. For example, when the address bus is driven by the Gray code, the calling address of the program instruction has a signal property that the address tends to increase by one. Therefore, if the binary code of the address is converted into the Gray code, the Hamming distance is significantly shortened. FIG. 3 shows a case where the address changes from the address 7FH (H indicates a hexadecimal number) to the address 80H. Two
When the address is written in the evolution code, the Hamming distance between 7FH and 80H is 8, and 1,0 inversion occurs 8 times. On the other hand, the Hamming distance in gray code notation is 1
Therefore, the polarity reversal of 1 and 0 occurs only once. The feature that the 1,0 inversion occurs only once in the Gray code is established in the entire address space.

As another embodiment for reducing the number of 1 and 0 inversions according to the present invention, there is a means for reducing the number of times of address transmission using the address bus without using code conversion. As shown in an embodiment of FIG. 9 described later, both the processor and the memory have program counters incorporated therein, and when the branch instruction does not come, both program counters are synchronized to transfer the contents of the memory to the processor. When a branch instruction appears, the address of the branch destination is transmitted to the memory via the address bus. Since the signal is input to the address bus only when the branch instruction is detected, the power for driving the address bus can be reduced.

[0009]

Embodiments of the present invention will be described with reference to the drawings. 1 is a block diagram of a first embodiment of a digital signal processing apparatus according to the present invention. In this embodiment, the processor 1 and the memory 9
-1, 9-2. ． ． 9-n and the input / output circuit 10. The address bus 7 and the data bus 8 are driven by a signal having a short Hamming distance coded according to the characteristics of the code structure of the signal. The processor 1 includes an address code converter 3 and a data code converter 4, and the processor 1 operates with a binary code. Therefore, it is possible to apply the conventional processor 1 already recorded in the database as the macro cell. By providing the input / output circuit 10 with the code converter 11 between the data bus 8 and the processing unit 12, compatibility is maintained with respect to the exchange of the binary code signal 14 with the outside.

Gray code is used as a specific code of the address bus 7. The Gray code is particularly effective when the Hamming distance between adjacent codes is always 1, and the address signal regularly increases by 1 like the address change during the program operation. Also, with respect to the data bus 8, a gray code is used for data of an image signal having a strong correlation with a nearby signal.

FIG. 4 shows a comparison of the Hamming distances when the Gray code and the binary code have 4 bits each. The data was compared with each other next to every other data. Comparing the averages of the Hamming distances of each case, (1) when they are adjacent Gray code: average of 1.00 2 evolution code: average of 1.73 (2) every other case Gray code: average of 2.00 2 evolution code : Average 1.57 (3) Every other two Gray code: Average 1.92 2 evolution code: Average 2.46 (4) Overall (no weighting) Gray code: Average 1.62 2 evolution code: Average 1. 90. Gray code is more effective for low power consumption for signals that have a strong correlation with neighboring signals.

In the embodiment of the present invention shown in FIG. 1, the processor 1, the memory 9 and the input / output circuit 10 are composed of three main constituent parts. These main constituent parts are formed on one chip. The same effect can be obtained in the case of Also,
The circuit 3 for converting a binary code into a Gray code can be configured by a conventionally known simple circuit in which exclusive OR circuits are arranged in parallel as shown in FIG.

Further, the code is not limited to the Gray code, and any code can be used as long as the Hamming distance can be shortened. FIG. 6 is a diagram for explaining an example of a 3-bit binary code and a conversion code having a short Hamming distance for the sake of simplicity. Black dots represent code positions, and binary codes are in the order shown by dotted lines, that is, 000, 001, 010, 011 and 11
0 ,. ． ． Although they are arranged in 111, the Hamming distance can be shortened and the codes are 110, 111, 1 as shown by the solid line.
01, 100,000, 001, 011, 010, 11
If they are arranged in a circular manner, the Hamming distance can be shortened.

FIG. 7 is a diagram showing the configuration of the second embodiment of the digital signal processing apparatus according to the present invention. The first embodiment is applied to a processor 15 having a Hubbard architecture structure having two address spaces of program memories 16-1, 16-2, 16-3 and data memories 17-1, 17-2, 17-3. Is. By separating the program and the data, the address conversion can be made smaller and the power consumption can be reduced. The gray code is also effective for the data memory address when there is a lot of processing for successively loading a large amount of data.

FIG. 8 is a diagram showing the configuration of a third embodiment of the digital signal processing apparatus according to the present invention. This embodiment is mainly intended for a dedicated processor. This embodiment is A
/ D converter 22, code conversion circuit 23, memory circuit 2
4, decoding circuit 25, arithmetic circuit 26, D / A converter 2
8 and the like are constructed on one chip. The data captured by the A / D converter 22 is converted by the code conversion circuit 23 into a code having a shorter Hamming distance than the binary code and is input to the memory circuit 24.

The memory circuit 24 is composed of a RAM (random access memory), a shift register and the like. The data in the memory circuit 24 is decoded by the decoding circuit 25, an operation is performed by the operation circuit 26 using the decoded data, and the operation result is output from the D / A converter 28 as an analog signal. If necessary, the operation result of the operation circuit 26 is code-converted by the code conversion circuit 27 and input to the memory circuit 24. As the memory capacity increases, more power is consumed when inputting / outputting data. In this embodiment, the number of 0 and 1 inversions associated with the input and output of data is reduced to configure a digital signal processing device with low power consumption.

FIG. 9 is a diagram showing the configuration of the fourth embodiment of the digital signal processing apparatus according to the present invention. In this example,
Similar to the third embodiment, it is intended for a dedicated processor and uses a Gray code as a code stored in the memory circuit 30. In addition, it adopts a pipeline structure as an arithmetic method. Therefore, the delay circuits 32, 37, 40
And so on.

The A / D converter 29 directly converts an analog signal into a Gray code. In this embodiment, three arithmetic circuits 33, 36 and 39 of A, B and C are used. Of the data in the memory circuit 30, the data calculated by the calculation circuit 33 is converted into a binary code by the conversion circuit 31 and calculated. A part of the calculation result is passed to the calculation circuit 36. Conversion circuit 31
The data by the gray code delayed by the delay circuit 32 for the number of steps used for is converted into a binary code by the conversion circuit 34 and added to the operation circuit 36 together with the operation result of the previous operation circuit 33 to be operated. Since the delay circuit is composed of a shift register using a flip-flop circuit,
Power consumption can be reduced by using a code having a short Hamming distance not only in the memory circuit but also in the delay circuit as in the present embodiment.

In this embodiment, the embodiment using the Gray code has been described, but other codes having a short Hamming distance may be used depending on the statistical properties of the data processed as in the third embodiment. The inputs of the plurality of arithmetic circuits are one or more of the following various signals depending on the processing contents of the dedicated processor. Output of own or other arithmetic circuit, output of analog-digital converter or memory circuit Analog-digital converter, output of memory circuit or signal obtained by delaying output of own or other arithmetic circuit by delay circuit. If it is not a binary code, it is input to the arithmetic circuit via the code converter.

FIG. 10 is a diagram showing the configuration of an embodiment of a code conversion circuit used in the digital signal processing device according to the present invention. In this embodiment, optimal code conversion can be performed depending on the type of signal to be processed and the type of device used, and in order to enhance the versatility of the code conversion circuit, a plurality of types of code conversion are included, including the case where no code conversion is performed. Is performed as an alternative. By the switch drive signal from the code selection signal generation circuit 45, the switch 43-0 on the input side,
Either the switch 1 or 2 or the switch 44-1 or 2 on the output side is selected. When the switch 43-0 is selected, the input code is output as it is. Switch 43
-1 and 44-1 are selected, the binary code and Gray code converter 42-1 is selected, and the switch 43-
2 and 44-2 are selected, the other converter 42-2
Is selected. The code selection signal generation circuit 45 may be incorporated as a circuit into a digital signal processing device,
Further, when it is not used after being incorporated in the digital signal processing device, it may be removed. If switching control is performed by microcode, switching can be performed using a program.

FIG. 11 is a diagram showing the configuration of a fifth embodiment of the digital signal processing device according to the present invention. This embodiment is a system including a processor and a memory as in the first and second embodiments, and particularly reduces 0, 1 inversion of the address bus. As described in the second embodiment, when the program is being executed, the program memory is often accessed while increasing the address by one. In such a case, it is effective to reduce the 0, 1 inversion by expressing the address signal in gray code as described in the second embodiment, but as shown in the present embodiment, the processor unit 46 and the memory unit 47 are paired. The method of providing the counter 48 for the program address and the register 49 for the branch address is also effective. Normally, the address counter 50 of the memory unit 47 is counted up via the clock signal line 52 in synchronization with the counter 48 of the processor unit 46, and no signal is passed through the address bus 53. Only when the address of the memory to be accessed is skipped due to a branch or the like, the address signal of the jump destination is sent via the address bus 53 to the address register 51 of the memory unit 47.
Send to. According to this embodiment, power consumption due to 0, 1 inversion of the address bus can be reduced. Although the case of the program memory is shown in this embodiment, it is also effective as the data memory in the case of an application using a large amount of continuous data.

[0022]

As described above, the present invention statistically reduces the Hamming distance from the binary code to reduce the power consumption due to the signal change in the data bus, address bus, memory, delay circuit, etc. of the digital signal processor. It is realized by converting into such a code and reducing the number of 0 and 1 inversions. When the Gray code is applied to a continuous signal having a signal change of 1, as described in the first embodiment,
The power consumption in the above portion is about 1 / 1.7. According to the present invention, it is possible to realize a digital signal processing device with lower power consumption than ever before.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of a digital signal processing device according to the present invention.

FIG. 2 is a diagram showing a configuration of a conventional microcomputer.

FIG. 3 is a diagram showing a comparison of a Hamming distance between a gray code and a binary code.

FIG. 4 is a diagram showing a comparison of a Hamming distance between a gray code and a binary code. It is a block diagram of the 2nd Example of the digital signal processing apparatus by this invention.

FIG. 5 is a circuit diagram for converting a binary code into a Gray code.

FIG. 6 is a diagram illustrating an example of a 3-bit binary code and a conversion code having a short Hamming distance.

FIG. 7 is a configuration diagram of a second embodiment of a digital signal processing device according to the present invention.

FIG. 8 is a configuration diagram of a third embodiment of a digital signal processing device according to the present invention.

FIG. 9 is a configuration diagram of a fourth embodiment of a digital signal processing device according to the present invention.

FIG. 10 is a diagram showing a configuration of an embodiment of a code conversion circuit used in the digital signal processing device according to the present invention.

FIG. 11 is a fifth part of the digital signal processing device according to the present invention.
It is a block diagram of the Example of.

[Explanation of symbols]

1, 15, 46: Processor, 2, 26, 3
3, 36, 39: arithmetic circuit 3, 4, 11, 23: code converter 5, 6, 13:
Connection line, 7, 18, 19, 53: Address bus, 8, 20, 2
1: data bus, 9, 16, 17, 24, 30: memory circuit, 10: input / output circuit, 12: processing unit, 22, 29: A
/ D converter, 25: decoding circuit 28: D / A converter 32, 37, 40: delay circuit 31, 34, 35, 38, 41, 42: gray / binary code conversion circuit, 43, 44: switch, 45: code selection signal generation circuit, 47: memory unit, 48, 50: counter, 49, 51: branch destination address register, 52: clock line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kouji Kojima 1-280, Higashi Koikeku, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Tatsuharu Matsuura 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central research institute

Claims (16)

[Claims] 1. Code conversion means for reducing the number of polarity reversals of binary values 0, 1 at the connection part of at least one digital signal processing means of a plurality of digital signal processing means connected by a bus with the bus. A digital signal processing device characterized by being provided. 2. The digital signal processing device according to claim 1, wherein a code conversion circuit is provided as the code conversion means so that a Hamming distance between adjacent codes becomes 1. 3. The digital signal processing device according to claim 1, wherein the plurality of digital signal processing means are an arithmetic circuit and a storage device by a binary code, an arithmetic circuit and an input / output control circuit by the binary code, or an input / output control. A digital signal processing device, which is at least one of a circuit and a storage device. 4. The digital signal processing device according to claim 1, wherein the plurality of digital signal processing means are an arithmetic circuit and a storage device by a binary code, the bus is an address bus, and the address of the storage device is A digital signal, which is set by a Gray code, and wherein the code conversion means is a code conversion circuit for a binary code and a Gray code provided in a connection portion of the arithmetic circuit for the binary code with the address bus. Processing equipment. 5. The digital signal processing device according to claim 1, wherein the plurality of digital signal processing means are a binary coded arithmetic circuit and a storage device, the bus is a data bus, and the data of the storage device is A digital signal recorded in Gray code, wherein the code conversion means is a code conversion circuit for the binary code and the Gray code provided in the connection portion of the arithmetic circuit for the binary code with the data bus. Processing equipment. 6. The digital signal processing device according to claim 1, wherein the plurality of digital signal processing means are an arithmetic circuit and an output circuit, the bus is a data bus, and the data in the storage device is recorded in gray code. The code converting means is provided in a first conversion circuit provided in a connection part of the arithmetic circuit with the data bus and a first conversion circuit provided in a connection part of the output circuit with the data bus. A second signal conversion circuit for inverse conversion, which is a digital signal processing device. 7. A digital signal processing apparatus according to claim 1, wherein one of said plurality of digital signal processing means is composed of an A / D converter for converting an input analog signal into a digital signal. Signal processing device. 8. The digital signal processing apparatus according to claim 1, wherein the code conversion means has a plurality of types of code conversion circuits and a means for switching the plurality of types of code conversion circuits. apparatus. 9. The digital signal processing device according to claim 8, wherein the means for switching the plurality of types of code conversion circuits is configured to switch the type of code conversion by microcode. .. 10. The digital signal processing device according to claim 1, wherein at least one digital signal processing means of the plurality of digital signal processing means is an arithmetic circuit using a binary code having an output terminal and an input terminal, and the input A digital signal processing device characterized in that a code converter for converting a gray code into a binary code is connected to a terminal, and a code converter for converting a binary code into a gray code is connected to the output terminal. 11. An analog-digital converter and a memory circuit for storing the output of the analog-digital converter,
In a digital signal processing device having an arithmetic circuit for performing an arithmetic operation using at least one of the output of the analog-digital converter and the output of the memory circuit, the analog-digital converter is a converter that outputs a code having a short Hamming distance. And converting the code having the short Hamming distance into a binary code on the input side of the arithmetic circuit.
A digital signal processing device, to which a code conversion circuit is connected. 12. The digital signal processing device according to claim 11, wherein the code having a short Hamming distance is a Gray code. 13. The digital signal processing device according to claim 11 or 12, wherein the analog-digital converter converts the analog signal into a binary code and a code converter that converts the binary code into a gray code. And a digital signal processing device. 14. The digital signal processing apparatus according to claim 11, 12 or 13, wherein there are a plurality of arithmetic circuits, each arithmetic circuit being an output of itself or another arithmetic circuit, said analog-digital converter or said memory circuit. Of the code signal converted by the first code conversion circuit, the output of the analog-digital converter, the memory circuit, or the output of itself or another arithmetic circuit is delayed by the delay circuit and converted by the first code conversion circuit. Code signal 1
Or, a digital signal processing device characterized by inputting a plurality of inputs. 15. A digital signal processing device comprising a processor having a processing unit for sequentially advancing arithmetic processing by the output of an arithmetic circuit counter, and a memory having a memory circuit for exchanging data with the processing unit via a data bus. In the above, each of the processor and the memory is provided with a paired program counter and a branching register, and a clock line for synchronizing the program counter of the processor and the program counter of the memory between the processor and the memory, A digital signal processing device comprising an address bus for sending data of a branch register of the processor to a branch register of the memory when an address is skipped. 16. A digital signal processing device, comprising a circuit for generating a Gray code address on an address bus in a central processing unit for performing digital calculation.