JP2000242549A - Line memory constructing method and line memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the format conversion and resolution conversion processing of an image signal by a line memory of a small capacity. SOLUTION: This line memory consists of plural line segments and a register group showing the connection information of the line segments, and a line memory 4 needed by each of signal processing parts 1 and 2 to obtain a delay signal is realized by cascading one or more line segments. A register showing the connection information of the line segments consists of leading line segment setting registers 401 and 402 setting line segments to first accessed for the plural parts 1 and 2 and the next line segment setting registers 403 and 404 setting, for the plural line segments, line segments that should next be accessed by the connected parts 1 and 2. Delay circuits and line buffers having various lengths are realized by adopting a line memory configuration having a link structure, and the plural signal processing parts in a signal processing integrated circuit share the shared line memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of configuring a line memory and a line memory, and more particularly to a method of configuring a line memory and a line memory in a large-scale signal processing integrated circuit.

[0002]

2. Description of the Related Art With the spread of digital video media,
A moving image signal processing system has been required to handle various forms of moving images. For example, digital satellite broadcasting using a broadcasting satellite is based on HDTV (HighDefini).
480, mainly for TV
A plurality of formats having different resolutions such as I, 480P, 720P, and 1080I are adopted. In order to display images in these formats after receiving them, it is necessary to perform format conversion according to the display. For image signal processing in the vertical direction, a line memory is used to generate a delay signal for a horizontal line. If a line memory is prepared for each image processing unit, the ratio of the line memory to the circuit scale of the entire signal processing increases. On the other hand, a sharing method in which a selector is inserted into the connection between the signal processing unit and the line memory that are executed exclusively, and the signal processing unit that accesses the common line memory is selected according to the operation mode of the signal processing Has been proposed. Regarding such a sharing method, see, for example, JP-A-8-331.
480 publication.

[0003]

Conventionally, when a line memory is connected to each signal processing unit, it is necessary to provide all necessary line memories independently. In addition, when the line memory is shared by a plurality of signal processing units, it is necessary to prepare a line memory capacity that can simultaneously use the line memory capacity that realizes the maximum delay among the plurality of signal processing units connected to the line memory. was there. All signal processing circuits are LSI
When mounted on a (semiconductor integrated circuit device), there is a problem that the ratio of the line memory to the chip area and power consumption increases. In order to integrate more signal processing circuits into one chip, it is essential to configure a line memory that can be efficiently shared. In order to respond to the demand for higher image quality, it is necessary to increase the number of taps of the filter, and a technology that makes more effective use of the line memory is desired.

An object of the present invention is to optimize the distribution of line memories to each signal processing unit when a plurality of signal processing units share a line memory, thereby minimizing the line memory cost of the plurality of signal processing units as a whole. It is to suppress.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a line memory (hereinafter, referred to as a logical line) required by the signal processing unit is realized by connecting a plurality of line segments individually or in cascade. A head line segment register for setting a line segment to be accessed first for a plurality of signal processing units, and a next line for setting a line segment to be accessed next by a connected signal processing unit for the plurality of line segments A segment setting register and a selector for switching connection between a plurality of signal processing units and line segments are provided, and each signal processing unit selects a line segment to be connected. In the line segment control, the number of line segments to be connected first by the number of signal processes connected to the line memory are connected by a line segment control register controlled by the CPU. According to the read / write control signal of the data output from the signal processing unit, the physical address of the connected line segment is changed, and when the line segment matches the maximum physical address of the line segment, the line segment is changed according to the next line segment register information. Switch line segment connection.

By adopting a line memory configuration having a link structure in this way, delay circuits and line buffers of various lengths are realized, and the line memory is shared by a plurality of signal processing units in the signal processing integrated circuit. By doing so, the overall line memory cost is reduced. An optimal line memory configuration can be provided according to the operation mode.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A line memory according to a first embodiment of the present invention is composed of a plurality of line segments, and each connected signal processing unit has one logic line required to obtain a delay signal. This is realized by cascading the above line segments. A line memory for performing noise reduction, vertical enlargement / reduction processing, format conversion, and the like of an image is collected, and a plurality of line memories are collectively managed to realize a necessary function with a minimum memory capacity.

FIG. 1 shows a first embodiment of the present invention. In FIG. 1, 1 is a first signal processing unit requiring a line memory, 2 is an Nth signal processing unit requiring a line memory (where N is an integer), and 3 is a first embodiment of the present invention. Central processing unit (hereinafter, referred to as CP)
Called U. 4 is a line memory according to the first embodiment of the present invention, 40 is a register for setting connection of a plurality of line segments 44 and 45, and 41 is a line segment selection control signal to be connected to a physical address for the signal processing unit 1. A generation unit 42 selects a line segment to be connected to a physical address for the signal processing unit 2 and a control signal generation unit. N × M selector, 44 is the first line segment, 45 is the Mth
(Where M> 1).

The line memory according to the first embodiment of the present invention is connected to a first signal processing section 1 exemplarily shown as a representative, data S6, and a read / write control signal S7 of the line memory. The control signal S7 is an address increment or a reset signal. The signal processing unit 1 applies the line memory output S of the present invention to the input signal S1.
6 to obtain an output signal S2. The N-th signal processing unit 2 exemplarily shown as a representative includes the data S
8 and a line memory read / write control signal S9. The signal processing unit 2 obtains an output signal S4 for the input signal S3 using the line memory output S8 of the present invention. Although this embodiment is configured to correspond to N signal processing units, the first and Nth signal processing units are exemplarily shown in FIG.

The line segment setting register 40 stores N
N signal registers 401 and 402 provided corresponding to the signal processing units 1 to N for setting a line segment to which the signal processing units 1 and 2 are to be connected first.
, And M registers 403 and 404 which are provided corresponding to the M line segments and set the line segments to be connected next.
In the figure, two registers 401 and 402 are respectively provided.
And 403 and 404 are illustratively shown. The bit width of each register only needs to be able to represent the number M of line segments.

The line segment setting register 40 is connected to the CPU 3 and can be set by software from the CPU 3. Line segment setting register 40
Is a two-block configuration for external writing and internal operation. After updating the head segment of each logical line and link information between line segments by writing data from the CPU 3, the internal operation register
The register value may be updated starting from the vertical synchronization signal.

The physical address / selection control signal generation section 41 of the first signal processing section is connected to the signal processing section 1 and the line segment setting register 40, and outputs a line segment selection control signal S11 to which the signal processing section 1 connects. , The physical address S10 for the selected line segment is generated. The physical address / selection control signal generation section 42 of the Nth signal processing section is connected to the signal processing section 2 and the line segment setting register 40, and is connected to the line segment selection control signal S13 to which the signal processing section 2 is connected. A physical address S12 is generated for the line segment. The other signal processing units (2 to N-1) not shown also include the same physical address / selection control signal generation unit as described above.

FIG. 2 shows the details of the physical address / selection control signal generator 41. In FIG. 2, 411 is a physical address counter, 412 is a line segment selection control signal generator, 413 is a selector for selecting the maximum physical address of the line segment, and 414 is a physical address comparator. The other 2 to N physical address / selection control signal generators are the same as above. The operation of the physical address / selection control signal generator 41 will now be described with reference to the operation flow of FIG.

Physical address / selection control signal generator 41
Is initialized by a reset control signal S7 synchronized with a horizontal synchronization signal of a video signal as a starting point of the operation.
The physical address counter 411 is reset, and the line segment selection signal generator 412 loads the first line segment 401 set in the register (step 1). Here, the selector 413 outputs the maximum physical address of the currently connected line segment according to the loaded first line segment (step 2). Subsequently, the physical address counter 411 increments the physical address according to the line memory control signal S7 input from the connected signal processing unit 1 (Step 3).

The comparator 414 compares the count value of the physical address 411 with the maximum physical address selected by the selector 413 (Step 4). When the address coincides with the maximum address of the currently selected line segment, the physical address counter 411 is reset and the line segment number (403 to 40) set in the next line segment register of the selected line segment.
4) Load (step 5). If the loaded next line segment number is not a zero (NULL) pointer, the operation following the loading of the maximum physical address of the line segment is repeated (step 6).

If the loaded next line segment number is a zero pointer, there is no next line segment, indicating the end of the logical line, and the increment of the physical address is stopped. In the above operation, the physical address / selection control signal generation unit generates a physical address for the line segment and generates a selection control signal indicating which line segment each signal processing unit connects to.

The selector 43 includes a signal processing unit input from the address control units 41 and 42 corresponding to each externally connected signal processing unit and a line segment selection control signal S1.
According to 1, S13, the path of the data, address, and control signal of the signal processing unit and the line segment is switched.
The line segment 44 includes the selector 43 and the data S14,
The line segment 45 is connected to the selector 43 by data S16 and the address and control signal S17.

It is desirable that each line segment can be read and written at the same time.
It can be realized by a RAM. By making the two ports dedicated to read / write, independent operation of read processing and write processing of the same line memory is enabled. However, an access restriction of each signal processing unit is provided so that reading / writing to the same address does not occur at the same timing.

Register 4 in the line memory of the present invention
By switching the connection between the plurality of line segments and the signal processing unit in accordance with the setting of 0, the necessary logic line memories can be realized in the signal processing units 1 to N. All signals from each signal processing unit are connected to the selector 4
By connecting to any one of the first to M-th line segments via 3, each signal processing unit can operate independently.
Also, while sharing the memory, each signal processing unit looks like a single logical line.

Attention is focused on register setting items. Selector 4
No. 3 selects M line segments to be connected to N signal processing units. When all of these combinations are set as registers, N × M settings are required. Line segment setting register 40 according to the present invention
Then, the first line segment of each of the N signal processing units,
Only N + M settings are required for the M line segments to be connected next to each other. The register set according to the present invention can realize an efficient line memory with a small number of setting items when a logical line memory is shared by more signal processing units.

Next, a description will be given, based on the signal processing shown in FIG. 4, of the shared realization of the line memory by a plurality of signal processing units using the line memory according to the first embodiment of the present invention. FIG. 4 shows a simplified part of a digital broadcast receiving circuit. First, it is a series of signal processing for decoding a bit stream encoded by MPEG2, performing a noise removal process, and further performing a format conversion. The operation of sharing the line memory according to the present invention in the noise removal processing and the format conversion processing will be described.

In FIG. 4, 5 is an MPEG2HL decoder, 6 is a noise removal processing unit, 7 is a format conversion unit,
8 is a selector. In the format conversion unit 7,
Reference numerals 71, 73, 75, and 77 denote selectors, reference numeral 72 denotes a horizontal resolution conversion unit that performs horizontal enlargement or reduction processing, reference numeral 74 denotes a line buffer for synchronous conversion when the input bit stream and the output signal are different in synchronization, and reference numeral 76 denotes a vertical buffer. This is a vertical resolution conversion unit that performs enlargement or reduction processing in the direction.

In the noise removal processing unit 6, block distortion generated at the boundary between a coded macro block and DCT block in the image signal encoded by MPEG2, or the high frequency component of the image signal is roughly quantized, Refers to a filter that removes ringing noise (mosquito noise) seen near the edge of. For example,
In order to operate as a block distortion removal filter, a change in pixel value at a block boundary position is calculated, and a portion that is determined to have large block distortion is adaptively subjected to a noise removal filter. These noise reduction filters can be realized by using a local operation unit. Here, briefly,
It is assumed that filtering of three taps is performed vertically. In this case, a delay circuit for two horizontal lines is required.

In the format conversion section 7, selectors 71, 73, 75, and 77 for switching the connection between the horizontal resolution conversion section 72, the synchronous conversion line buffer 74, and the vertical resolution conversion section 76 in accordance with the image enlargement / reduction processing. Switch appropriately. The path of the signal passing through the format conversion unit 7 is set such that the line memory for obtaining the delay signal is minimized.
For example, in the case of horizontal enlargement and vertical enlargement, it is desirable to set the synchronous conversion line buffer 74, the vertical resolution converter 76, and the horizontal resolution converter 72 in this order. In the case of horizontal reduction and vertical enlargement, it is desirable to set the horizontal resolution converter 72, the synchronous conversion line buffer 74, and the vertical resolution converter 76 in this order. In the case of horizontal enlargement and vertical reduction, it is desirable to set the vertical resolution converter 76, the synchronous conversion line buffer 74, and the horizontal resolution converter 72 in this order. In the case of horizontal reduction and vertical reduction, it is desirable to set the horizontal resolution converter 72, the vertical resolution converter 76, and the synchronous conversion line buffer 74 in this order.

Among them, a line memory for obtaining a delay signal of a horizontal line in the vertical resolution converter 76 is required. The line buffer 74 is constituted by a line memory, and performs synchronous conversion by controlling the memory write in synchronization with the MPEG decode signal and controlling the memory read in accordance with the synchronization of the display system. The selector 8 switches between an output signal of the noise removal processing unit 6 and an output signal of the format conversion unit 7. When the decoding signal of the decoder 5 is the same as the synchronization of the display system, the format conversion unit 7 is made to pass through.

FIG. 5 shows the details of the connection relation of the blocks requiring the line memory in the above processing unit. Here, for the sake of simplicity, only the luminance signal is shown, the noise removal processing unit 6 performs signal processing of three vertical lines, and the format conversion unit 7 performs scaling processing using data of four vertical lines. In FIG. 5, 61, 62, 731, 732,
733 is a delay circuit for obtaining a delay signal of a horizontal line. 63 is a local operation unit, and 734 is a vertical filter. In FIG. 5, the connection with the line memory 4 of the present invention is indicated by a dotted line, indicating that there is no signal exchange in the operation mode.

In FIG. 5, it is assumed that 1920 pixels in the horizontal direction and 1080 vertical lines (referred to as 1080I) of the interlaced scanning system are used as the output of the signal processing. First, as (A) mode 1, 1920 horizontal pixels and 1 vertical
A processing path is assumed in which a 080-line decoded image is input, the noise is removed by the noise removal processing unit 6, and then the data is output through the format conversion unit 7.

(B) Mode 2, horizontal 720 pixels,
After the decoded image of 480 vertical lines of the interlaced scanning system is input and the noise is removed by the noise removal processing unit 6, the format conversion unit 7 extends the horizontal and vertical directions to 1920 pixels horizontally and 1080 vertical lines of the interlaced scanning system. Suppose. In the figure, 61, 62, 731, 732, 733, 74
The numbers described therein indicate the required line memory capacity (bytes) of each delay circuit.

The line memory required for the signal processing of FIG.
In the line memory configuration according to the present invention, six 720-byte line segments may be prepared. These are represented by line segments # 1 to # 6, respectively. In the block diagram of FIG. 1, M = 6. Further, the signal processing units requiring line memories include 61, 62, 731, 732, 733, 7
There are six of four. That is, N = 6 in the block diagram of FIG.

Tables 1 and 2 show the line segment settings according to the operation modes in this case. FIG. 6 shows a method of realizing the delay line 61 in the operation mode 1 by using line segments, and FIG. 7 shows a method of realizing the delay circuit 731 in operation mode 2 by using line segments. In FIG. 6, two 1920-byte logical lines are divided into 720-byte line segments # 1, # 2,
This is realized by cascading # 3 and # 4, # 5, and # 6, respectively. In FIG. 7, six logical lines of 720 bytes are converted into line segments # 1 and # of 720 bytes.
This is realized by using each of # 2, # 3, # 4, # 5, and # 6 independently. In the line memory of the present invention, 72
Line memories having different lengths, such as 0 bytes and 1920 bytes, are realized by using line segments alone or by cascade connection. If attention is paid to each line segment, it is used as a line memory for different signal processing depending on the operation mode.

As described above, in the operation mode in which the use state of the line memory is different, the line segment register 4
It can be seen that a logical line memory required by a plurality of signal processing units can be realized only by changing the setting of 0.

[0032]

[0033]

The total line memory capacity when line memories are independently arranged in each signal processing unit is 1920 bytes × 2
It is 6720 bytes of (line + 720 bytes x 4 lines). Also, in the case of switching the line memory by the conventional simple selector, similarly, 1920 bytes × 2 lines +
720 bytes x 4 lines of 6720 bytes are required.
In the line memory configuration according to the present invention, 4320 bytes of 720 × 6 lines are sufficient. By setting the line segment more finely, it is possible to further reduce the capacity of the line memory.

A second embodiment of the present invention will be described with reference to FIGS. FIG. 8 is a block diagram of a line memory according to the second embodiment of the present invention. Compared to the line memory of the first embodiment shown in FIG. 1, a selector 46 for switching head line segment information, an L-th line segment setting register (where L> 1 is an integer) 40 of a first line memory request unit
5 has been added. The selector 46 sets one of the registers 401 and 404 indicating the head of the logical line to the head line segment selection control signal S18 from the signal processing unit 1.
Switch according to. By adding the head line segment selection control signal S18, a plurality of logical lines
Access is enabled by system data S6 and control signal S7.

In the case of the present embodiment, the operation of generating the physical address in the physical address / selection control signal generator 41 is the first operation.
However, the switching of the line segment is also performed when the control signal S18 is changed in addition to the change of the physical address to the maximum address of the currently connected line segment. In this case, since the address of the logical line becomes 0, the physical address is reset to 0, and further, a register value indicating the leading line segment of the next logical line is loaded.

The operation of the line memory according to the second embodiment of the present invention will be described with reference to FIG. The signal processing will be described using a format converter as an example. In FIG. 9, reference numeral 735 denotes line memory write control units 735 and 736 for selectively controlling which delay circuit receives an input signal.
The input signal is written (S61) to one selected logical line memory by the write control unit 735 according to one set of control signals S71. Since the filter unit 734 needs all of the delay signals to read the line memory, the read operation is performed from three logical lines by three sets of control signals S72, S73, and S74 (S62, S63, and S64).
I do. In the filter unit 734, the memory write control unit 7
The delay time of the output signal of each logic line is determined based on the memory write control signal S18 input from the CPU 35, and the filtering process is performed.

In the vertical resolution converter 73 of the format converter 7 shown in FIG. 5, the output signal of the delay circuit 731 is sent to the delay circuit 732 and the output signal of the delay circuit 732 is sent to the delay circuit 7.
In contrast, in the present embodiment shown in FIG. 9, if a delay circuit for inputting the output of the synchronous conversion line buffer 74 is selected, only one system is required for writing to the three delay circuits. A plurality of logic lines can be accessed by one control signal. Unnecessary read / write operations to the line memory can be eliminated.

The operation and effect obtained from the above embodiment are as follows. (1) A plurality of line segments connected to signal processing means and a register for setting connection information of the plurality of line segments are used, and the plurality of line segments are singly or cascaded according to the connection information set in the register. By connecting, by configuring the logical line memory required by the signal processing means, delay circuits and line buffers of various lengths can be realized, and a plurality of signal processing units in the signal processing integrated circuit can be realized. In this case, it is possible to achieve the effect that the line memory can be realized using a small-scale circuit.

(2) The register for setting the connection information of the line segment includes a line segment number indicating the head of the logical line memory of the plurality of signal processing means, and a line segment cascaded next to the plurality of line segments. By recording the numbers, it is possible to obtain an effect that delay circuits and line buffers of various lengths can be realized by software.

(3) When the register for setting the connection information of the line segment is a zero pointer, by processing as the end of the logical line memory, it is possible to make a determination based on the same information including the presence / absence of connection. Can be easily determined.

(4) A plurality of line segments selectively connected to the signal processing means via a selector, and a register for setting connection information of the plurality of line segments, wherein the connection information held in the register is provided. Realizing delay circuits and line buffers of various lengths by configuring the logical line memory required by the signal processing means by controlling the selector according to Therefore, an effect is obtained that a line memory in a plurality of signal processing units in a signal processing integrated circuit can be realized using a small-scale circuit.

(5) As a register for setting the connection information of the line segment, a line segment number indicating the head of a logical line memory of a plurality of signal processing means, and a line segment number cascaded next to the plurality of line segments By using the above, it is possible to obtain an effect that each line segment is set as a minimum unit and can be used in all combinations.

The embodiments of the present invention have been described above in detail. As described above, by applying the present invention to image signal processing, line memories of different lengths that can be shared by a plurality of signal processing units can be efficiently realized. Further, a highly flexible line memory configuration according to various operation modes can be realized.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. In the above-described embodiment, as the signal processing unit using the line memory, the case of the image noise removal processing and the resolution conversion processing has been described. However, the signal processing unit is not limited to this combination of signal processing, and may be combined with other signal processing. The same applies to the case where Further, the method of realizing the line segments is not particularly limited, and a method using an SRAM or a combination of flip-flops may be used.

[0046]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, using a plurality of line segments connected to the signal processing means and a register for setting connection information of the plurality of line segments, connecting the plurality of line segments individually or in cascade according to the connection information set in the register By configuring the logic line memory required by the signal processing means, delay circuits and line buffers of various lengths can be realized, and a plurality of signal processing units in the signal processing integrated circuit can be used. Can be realized using a small-scale circuit.

That is, in the line memory configuration method of the present invention, (1) a line memory having a different length can be realized for a signal processing unit to be connected, and (2) a line memory for a plurality of signal processing units can be realized. Sharing is possible, and (3) the line memory capacity to be shared can be reduced, so that cost reduction and circuit power consumption can be achieved by reducing the circuit scale. Further, with the line segment connection setting register according to the present invention, a circuit system having a high degree of freedom can be configured with a small number of registers. That is, it is possible to cope with many operation modes of signal processing, and to easily cope with a change in system specifications.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a line memory according to the present invention.

FIG. 2 is a diagram showing a first physical address / selection control signal generator of FIG. 1;

FIG. 3 is an operation flowchart example of the first embodiment of the line memory according to the present invention;

FIG. 4 is a block diagram showing signal processing including the first embodiment of the line memory according to the present invention.

FIG. 5 is a block diagram showing details of connection between a line memory and a signal processing unit according to the present invention in FIG. 4;

FIG. 6 is a diagram showing a first example of a line memory segment of the first embodiment of the line memory according to the present invention.

FIG. 7 is a diagram showing a second example of the line memory segment of the first embodiment of the line memory according to the present invention;

FIG. 8 is a block diagram showing a second embodiment of the line memory according to the present invention.

FIG. 9 is a block diagram showing details of connection between a second embodiment of the line memory according to the present invention and a signal processing unit.

[Explanation of symbols]

1 ... first signal processing unit, 2 ... Nth signal processing unit, 3 ... C
PU, 4 ... line memory, 40 ... line segment setting register, 41 ... first physical address / selection control signal generator, 42 ... Nth physical address / selection control signal generator, 43 ... data / address / control signal Selector, 44
... first line segment, 45 ... Mth line segment, 401 ... first line segment setting register of first signal processing unit, 402 ... first line segment setting register of Nth signal processing unit, 403 ... first Next line segment setting register of the line segment, 404... Next line segment setting register of the Mth line segment, 405... Lth first line segment setting register of the first line memory request unit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koichi Ono 5-2-1, Josuihoncho, Kodaira-shi, Tokyo F-term in the System LSI Development Center of Hitachi, Ltd. (Reference) 5B047 AA30 EA05 5B060 AB08 AC13 GA00 GA06 5F083 BS00 LA06 ZA13

Claims (5)

[Claims] 1. A plurality of line segments connected to signal processing means, and a register for setting connection information of the plurality of line segments, wherein the plurality of line segments are stored in accordance with the connection information set in the register. A method for configuring a line memory, wherein a logical line memory required by the signal processing means is configured by being connected alone or in cascade. 2. The register according to claim 1, wherein the register for setting connection information of the line segment includes a line segment number indicating a head of a logical line memory of a plurality of signal processing means, and a cascade connection next to the plurality of line segments. A line segment number to be recorded. 3. The line memory configuration according to claim 1, wherein when the register for setting the connection information of the line segment is a zero pointer, processing is performed as the last of the logical line memory. Law. 4. A system comprising: a plurality of line segments selectively connected to a signal processing unit via a selector; and a register for setting connection information of the plurality of line segments, according to the connection information held in the register. A line memory comprising a logical line memory required by the signal processing means by controlling the selector and connecting the plurality of line segments individually or in cascade. 5. The register according to claim 4, wherein the register for setting the connection information of the line segment is cascaded next to the line segment number indicating the head of the logical line memory of the plurality of signal processing means and the plurality of line segments. A line segment number for recording the line segment number.