JPH11317962A - Data storage method and data transfer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the data transfer circuit that image data or the like are transferred between memories by using an address counter circuit whose scale is less than a half in comparison with a conventional circuit. SOLUTION: The data transfer circuit that transfers data between memories or from a memory to other circuit is provided with at least one address counter circuit (a) and an address rearrangement device (c) that rearranges counts of the address counter circuit (a) and that provides an output to an address input terminal of the memory, and also with a mode selection circuit (e). The address rearrangement device (c) changes combinations of address rearrangement methods and its operating timing under the control of the mode selection circuit (e). Furthermore, the address counter circuit (a) is externally preset.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage method and a data transfer circuit, and more particularly to a method for storing input image data in a frame memory or detecting a motion vector in an MPEG-compliant encoding system. The present invention relates to a technique effective when applied to data transfer of image data from a memory.

[0002]

BACKGROUND OF THE INVENTION MPEG (M oving P ictur
e E xperts G roup) encoding system is moving image data (hereinafter, simply referred to as an image. aims at efficient image compression), is detected as a motion vector the motion of the image due to aging, coding for image compression Used as coefficients. Since this motion vector is detected by comparing between frames or between fields of an image, M
In the PEG encoding system, an image of several frames is always held, and an I picture image (Int
ra coded Picture) and P-picture image (Predictive coded Picture)
re) and a B-picture image (Bidirectionally Predicti) serving as comparison source data.
ve Coded Picture) and P-picture image must be supplied to the motion vector detection circuit at the same timing. In this case, the image is a macroblock of 16 × 16 pixels (hereinafter referred to as “M”) in accordance with the MPEG coding unit with respect to the image input by the interlace method.
Called B. ) Units must be used. Apart from this, the original image to be compressed must be rearranged as a block of 8 × 8 pixels in DCT (discrete cosine transform) units and supplied to a DCT processing circuit. Normally, each pixel (one pixel) of an image has 8-bit width luminance information (Y) and 8-bit width color difference information (Cb (= B (blue) −
Y) and Cr (= R (red) -Y)).

FIG. 17 is a diagram showing a data arrangement of an input image, an original image to be compressed, and an image for detecting a motion vector in the MPEG encoding system. FIG. 17A shows an input image, in which one frame is composed of a top field (Top Field) and a bottom field (Bottom Field) by interlaced input, and the image input order in one field is from left to right. , From top to bottom. FIG.
7 (b) is an original image to be subjected to compression processing at the time of encoding, and treats 64 pixels of 8 × 8 pixels as a DCT unit as one unit. Therefore, the image at this time has a data array in which top fields and bottom fields are alternately combined in line units, that is, 8 × 4 pixels of the top field of the input image shown in FIG. 8x4
It is necessary to form a data array in which pixels are combined. Since image processing in DCT units needs to be processed in order in MB units, it is necessary to process in numerical order shown in FIG. 17B. FIG. 17C shows an image for detecting a motion vector, which is used as a compression coefficient of an original image for encoding that is subjected to compression processing in MB units. Therefore, similarly, a top field and a bottom field are alternately combined. ,
Processing is performed with 256 pixels of 16 × 16 pixels as one unit.

FIG. 18 is a block diagram showing an example of a connection configuration of each memory in the MPEG encoding system. As the input image, in the case of the NTSC system, one frame of image data is input line-sequentially every 1/30 second. The image is temporarily stored in the frame memory (d), read out,
Alternatively, the data array is read out in a desired array when data is transferred between memories, thereby generating the above-described data array defined by the MPEG standard. Here, the frame memory (d) needs a capacity capable of holding image data of several frames before and after to be compared when detecting a motion vector. The encoding of the original image by the encoder (encoding unit) (n), the detection of the motion vector by the motion vector detection circuit (m), and the writing of the input image to the frame memory (d) are performed simultaneously. Therefore,
The input image is stored in a frame memory (d), and the image stored in the frame memory (d) is stored in an encoder (n).
Alternatively, it is necessary to repeat the transfer to the motion vector detection circuit (m). However, for simplification of the system, the data bus (l) is shared, and a buffer memory (j) of a FIFO (first-in first-out) system for rate conversion is provided for each. The writing and reading of the image to and from the frame memory (d) are devised such that the image is transferred at a rate several times that at the time of inputting the image. In addition, a memory (hereinafter, referred to as a reference memory) (k) for holding reference data for detecting a motion vector in the motion vector detection circuit (m) is required. It is necessary to transfer data for one frame of an I picture or a P picture.

[0005] The storage format of the input image is a (4: 2: 0) format in units of macro blocks according to the MPEG standard. The (4: 2: 0) format based on MPEG is shown in FIG.
As shown in (a), 1 MB is a unit of 16 × 16 pixels composed of four pieces of luminance information (Y) and luminance information (Y).
Has two pieces of color difference information (Cb, Cr) in 8 × 8 pixel units reduced (or decimated) to 2: 1 half pixels horizontally and vertically. Therefore, the input data to the encoder (n) is as shown in FIG.

In order to encode these MBs in accordance with the MPEG standard, as shown in FIG. 20, first, a DCT block of luminance information (Y) of 16 × 16 pixels and a color difference of 8 × 8 pixels are used. Information (Cb) and the DCT block of the information (Cb) at the same time.
DC of block 2 and color difference information (Cr) of 8 × 8 pixels
The encoding process is performed simultaneously with the T block. Therefore, 1
DCT blocks 3 and 4 of the luminance information (Y) of 6 × 16 pixels are subjected to the encoding processing of the luminance information (Y) only. By repeatedly performing the above-described processing in MB units, a moving image can be subjected to real-time compression processing. Therefore, in order to perform the above-described processing by following the input speed of the moving image data, the frame memory (d) must be set so that the image data can be output to the encoder (n) in the (4: 2: 0) format described above. It is necessary to convert the data array in advance.

[0007]

Conventionally, an inexpensive DRAM memory is used as a frame memory (d) for temporarily storing an input image, and the operations of a memory as a transfer source and a memory as a transfer destination are synchronized. In addition, each address is individually controlled in accordance with the required image data arrangement. However, in the conventional method, an image for detecting a forward or backward motion vector and an original image to be compressed are arbitrarily written while an input image to be input one after another is written into a frame memory (d). It was necessary to read alternately for each MB unit, and to achieve this, high-speed memory control and hardware were required.

FIG. 21 is a block diagram showing a schematic hardware configuration for transferring image data from the frame memory (d) in the conventional method. As shown in the figure,
In the conventional method, for each frame memory (d), each address of a row (Row) / column (Column) having a different drive timing is stored in a dedicated address counter circuit (g, g) controlled by a timing control circuit (i). h), the image data is transferred in synchronization with the drive timing. In this case, the address counter circuit (g, h) requires a large number of gates when constituted by a logic circuit. In particular, in order to handle a VGA class image size, a row address, In addition, it is necessary to provide a counter of 9 bits or more for each column address, and a logic circuit of thousands to 10,000 gates is required only by the address counter circuit (g, h), which hinders hardware compactness and cost reduction. Had become. In order to support a plurality of transfer modes, it is necessary to control each address independently. Therefore, the address counter circuit (g, h)
Had a problem that the scale was further increased.

Further, as described above, in order to be able to output image data in the (4: 2: 0) format to the encoder (n), it is necessary to previously convert the data array in the frame memory (d). However, there have conventionally been two methods as this method. In the first method, as shown in FIG. 22, when chrominance information (data) is taken into a buffer memory (j) of the FIFO system for inputting chrominance information, the chrominance information (Cb) and the chrominance information (Cr) are set to 1 The pixel data is written alternately for each pixel, and thereafter, the rate is changed and the luminance information (Y) is stored in the lower byte of the frame memory (d) and the color difference information (Cb, C
r). As a result, the color difference information (Cb, Cr) is alternately arranged in pixel units in the upper byte area of the frame memory (d), so that the data transfer from the frame memory (d) to the encoder (n) requires After the color difference information (Cb) is transferred to the encoding FIFO buffer memory (j) at the same time as the information (Y), only the color difference information (Cr) is transferred again, so that the data is stored in the FIFO buffer memory (j). Therefore, the procedure of arranging in MB was performed.

The second method is a method of preparing separate frame memories for luminance information (Y) and color difference information (Cb, Cr) as shown in FIG. In this method, when all data of the color difference information (Cb, Cr) is temporarily stored in the frame memory (d) and transferred to the buffer memory (j) of the FIFO method for encoding, the MB array conforms to MPEG. Thus, the reading of the frame memory (d) is controlled.

However, in the first method of the conventional data array conversion, since data must be transferred twice, the data bus (l) is occupied for a longer time, and the data transfer period to another device is reduced. There was a problem that squeezed. In this case, since the image size that can be processed is limited by the data transfer time, a system that performs high-speed transfer between the memories is necessary. However, this causes a problem that the system becomes expensive and the cost increases. There were also points. In the second method in the conventional data array conversion,
Although the image data can be transferred at one time, the address must be controlled for each frame memory (d), the control circuit becomes large due to the complicated address management, and the number of memories increases. There was a problem of doing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a data storage method in which luminance information (Y) and color difference information (Cb, Cr) of an input image are provided. ) Can be easily stored in a frame memory in a predetermined format. It is another object of the present invention to provide a technology that enables transfer of image data and the like between memories by using an address counter circuit that is half or less than that of the conventional example.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, the present invention provides a method of storing, in a memory, luminance information of an input frame image and a plurality of pieces of color difference information of the input frame image, the plurality of pieces of color difference information having an information amount reduced as compared to the luminance information. In the storing method, when writing the luminance information to the memory, the luminance information and the plural color difference information are written by alternately writing the plural pieces of color difference information to the memory every predetermined number of pixels.
The data is stored in the memory in a predetermined arrangement.
Further, the present invention provides a method for storing, in a memory, luminance information of an input frame image and a plurality of pieces of color difference information of the input frame image, the plurality of pieces of color difference information having an information amount reduced as compared with the luminance information. In the storage method, when writing the luminance information to the memory, the plurality of color difference information is alternately written to the memory for each predetermined number of pixels, and the plurality of color difference information is written to the memory, and The non-writing of a plurality of pieces of color difference information into the memory is repeated for each predetermined number of lines, so that the luminance information and the plurality of pieces of color difference information are stored in the memory in a predetermined arrangement. The present invention also provides a data storage method for storing luminance information of an input frame image and a plurality of color difference information in a memory, wherein the luminance information and the plurality of color difference information of the input frame image are stored in a buffer memory at different frequencies. When writing and reading the luminance information from the buffer memory and writing to the memory, the plurality of color difference information is alternately read from the buffer memory for each predetermined number of pixels and written to the memory, so that the luminance information and the plurality of color difference The information is stored in the memory in a predetermined arrangement. The present invention also provides a data storage method for storing luminance information of an input frame image and a plurality of color difference information in a memory, wherein the luminance information and the plurality of color difference information of the input frame image are stored in a buffer memory at different frequencies. Writing, when reading the luminance information from the buffer memory and writing to the memory, the plurality of color difference information is alternately read from the buffer memory for each predetermined number of pixels and written to the memory, and the plurality of color difference information By repeating reading from the buffer memory and stopping reading of the plurality of pieces of color difference information from the buffer memory for each predetermined number of lines, the luminance information and the plurality of pieces of color difference information are arranged in the memory in a predetermined array. Is stored. Further, the present invention is characterized in that the plurality of color difference information and the luminance information are stored in upper bits and lower bits of the same address of the memory, respectively. Further, according to the present invention, the memory is a memory in which input or output of information is performed in synchronization with a clock, and a memory having a plurality of memory arrays, wherein brightness information of the input frame image in a first direction is provided. A plurality of pieces of color difference information are continuously stored by switching the memory array of the memory, and the luminance information and the plurality of pieces of color difference information of the input image in the second direction are switched to the memory by switching addresses. It is stored. Further, according to the present invention, the input frame image includes a first field image and a second field image, and luminance information and a plurality of pieces of color difference information of the first field image in a second direction are stored in the memory. In the first area, the luminance information and the plurality of pieces of color difference information of the second field image in the second direction are:
It is stored in a second area of the memory.

In another aspect of the present invention, in a data transfer circuit for transferring data between memories or from a memory to another circuit, at least one address counter circuit and a count value of the address counter circuit are rearranged, and And an address rearranging device for outputting to the address input terminal. Also, the present invention
The address counter circuit can be preset from the outside. Further, the present invention is characterized in that the operation of the address rearrangement device and the combination of the rearrangement of the addresses can be changed by external control. Further, the present invention further includes a mode selection circuit, wherein the address rearrangement device can change a combination of its operation timing and address rearrangement under the control of the mode selection circuit. Features. Further, the present invention is characterized in that the mode selection circuit controls a combination of the operation timing of the address rearranging device and the rearrangement of addresses based on data transferred from the outside. Further, the present invention is characterized in that the address rearranging device generates a row address and a column address of an address multiplexer type memory. Further, the present invention is characterized in that the memory is a memory that inputs or outputs information in synchronization with a clock and has a plurality of memory arrays.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

FIG. 1 is a block diagram showing a schematic configuration of a data transfer circuit according to an embodiment of the present invention. In the figure, a is an address counter circuit (binary counter), b is a register storing a base address, c is an address rearranging device (hereinafter, referred to as an address scrambler circuit), d is a frame memory, and e is a frame memory. Mode selection circuit, f
Denotes a microcomputer, and l denotes an image data bus. In the present embodiment, the frame memory (d) for image storage shown in FIG. 1 has a row address of 9 bits, a column address of 8 bits,
A 4-Mbit synchronous DRAM (hereinafter referred to as SDRAM) with 1-bit memory bank control and 16-bit width I / O
Called. ). In this case, this SDRAM
Has a burst length of 8 bits, so the lower 3 bits of the column address become unnecessary. Therefore, the address counter circuit (a) only needs to sequentially count up 1 bit of the memory bank control of the SDRAM, 9 bits of the row address, and 5 bits of the column address. Therefore, the address counter circuit (a) may have 15 bits.

Here, the address counter circuit (a)
Is a presettable type, and the address counter circuit (a) is preset by a microcomputer (f)
Sends the base address to a register (b) via an address bus, and sets the base address in an address counter circuit (a). The data on the data bus output simultaneously from the microcomputer (f) is treated as an instruction for mode selection and the like, the instruction is decoded by the mode selection circuit (e), the transfer mode and the frame memory (d) are selected, and the address input is performed. Perform timing control. The address scrambler circuit (c) is a switch for selecting which bit of the 15-bit counter value output from the address counter circuit (a) is to be selected according to the transfer mode and the timing. It is executed under the control of the selection circuit (e).

The operation of the present embodiment will be described below with reference to an example of motion vector detection and compression image data transfer from the frame memory (d). FIG. 2 is a block diagram showing a schematic configuration of an example of an SDRAM used as a frame memory (d) for storing images in the present embodiment. The SDRAM shown in FIG. 1 is not particularly limited, but is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. The SDRAM shown in FIG. 1 includes a memory array 301A forming a memory bank 1 and a memory array 301B forming a memory bank 2. Each of the memory arrays (3
01A, 301B) include dynamic memory cells arranged in a matrix. Select terminals of memory cells arranged in the same row are connected to word lines of each row, and data input / output terminals of memory cells arranged in the same column are connected to complementary data lines of each column. One of the complementary data lines is driven to a selected level in accordance with the result of decoding the row address by the row address decoder (302A, 302B).

A sense amplifier and a column selection circuit (304)
A, 304B) detects and amplifies a small potential difference generated in each complementary data line by reading data from the memory cell. The sense amplifier and the column selection circuit of the column selection circuit (304A, 304B) individually select complementary data lines and connect them to the complementary common data lines.
This column selection circuit includes a column decoder (303A, 303B)
Is selected according to the result of decoding the column address. The complementary common data line is connected to the input buffer 309
And the input terminal of the output buffer 308. An input terminal of the input buffer 309 and an output terminal of the output buffer 308 are connected to a data output terminal (I / O).

A row address or a column address input from an address input terminal (Adin) is fetched and held in a multiplex format by a row address buffer 306 and a column address buffer 305. The output of the column address buffer 305 is supplied to the column address counter 307 as preset data of the column address counter 307. The column address counter 307 stores the preset data,
Alternatively, data obtained by sequentially incrementing the preset data is supplied to a column address decoder (303A, 303B) as a column address.

The controller 310 includes an address signal, a clock signal (CLK), and a chip select signal (/ CS) (symbol //) input from an address input terminal (Adin).
Means that the signal to which this is attached is a row enable signal. ), Row address strobe signal (/ R
AS), an external control signal such as a column address trobe signal (/ CAS) is input, and an internal timing for controlling the operation mode of the SDRAM or the operation of each of the circuit blocks based on the level change and timing of these signals. Form a signal.

In this embodiment, each frame memory (d) stores input image data inputted by sequential scanning in units of frames. In this case, FIG.
As shown in (1), image data in the horizontal direction of an input image (input image for each line) is continuously stored with a burst length of 8 in the column direction of the SDRAM by alternately switching between memory banks 1 and 2. Are stored by switching the row address in the vertical direction. That is, 0th to 7th of the input image of the first line of the top field
The pixel at the (0,0,0,0,0,0,0,0,0,
In the row address 0), the burst length is 8 in the SDRAM column direction and stored in the memory bank 1. The eighth through fifteenth pixels have the burst length 8 in the SDRAM column direction and are stored in the memory bank 2. Similarly, the pixels of the input image of the first line of the top field are sequentially stored in the memory bank 1 and the memory bank 2 in the same manner. Here, in the present embodiment, since the number of pixels per field is 240 × 512 pixels, the 496th to 496th pixels of the input image of the first line of the top field are input.
The 03rd pixel has a burst length of 8 in the SDRAM column direction and is stored in the memory bank 1. The 504th through 511th pixels have a burst length of 8 in the SDRAM column direction and is stored in the memory bank 2. Is stored. Also, the 0th to 7th of the input image of the next one line after the top field
The pixel switches the row address to (0, 0,
0, 0, 0, 0, 0, 0, 1), the memory bank 1 and the memory bank 2 have a burst length of 8 in the column direction of the SDRAM, similarly to the input image of the first line. It is stored alternately and continuously. further,
The input image of each bottom-filled line is (0, 1,
1, 1, 0, 1, 1, 1, 1) and, similarly to the above-mentioned top field, by alternately switching the memory bank 1 and the memory bank 2 with a burst length of 8 in the column direction of the SDRAM. It is stored continuously.

FIG. 4 shows an address transition of a row address and a column address when a data array for detecting a motion vector is generated in this embodiment.
5 is a table showing the address transition of row addresses and column addresses when a data array of a compression image is generated in the present embodiment. 4 and 5, the order of transition of the transfer address changes from top to bottom, and the burst length is 8 on the frame memory side, so the increment does not require the lower 3 bits of the column address.

FIG. 6 shows each address value shown in FIG.
Address order shown in (a) (row address A7 → A6 → A
5 → A4 → A3 → column address A7 → A6 → A5 → A4
→ A3 → A2 of row address → A1 → A0 → A8 → SDR
It is a table showing the change of each address value when rearranged from the upper bits in the order of A9 in the memory bank control of AM). As can be seen from the table shown in FIG. 6, in the present embodiment, when a data array for detecting a motion vector is generated, a row address and a column address are combined by one 15-bit address counter circuit (a). , Row and column addresses can be incremented. FIG. 7B shows each pixel in the 16 × 16 pixel MB (which is a unit of motion vector detection of MPEG) read out by the address transition of the row address and the column address shown in FIG. The MB is 256
It is composed of (= 16 × 16) pixels. In this embodiment, the number of pixels per frame is 480 × 5.
Since there are 12 pixels, 960 MBs are generated.

FIG. 8 shows each address value shown in FIG.
Address order shown in (a) (row address A7 → A6 → A
5 → A4 → A3 → column address A7 → A6 → A5 → A4
It is a table showing the transition of each address value when rearranged from the upper bits in the order of → A3 → A2 of row address → A9 of memory bank control of SDRAM → A1 of row address → A0 → A8. As can be seen from the table shown in FIG. 8, in the present embodiment, when a data array of a compression image is generated, one address counter circuit (a) of 15 bits including a row address and a column address is used. Row and column addresses can be incremented.
FIG. 9B shows an arrangement of each pixel in 8 × 8 pixels (this is a unit of DCT of MPEG) read by the address transition of the row address and the column address shown in FIG. . In FIG. 9B, the sub transition occurs due to the address transition of the row address and the column address shown in FIG.
The data is read from the frame memory (d) in the order of MB1, subMB2, subMB3, and subMB4.

As described above, in this embodiment, even when a data array for detecting a motion vector or a data array for a compression image is generated, one 15-bit address counter circuit (a) is used. Can be used to increment the row and column addresses. That is, in the present embodiment, an address scrambler circuit (c) is provided between a frame memory (d) having nine address pins and a 15-bit address counter circuit (a), and the address scrambler circuit (c) is provided. c)
Under the control of the mode selection circuit (e),
By appropriately selecting a 15-bit counter value output from the address counter circuit (a) according to the row address input and the column address input, and inputting it to the address input terminal of the frame memory (d), FIG. And FIG.
Address transition.

FIGS. 10 and 11 are schematic diagrams for explaining the operation of the address scrambler circuit (c) of the present embodiment. FIG. 10A shows an address scrambler circuit (c) at the time of inputting a row address when a data array for detecting a motion vector is generated in the present embodiment.
FIG. 10B shows the switching of the address scrambler circuit (c) at the time of inputting a column address when generating a data array for detecting a motion vector in the present embodiment. That is, the address scrambler circuit (c) operates at the timing when a row address is required by using a 15-bit address counter circuit (a).
Is input to the address input terminal of A9 of the frame memory (d), and the C1 bit is input to A of the frame memory (d).
8 to the address input terminals C0 to C4 to the address input terminals A0 to A2 of the frame memory (d).
14 to the address input terminals A3 to A7 of the frame memory (d). Also, at the timing when a column address is required, a 15-bit address counter circuit (a)
Are input to the address input terminal of A9 of the frame memory (d), and C5 to C9 are input to A of the frame memory (d).
3 to A7, and "Low level" to the address input terminals A0 to A2 and A8 of the frame memory (d).

FIG. 11A shows the structure of this embodiment.
FIG. 10B shows the switching of the address scrambler circuit (c) at the time of inputting the row address in the case of generating the data array of the image for compression. This shows the switching of the address scrambler circuit (c) when the column address is input. That is, the address scrambler circuit (c) outputs 1 at the timing when a row address is required.
The C0 bit of the 5-bit address counter circuit (a) is set to the A8 address input terminal of the frame memory (d), C1 and C2 are set to the A0 and A1 address input terminals of the frame memory (d), and the C3 bit is set to the frame memory. C4 is connected to the address input terminal A9 of the memory (d), and C10 to C1 is connected to the address input terminal A2 of the frame memory (d).
4 is input to the address input terminals A3 to A7 of the frame memory (d). At the timing when a column address is required, the C3 bit of the 15-bit address counter circuit (a) is input to the address input terminal of A9 of the frame memory (d), and C5 to C9 are input to A3 of the frame memory (d).
To the address input terminals A7 to A7, and "Low level" is input to the address input terminals A0 to A2 and A8 of the frame memory (d). As described above, in the present embodiment, the transition of the column address / row address of the transfer source frame memory (d) is performed by incrementing one address counter circuit (a), and the address required in each transfer mode is changed. In order to make a transition, one address scrambler circuit (c) is switched with good timing under the control of the mode selection circuit (e) in accordance with the data transfer mode, the row address input, and the column address input. The address transition shown in FIGS. 4 and 5 can be performed. In the burst mode, the selected address of the frame memory (d) need only be the head address of each burst, so that the number of bit digits of the address counter circuit (a) can be reduced. The address scrambler circuit (c) includes a logic circuit (for example, an AND circuit),
Alternatively, it can be constituted by a multiplexer or the like, but it is also possible to use a mechanical switching device.

Conventionally, when a plurality of data transfers having different address transitions are alternately performed in arbitrary units, it is difficult to manage the address transitions in each transfer mode with one address counter circuit (a). This has been done by providing a counter circuit and operating the counter alternately in arbitrary units. However, in the present embodiment, the count value of the address counter circuit (a) is transferred to the host at the time of mode switching using the burst operation of the SDRAM constituting the frame memory (d), and the transfer address of the next transfer mode is transferred. Received from the host,
By setting as a base address of the address counter circuit (a), a set of address counter circuits (a)
Can support a plurality of transfer modes. Further, in the present embodiment, an SDRAM having a plurality of memory banks is used for the frame memory (d), the source memory and the destination memory are operated in synchronization, and the word selection time is performed during burst by switching memory banks. Thus, data transfer can be performed without interruption. Furthermore, since a presettable type is used as the address counter circuit (a), and the start address of the next transfer mode is externally set during a burst as the base address of the address counter circuit (a), one set of The address counter circuit (a) can support all transfer modes. In this case, the device that gives the address from outside
For example, a single-chip microcomputer may be used.

FIG. 12 is a block diagram for explaining an example of a setting method for setting the base address of the address counter circuit (a) from the host side in the present embodiment. In the example shown in FIG. 12, the microcomputer (f) is used as a host.
(Eg, a single-chip microcomputer or the like) is used to manage the frame memory (d) to be driven, addresses during transition, address scramble selection information, and the like. Here, the address counter circuit (a), the registers (b, bo), the address scrambler circuit (c), and the mode selection circuit (e)
Is composed of a gate array (G / A). In the example shown in FIG. 12, a gate array (G /
Control is started for A) by writing data via an 8-bit bus (lm). The data at this time is decoded by the mode selection circuit (e) to determine the data transfer mode and the frame memory (d), and the gate array (G / A) starts driving the frame memory (d). . The address input at the time of writing from the microcomputer (f) is set as it is in a register (b) provided in the gate array (G / A) via a switch (SW), and the address of the address counter circuit (a) is set. Preset as base address. Driving frame memory (d)
Is interrupted by an external interrupt or the like, the switch (SW) is switched, and the count value in the register (bo) holding the count value of the address counter circuit (a) at that time is returned to the microcomputer. (F) and is managed in the microcomputer (f).

In general, in order to transfer data between memories at high speed, it is common to perform DMA transfer by a CPU. However, in MPEG image data transfer processing, motion vector detection and transfer of an original image for compression are performed in parallel. Therefore, high-speed processing by the CPU is required, and the processing cannot be performed by an inexpensive microcomputer. Therefore, it is necessary to use a personal computer-level CPU of several hundred MHz or more, or to construct a high-speed data transfer system using hardware such as a DSP, which requires a memory address counter circuit (a) and a controller for each memory. However, there has been a problem that a huge number of logic circuits are required. However, according to the present embodiment, each frame memory (d)
In addition to the need for a row address counter circuit and a column address counter circuit, each of which is required only for one set, the address counter circuits for all transfer modes can be shared, and the memory control circuit can be greatly reduced. . Therefore, according to the present embodiment, even if a data transfer system is constructed by hardware, only a few thousand gates logic is required for memory control, and a cheap and compact system can be constructed.

In the present embodiment, the input data to the encoder (encoding unit) (n) is converted into a frame (4: 2: 0) format in macroblock units required by MPEG. The storage of the luminance information (Y) and the color difference information (Cb, Cr) in the memory (d) is controlled. Next, a method of storing luminance information (Y) and color difference information (Cb, Cr) in the frame memory (d) according to the present embodiment will be described. As described above, in the present embodiment, since the screen size is 512 × 480 pixels, 32 × 30 MBs (macroblocks) are created with this screen size. FIG. 13 is a block diagram illustrating a schematic configuration of the image input unit according to the present embodiment. As shown in the figure,
When writing 8-bit image data A / D-converted by a sampling clock of 13.5 MHz into a buffer memory (j) of the FIFO system for image input, the luminance information (Y) is written for all pixels. , The color difference information (Cb, Cr) with respect to the luminance information (Y)
The control circuit (p) controls to write half the pixels in both the horizontal and vertical directions. That is, the luminance information (Y) is performed with a write clock of 13.5 MHz,
The color difference information (Cb, Cr) is 6.75 (= 13.5 /
2) A write enable signal (/ WE) is output from the control circuit (p) so as to stop the writing at a write clock of MHz and for each line, and the input FIFO
The buffer memory (j) of the O system is controlled. FIG. 14A shows the control timing of the input FIFO buffer memory (j) at the time of writing and the outline of the write data. The luminance information (Y) written in the input FIFO buffer memory (j),
FIG. 15 shows an outline of the data of the color difference information (Cb, Cr).
Shown in

Next, the image data stored in the input FIFO buffer memory (j) is transferred to the frame memory (d), and the image data is stored in the frame memory (d). In this case, of the frame memory (d) of the 16-bit bus, the lower 8 bits are assigned to the luminance information (Y) and the upper 8 bits are assigned to the color difference information (Cb, Cr) to write the image data. This corresponds to the input format to the encoder (n), as shown in FIG.
The lower bits are assigned. Here, the reading of the FIFO type buffer memory (j) for inputting the color difference information (Cb, Cr) is performed by alternately using the color difference information (Cb) and the color difference information (Cr) for every eight pixel data, and using eight lines. Control is performed by a write enable signal (/ WE) and an output enable signal (/ OE) so that reading is stopped for each data. When this is repeated for 16 lines, the transfer of 32 macroblocks in the horizontal direction is completed. Similarly, when the transfer is performed up to 480 lines, the entire transfer is completed. FIG. 14 shows the control timing and data outline of an input FIFO buffer memory (j) at the time of reading.
(B). Note that MB in FIG. 14B is an abbreviation for macroblock.

Thus, the frame memory (d) contains
Luminance information (Y) and color difference information (C) of each image data
(b, Cr) is written in the specified address in the form of (4: 2: 0) in units of macroblocks in upper 8 bits and lower 8 bits. FIG. 16 shows an outline of the data of the luminance information (Y) and the color difference information (Cb, Cr) stored in the frame memory (d). The frame memory (d) stores the luminance information (Y) and the color difference information (Cb, Cr) in the MPE.
Since the data is stored in a G-compliant request format, an original image for compression can be output without requiring complicated address control at the time of output.

As described above, in order to convert the image array in the (4: 2: 0) format in macroblock units and save the data in the memory, the color difference information (Cb, Cr) is transferred twice, or the luminance information (Y) and the luminance information (Y) are stored. The color difference information (Cb, Cr) has been stored in separate memories, but the former method reduces the image data transfer time to another by occupying the data bus (l) by writing twice, which limits the image size. The latter is expensive, the cost of using two memories,
The complexity of control lines and the increase in the scale of control circuits have been problems.

However, according to the present embodiment, when the image data is transferred from the input FIFO type buffer memory (j) to the frame memory (d), the color difference information (C
By controlling the reading of each data of the input FIFO buffer memory (j) storing (b, Cr), (4: 2:
0) format image data in one frame memory (d)
Can be stored in the upper and lower bytes. As described above, according to the present embodiment, in one image data transfer, the macroblock unit (4: 4) is transferred from the input FIFO buffer memory (j) to the frame memory (d).
2: 0) format can be stored without preparing a frame memory for luminance information (Y) and a frame memory for color difference information (Cb, Cr).

Thus, according to the present embodiment, the cost of the memory is suppressed, and the luminance information (Y) and the color difference information (4: 2: 0) in macroblock units are stored in the frame memory by simple control. Cb, Cr) can be stored.

In the above description, the input data to the encoder (n) has been described in the case of the (4: 2: 0) format in units of macro blocks required in MPEG, but the present invention is not limited to this. However, it goes without saying that the present invention is also applicable to the (4: 2: 2) format in macroblock units required in MPEG. In the above description, 512
The present invention has been described as a data conversion device with an image size of × 480 pixels. However, the present invention is common to circuits that require input in units of macroblocks, which are processing units of MPEG compression processing, and the image size is 360 × 240 of MPEG1. It is needless to say that the present invention can be applied to any of 720 × 480, which is the main level of MPEG2.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

[0041]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, data can be transferred by at least one address counter circuit irrespective of the number of memories and the number of operating modes, so that the number of logics in the control circuit of the memory can be significantly reduced. It becomes possible. As a result, cost and mounting area can be reduced, and an inexpensive and compact system can be constructed. (2) According to the present invention, the luminance information and the plurality of color difference information can be stored in the memory in a predetermined arrangement which is a unit of image compression processing by one writing without using a plurality of memories. Costs can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a data transfer circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of an example of a synchronous DRAM used as a frame memory for storing images in the present embodiment;

FIG. 3 shows a synchronous DRAM according to the embodiment.
FIG. 4 is a diagram for explaining a method of storing data in a.

FIG. 4 is a table showing an address transition of a row address and a column address when a data array for detecting a motion vector is generated in the present embodiment.

FIG. 5 is a table showing an address transition of a row address and a column address when a data array of a compression image is generated in the present embodiment.

6 is a table showing transition of each address value when each address value shown in FIG. 4 is rearranged.

7 is a diagram showing a rearrangement order of each rearranged address value shown in FIG. 6;

8 is a table showing transition of each address value when each address value shown in FIG. 5 is rearranged.

FIG. 9 is a diagram illustrating a rearrangement order of each rearranged address value illustrated in FIG. 8;

FIG. 10 is a schematic diagram for explaining the operation of the address scrambler circuit according to the present embodiment.

FIG. 11 is a schematic diagram for explaining the operation of the address scrambler circuit according to the present embodiment.

FIG. 12 is a block diagram for explaining an example of a setting method for setting a base address of an address counter circuit from the host side in the present embodiment.

FIG. 13 is a block diagram illustrating a schematic configuration of an image input unit according to the present embodiment.

FIG. 14 is a diagram showing a control timing of an input-output FIFO type buffer memory at the time of writing and reading, and an outline of write data and read data in the present embodiment.

FIG. 15 is a diagram showing an outline of data of luminance information (Y) and color difference information (Cb, Cr) written in an input FIFO type buffer memory in the present embodiment.

FIG. 16 is a diagram showing an outline of data of luminance information (Y) and color difference information (Cb, Cr) stored in a frame memory (d) in the present embodiment.

FIG. 17 is a diagram showing a data arrangement of an input image, an original image to be compressed, and a motion vector detection image in the MPEG encoding system.

FIG. 18 is a block diagram illustrating an example of a connection configuration of each memory in an MPEG encoding system.

19 is a diagram showing a data array input to the encoder shown in FIG.

[Fig. 20] Fig. 20 is a diagram illustrating a coding order of macroblocks in the MPEG encoding system.

FIG. 21 is a block diagram showing a schematic hardware configuration for transferring image data from a conventional frame memory.

FIG. 22 is a block diagram showing an example of a connection configuration of each memory in order to connect each memory for transferring image data to an encoder in the conventional MPEG-compliant (4: 2: 0) format.

FIG. 23 is a block diagram showing another example of a connection configuration of each memory in order to connect each memory for transferring image data to an encoder in a conventional MPEG-compliant (4: 2: 0) format. is there.

[Explanation of symbols]

a ... address counter circuit, b, b1 ... register, c ...
Address scramble circuit, d ... frame memory, e ...
Mode selection circuit, f: microcomputer, g: row counter circuit, h: column counter circuit, i: timing control circuit,
j: FIFO type buffer memory, k: Reference memory, l: Image data bus, m: Motion vector detection circuit, n: Encoder circuit, p: Control circuit, 301A, 3
01B: memory array, 302A, 302B: row address decoder, 303A, 303B: column decoder, 304
A, 304B: sense amplifier and column selection circuit, 305
... column address buffer, 306 ... row address buffer,
307: column address counter circuit (a), 308: output buffer, 309: input buffer, 310: controller.

Claims (14)

[Claims] 1. A data storage for storing, in a memory, luminance information of an input frame image and a plurality of pieces of color difference information of the input frame image, the plurality of pieces of color difference information having an information amount reduced as compared with the luminance information. In the method, when writing the luminance information to the memory, the plurality of color difference information is alternately written to the memory for each predetermined number of pixels, so that the luminance information and the plurality of color difference information are arranged in a predetermined arrangement. A data storage method characterized by storing in a memory. 2. A data storage for storing, in a memory, luminance information of an input frame image and a plurality of pieces of color difference information of the input frame image, the plurality of pieces of color difference information having an information amount reduced compared to the luminance information. In the method, when writing the luminance information into the memory, the plurality of pieces of color difference information are alternately written into the memory for each predetermined number of pixels, and the plurality of pieces of color difference information are written into the memory, and Non-writing of said color difference information in said memory for every predetermined number of lines to store said luminance information and a plurality of color difference information in said memory in a predetermined arrangement. 3. A data storage method for storing luminance information of an input frame image and a plurality of pieces of color difference information in a memory, wherein the luminance information of the input frame image and the plurality of pieces of color difference information are written to a buffer memory at different frequencies. When reading the luminance information from the buffer memory and writing the luminance information to the memory, the luminance information and the plural color difference information are obtained by alternately reading the plural pieces of color difference information from the buffer memory every predetermined number of pixels and writing the plural pieces of color difference information to the memory. Are stored in the memory in a predetermined arrangement. 4. A data storage method for storing luminance information of an input frame image and plural pieces of color difference information in a memory, wherein the luminance information of the input frame image and plural pieces of color difference information are written into a buffer memory at different frequencies. When the luminance information is read from the buffer memory and written to the memory, the plurality of pieces of color difference information are alternately read from the buffer memory for each predetermined number of pixels and written to the memory, and the plurality of pieces of color difference information are buffered. By repeating reading from the memory and stopping reading of the plurality of pieces of color difference information from the buffer memory for each predetermined number of lines, the luminance information and the plurality of pieces of color difference information are stored in the memory in a predetermined array. A data storage method characterized by storing. 5. The memory according to claim 1, wherein the plurality of color difference information and the luminance information are stored in upper bits and lower bits of the same address of the memory, respectively. Data storage method. 6. The memory, wherein information is input or output in synchronization with a clock, and the memory includes a plurality of memory arrays, wherein the memory stores a plurality of pieces of luminance information of the input frame image in a first direction. The color difference information is continuously stored by switching the memory array of the memory, and the luminance information in the second direction of the input image and a plurality of pieces of color difference information are switched by switching the address,
The data storage method according to claim 1, wherein the data is stored in the memory. 7. The input frame image is composed of a first field image and a second field image, and the luminance information and the plurality of color difference information of the first field image in a second direction are stored in a second area of the memory. 7. The data according to claim 6, wherein luminance information and a plurality of pieces of color difference information of the second field image in a second direction are stored in a second area of the memory. Storage method. 8. A data transfer circuit for transferring data between memories or from a memory to another circuit, wherein at least one address counter circuit and a count value of the address counter circuit are rearranged.
A data transfer circuit, comprising: an address rearranging device for outputting to an address input terminal of the memory. 9. The data transfer circuit according to claim 8, wherein said address counter circuit can be preset from outside. 10. The data according to claim 8, wherein the address rearranging device can change a combination of its operation timing and address rearrangement by external control. Transfer circuit. 11. A mode selection circuit, wherein the address rearrangement device is capable of changing a combination of an operation timing and an address rearrangement under the control of the mode selection circuit. The data transfer circuit according to any one of claims 8 to 10, wherein 12. The method according to claim 11, wherein the mode selection circuit controls a combination of an operation timing of the address rearranging device and an address rearrangement based on data transferred from the outside. Data transfer circuit. 13. The data transfer circuit according to claim 8, wherein said address rearranging device generates a row address and a column address of an address multiplexer type memory. 14. The memory according to claim 8, wherein input / output of information is performed in synchronization with a clock, and the memory has a plurality of memory arrays. A data transfer circuit according to claim 1.