JP2005236946A - Accessing method to dram - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speedily perform access processing with respect to a DRAM in MPEG processing. <P>SOLUTION: A two-dimensional image is input in order of raster, and these image data are stored in a 16-bit SDRAM performing changeovers between a bank 0 and a bank 1. Concretely, the data are stored performing changeovers between the bank 0 and the bank 1 by every 8 pixel. In this case, data in the direction of the row of the two-dimensional image are stored in the same bank. When a 32-bit SDRAM is used, data are stored performing changeovers between the bank 0 and the bank 1 by every 16 pixel. In this case, storage is performed concerning the data in the row direction of the two-dimansional data so that the bank 0 and the bank 1 alternate. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a DRAM access method in MPEG processing.

  In a compression technique based on MPEG (Moving Picture Expert Group), processing is performed in units of macroblocks of 16 pixels in the vertical direction and 16 pixels in the horizontal direction in the two-dimensional image. Therefore, it is desirable that the image data stored in the memory can be processed at high speed with respect to the image data in units of macroblocks.

  However, image data transferred in raster order from an image input device such as a CCD is generally stored in a memory as a two-dimensional image. That is, an image in units of macroblocks is stored as it is as a two-dimensional image image in a plurality of rows of storage areas in the memory. For this reason, in order to read image data in units of macroblocks, it is necessary to access a plurality of rows of storage areas.

  Here, when an SRAM (Static Random Access Memory) is used as a memory, it is possible to access a plurality of rows of storage areas at a high speed, but there is a problem that the SRAM is expensive. Therefore, DRAM (Dynamic Random Access Memory) will be adopted from the viewpoint of cost, but the processing of switching the row address and accessing the storage area of a plurality of rows of the DRAM has a problem that the processing speed is slow. .

  Therefore, a technique for accessing macroblock unit image data at high speed is disclosed in Patent Document 1 below.

JP-A-10-162131 JP 2003-186740 A

  In Patent Document 1, when image data input in raster order is stored in a memory, the image data is rearranged in advance so that image data in units of macroblocks is stored in the same row of the memory. is there.

  However, the method disclosed in Patent Document 1 has a problem that the write control for the memory is complicated. Further, the above-mentioned Patent Document 2 discloses a technique for alternately accessing two banks of a memory and concealing overhead due to precharge to a DRAM, but in consideration of access to image data in units of macroblocks. Therefore, it is not possible to speed up image access in units of macroblocks.

  In view of the above problems, an object of the present invention is to provide an efficient method for accessing macroblock image data stored in a DRAM at high speed.

  In order to solve the above-mentioned problem, the invention described in claim 1 is a method for accessing a DRAM having a first bank and a second bank, wherein a first two-dimensional image to be processed by MPEG is input in raster order. Step and data in the row direction of the two-dimensional image are stored in the DRAM while alternately switching the first bank and the second bank every 8 pixels, and the data in the column direction of the two-dimensional image is described above. And a second step of storing in the same bank of the DRAM.

  A second aspect of the present invention is the DRAM access method according to the first aspect, wherein the first bank and the second bank are alternately switched with respect to the image data stored in the second step. A third step of accessing a macroblock for MPEG processing of 16 pixels vertically by 16 pixels horizontally by accessing in units of 8 pixels is provided.

  According to a third aspect of the present invention, in the DRAM access method according to the second aspect, in the third step, the mth row (m is 0 to 14) in the macroblock stored in the first bank. Integer) 8-pixel image data, then access the next 8-pixel image data in raster order stored in the second bank, and then access the second macroblock stored in the first bank. and accessing the next 8-pixel image data in the raster order stored in the second bank after accessing the 8-pixel image data in the (m + 1) th row.

  According to a fourth aspect of the present invention, in the DRAM access method according to the first aspect, in the second step, the image data of the nth row (n is an integer of 0 or more) of the two-dimensional image is Storing in the storage area of the nth row of the first bank and the second bank, and storing the image data of the (n + 1) th row in the storage area of the (n + 1) th row of the first bank and the second bank. , Including.

  According to a fifth aspect of the present invention, in the DRAM access method according to the fourth aspect, in the third step, in the macroblock stored in the nth row of the first bank, the mth row (m is (E.g., an integer from 0 to 14), the next 8-pixel image data is accessed in the raster order stored in the nth row of the second bank, and then the second After accessing the image data of the 8th pixel of the (m + 1) th row in the macro block stored in the (n + 1) th row of the 1 bank, the next 8 pixels in the raster order stored in the (n + 1) th row of the 2nd bank are accessed. Accessing image data.

  A sixth aspect of the present invention is the DRAM access method according to any one of the first to fifth aspects, wherein the DRAM is capable of storing 16-bit data at one address, and each of the two-dimensional images is stored. Each pixel includes 8-bit information, so that image data of 8 pixels is stored for each of four consecutive addresses in the same row for the first and second banks of the DRAM. And

  A seventh aspect of the present invention is the DRAM access method according to the sixth aspect, wherein image data of 8 pixels continuous in a raster order is burst-transferred to the DRAM.

  The invention according to claim 8 is the DRAM access method according to claim 6 or 7, wherein when the image data stored in the DRAM is Y (luminance) data, one of the DRAMs is stored. Y data for 2 pixels is stored for the address.

  The invention according to claim 9 is the DRAM access method according to any one of claims 6 to 8, wherein the image data stored in the DRAM is U, Y (color difference) data. One set of U data and V data is stored for one address of the DRAM.

  The invention according to claim 10 is a method for accessing a DRAM having a first bank and a second bank, wherein a first step of inputting a two-dimensional image to be processed in MPEG in a raster order, and the two-dimensional image Is stored in the DRAM while alternately switching the first bank and the second bank every 16 pixels, and the data in the column direction of the two-dimensional image is stored in the first bank every row. And a second step of storing in the DRAM so that the second banks alternate.

  The invention according to claim 11 is the DRAM access method according to claim 10, wherein the first bank and the second bank are alternately switched with respect to the image data stored in the second step. A third step of accessing a macroblock for MPEG processing of 16 pixels vertically × 16 pixels horizontally by accessing in units of 16 pixels is provided.

  A twelfth aspect of the present invention is the DRAM access method according to the eleventh aspect, wherein the third step includes the m-th row (m is 0 or more and 14 or less) in the macroblock stored in the first bank. After accessing the 16-pixel image data of (integer), the step of accessing the 16-pixel image data of the (m + 1) th row in the macroblock stored in the second bank is then included.

  A thirteenth aspect of the present invention is the DRAM access method according to the eleventh or twelfth aspect, wherein the third step is performed when successive macroblocks adjacent to each other on a two-dimensional image are accessed. Is characterized in that the access order in the column direction is reversed for adjacent macroblocks.

  A fourteenth aspect of the present invention is the DRAM access method according to the twelfth aspect, wherein the third step is adjacent to the macroblock after the macroblock is accessed by the step according to the second aspect. When accessing the macroblock continuously, after accessing the 16th pixel image data of the kth row (k is an integer of 1 to 15) in the macroblock stored in the first bank, Next, the method includes a step of accessing image data of 16 pixels in the (k−1) th row in the macro block stored in the second bank.

  A fifteenth aspect of the present invention is the DRAM access method according to any one of the tenth to fourteenth aspects, wherein the DRAM can store 32-bit data at one address, and each of the two-dimensional images Each pixel includes 8-bit information, so that the first and second banks of the DRAM store image data of 16 pixels at four consecutive addresses in the same row. And

  A sixteenth aspect of the present invention is the DRAM access method according to any one of the tenth to fourteenth aspects, wherein the DRAM is capable of storing 16-bit data at one address, and each of the two-dimensional images is stored. Each pixel includes 8-bit information, so that the first and second banks of the DRAM store 16-pixel image data for eight consecutive addresses in the same row. And

  The invention according to claim 17 is the DRAM access method according to claim 15 or 16, characterized in that image data of 16 pixels continuous in raster order is burst-transferred to the DRAM. To do.

  The invention according to claim 18 is the DRAM access method according to claim 15, wherein the image data stored in the DRAM is Y (luminance) data with respect to one address of the DRAM. Y data for four pixels is stored.

  The invention described in claim 19 is the DRAM access method according to claim 15 or 18, wherein the image data stored in the DRAM is U, Y (color difference) data. Two sets of U data and V data are stored for one address.

  The invention according to claim 20 is the DRAM access method according to claim 16, wherein the image data stored in the DRAM is Y (luminance) data with respect to one address of the DRAM. Y data for two pixels is stored.

  The invention according to claim 21 is the DRAM access method according to claim 16 or claim 20, wherein the image data stored in the DRAM is U, Y (color difference) data. One set of U data and V data is stored for one address.

  According to the present invention, since the two-dimensional image data in the raster order is stored in the DRAM while switching between the first bank and the second bank, it is necessary to continuously access the image data in different rows for the stored image data. Even in this case, it becomes possible to change the row address of the other bank while accessing one bank, and the access efficiency is improved.

  Further, when accessing image data in units of macroblocks in MPEG processing, the DRAM can be accessed efficiently while switching between the first bank and the second bank, so that the speed of MPEG processing can be increased. It is.

{First embodiment}
The first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an overall schematic diagram of an image processing apparatus. The image processing apparatus is based on, for example, an input unit 1 composed of an image sensor such as a CCD, an SDRAM (Synchronous DRAM) 4 storing image data output from the input unit 1, and image data stored in the SDRAM 4 based on the MPEG standard. When the image processing unit 2 that performs compression processing and the image data output from the input unit 1 are stored in the SDRAM 4 and when the MPEG processing unit 2 accesses the image data stored in the SDRAM 4, access control to the SDRAM 4 is performed. And a memory control unit 3.

  Here, the image data output by the input unit 1 is output in raster order. In this specification, the raster order is a procedure in which a two-dimensional image is continuously output as one-dimensional image data, and more specifically, image data in the uppermost row starting from the upper left pixel in the two-dimensional image. Are sequentially transferred, and after transferring to the rightmost pixel, the image data of the next row is sequentially transferred from the left end to the right end, and the image data of each row is sequentially transferred as one-dimensional image data. The raster order includes not only progressive transfer but also interlace transfer. In interlaced transfer, transfer of image data for one field with respect to image data in odd rows and transfer of image data for one field with respect to image data in even rows are alternately performed.

  Further, the SDRAM 4 in the first embodiment can store 2 bytes (16 bits) of data in a memory area of one address. That is, the SDRAM 4 in the first embodiment is a 16-bit SDRAM. The SDRAM 4 is capable of burst transfer processing that continuously accesses data to four consecutive addresses. That is, the SDRAM 4 is capable of burst transfer of 64 bits (4 addresses × 16 bits) of data.

  FIG. 2 is a diagram illustrating a pixel configuration of two-dimensional image data. Here, a two-dimensional image will be described as an example in which the horizontal 320 pixels, that is, the image data of one row (horizontal one line) is 320 pixels. Further, in this specification, as shown in the figure, the horizontal direction of the two-dimensional image will be described as appropriate in correspondence with the row direction, and the vertical direction of the two-dimensional image will correspond with the column direction.

  In FIG. 2, two-dimensional image data is displayed divided into blocks. Here, one section in the column direction corresponds to one row (one horizontal line) of the image. One section in the row direction corresponds to image data for 8 pixels. That is, one block is a set of image data for 8 pixels. The display of 0 to 7 pix, 8 to 15 pix, etc. displayed in each block is a pixel number assigned to all pixels in raster order with the leftmost pixel in the top row as the 0th image. . Therefore, if the image data is 320 pixels wide × 100 pixels high, numbers from 0 to 31999 are assigned to the pixels in raster order.

  The leftmost block in the top row (0th row) corresponds to the 0th to 7th pixels in the 0th row of the 2D image, and the right block is the 8th row in the 0th row of the 2D image. It corresponds to the pixels from the 15th to the 15th. The rightmost block of the uppermost row (0th row) corresponds to the 312th to 319th pixels of the 0th row, and the leftmost block of the next row (1st row) corresponds to the 320th to 327th pixels. To the first pixel (this corresponds to the 0th to 7th pixels in the first row in the two-dimensional image).

In this way, the two-dimensional image is blocked every 8 pixels in raster order. Further, as shown in the figure, the blocks in the column direction are grouped, and these groups are alternately stored in the bank 0 and the bank 1 of the SDRAM 4. Specifically, in the figure, the group of blocks not shaded is stored in bank 0 of SDRAM 4 and the group of blocks shaded is stored in bank 1 of SDRAM 4. In the figure, the display of A _0,0 , B _0,0, etc. will be described later. When this two-dimensional image data is stored in the SDRAM 4, the memory area (bank 0 and bank 1) is stored. (Memory area) block name.

  FIG. 3 is a timing chart when the raster control image data output from the input unit 1 is written into the SDRAM 4 by the memory control unit 3. FIG. 4 is a diagram showing the order of writing to the bank 0 of the SDRAM 4, and FIG. 5 is a diagram showing the order of writing to the bank 1 of the SDRAM 4. FIG. 6 shows the pixel number of the image data stored in each memory area of bank 0 (this number is the left end (0th column) of the uppermost row (0th row) of the two-dimensional image as described above. 7 is a number assigned in raster order to all pixels, with the pixel of 0 being the 0th image. FIG. 7 is a pixel number of image data stored in each memory area of bank 1 FIG.

4 and 5, the subscripts such as the memory areas a _0,0 and b _0,0 are the first subscript indicating the row number of the memory area, and the second subscript is the memory area. Indicates the column number. Therefore, the memory areas a ₁ and 4 indicate the memory area of the first row and the fourth column of the bank 0. In addition, block areas A _0,0 , B _{0,0 and the} like in FIGS. 4 and 5 indicate blocks composed of four memory areas. The subscript of the block area corresponds to the row number and column number of the first (leftmost) memory area included in the block area.

In FIG. 3, first, “0” is set to the bank address, “0” is set to both the row address and the column address, and image data for 8 pixels from the 0th to the 7th is burst transferred. . That is, since the image data of 1 pixel is 8 bits, image data for 8 pixels (8 pixels × 8 bits) is burst transferred. The image data for 8 pixels is stored in the block area A _0,0 of bank 0 shown in FIG. The block area A _0,0 is an area composed of memory areas a _0,0 , a _0,1 , a _0,2 , a _0,3 . In FIG. 3, Bank ADDRESS indicates a bank address signal, and ADDRESS indicates a row and column address signal. Bank0 and Bank1 indicate the access timing of data to bank 0 and bank 1, respectively, and the contents of the transferred data. The data contents (numbers such as 0, 1) indicate the pixel numbers described above.

On the other hand, as shown in FIG. 3, the bank address is set to “1” at the timing when the image data for 8 pixels from 0th to 7th is written in the block area A _0,0 . Then, after writing to the block area A _0,0 , image data for 8 pixels from the 8th to the 15th is burst transferred. The image data for 8 pixels is stored in the block area B _0,0 of bank 1 shown in FIG. The block area B _0,0 is an area composed of the memory areas b _0,0 , b _0,1 , b _0,2 , b _0,3 .

Further, the bank address is set to “0” at the timing when the image data for 8 pixels from the 8th to the 15th is written in the block area B _0,0 . Then, after writing to the block area B _0,0 , image data for 8 pixels from the 16th to the 23rd is burst transferred. The image data for 8 pixels is stored in the block area A _0,4 of the bank 0 shown in FIG. 4 by setting “4” as the column address. The block area A _0,4 is an area composed of memory areas a _0,4 , a _0,5 , a _0,6 , a _0,7 .

The bank address is set to “1” at the timing when writing is performed in the block areas A _0,4 . Then, after writing to the block areas A _0,4 , image data for 8 pixels from the 24th to the 31st is burst transferred. The image data for 8 pixels is stored in the block area B _0,4 of the bank 1 shown in FIG. 5 by setting “4” to the column address. The block area B _0,4 is an area composed of memory areas b _0,4 , b _0,5 , b _0,6 , b _0,7 .

With the above processing, as shown in FIGS. 6 and 7, the block areas A _0,0 and A _0,4 of the bank ₀ and the block areas B _0,0 and B _0,4 of the bank 1 are changed from the 0th to the 31st. Up to 32 pixels of image data are stored. Thereafter, similarly, the bank 0 and the bank 1 are switched, the image data is burst transferred in units of 8 pixels, and the image data is sequentially stored in the SDRAM 4. The arrows in FIGS. 4 and 5 indicate the storage order in bank 0 and bank 1, respectively. After the image data of the 0th row of the two-dimensional image is stored in the direction of the arrow by the above-described procedure, the image data of the first row is similarly stored in the direction of the arrow, and the image data of each row is stored sequentially. The The write procedure for the SDRAM 4 can be expressed using a block area. Block area A _0,0 → B _0,0 → A _0,4 → B _0,4 → A _0,8 → B _0,8 → A _0,12 In this order, the two-dimensional image data is stored sequentially.

  In this way, 2D image data to be subjected to MPEG processing is stored in the SDRAM 4 as a 2D image image while switching between bank 0 and bank 1. As shown in FIG. 2, the image data is all stored in the same bank for the column direction in the two-dimensional image. For this reason, when attention is paid to the macroblock of the two-dimensional image, the image data in the macroblock is stored across a plurality of rows of the SDRAM 4. Does not occur. Although this access procedure will be described in detail later, the row to be accessed for bank 0 is switched at the timing when data in bank 1 is accessed, and bank 1 is accessed at the timing when data in bank 0 is accessed. This is because it is possible to switch the row to be accessed.

  In this embodiment, as shown in FIGS. 6 and 7, the image data for one horizontal line of the two-dimensional image data is stored in the memory areas of the same row of bank 0 and the same row of bank 1 of SDRAM 4. When the horizontal line of the two-dimensional image data is stored and moved to the next horizontal line, the storage areas of the bank 0 and bank 1 memory areas are also changed. Such a storage method has a demerit in terms of effective use of the memory area, but has an advantage in that the circuit configuration can be simplified. Therefore, this method is effective when there is a margin in the memory area.

  However, the above storage method is an example, and the present invention is not limited to this. That is, after the image data of the first line of the two-dimensional image input in raster order is stored in the first line (bank 0 or bank 1) of the SDRAM 4, the image data of the second line is continued and one line of the SDRAM 4 is continued. You may take the method of storing in eyes. Similarly, in each row of the SDRAM 4, the row to be stored is not changed corresponding to the horizontal line of the image data, and the image data is sequentially packed and stored. In this case, image data for 8 pixels transferred at a time (that is, image data for 1 burst transfer) may be stored in the same row of any bank of the SDRAM 4. Thus, if the row address of the other bank is changed at the timing when one of the data in bank 0 and bank 1 is accessed, the processing speed can be increased. Or, conversely, the data size of one horizontal line of the two-dimensional image may be larger than the size that can be stored in one row of SDRAM 4 (the sum of the sizes that can be stored in one row of bank 0 and bank 1). Also in this case, there is no problem if the image data is stored in the same row of any bank in units of 8 pixels and the row address of each bank is changed in the middle of one horizontal line of the two-dimensional image. . That is, according to the present invention, the image data for 8 pixels, which is half of the image data of one row constituting the macro block, are all stored in the same row of one bank, and the remaining half following this. That is, all the image data for 8 pixels are stored in the same row of the other bank, and all the data in the column direction are stored in the same bank. If such a storage method is used, as will be described later, even when it is necessary to change the row address of one of the banks when accessing the image data in units of macroblocks, it is always necessary to change to the other bank. Since the access process intervenes, the occurrence of idle time can be eliminated by changing the row address during that time.

  Next, processing for accessing the image data stored in the SDRAM 4 in units of macro blocks in order for the MPEG processing unit 2 to perform MPEG compression processing will be described. The access process includes a process for reading out image data in units of macroblocks to which the MPEG processing unit 2 performs an MPEG compression process, and a process for writing image data in units of macroblocks.

FIG. 8 is a timing chart of a process for accessing the image data stored in the SDRAM 4 by the memory control unit 3. FIG. 9 is a diagram showing an access order to the bank 0 of the SDRAM 4, and FIG. 10 is a diagram showing an access order to the bank 1 of the SDRAM 4. FIG. 8 to FIG. 10 are diagrams showing features common to image data read processing and write processing in units of macroblocks. Further, each memory area a _0,0 in FIGS. 9 and 10, b _0,0, etc. are associated with the memory region a _0,0, b _0,0, etc. in FIGS. 4 and 5, described above It is assumed that two-dimensional image data is stored in an array as shown in FIGS. 6 and 7 by the writing process.

First, image data read processing in units of macroblocks will be described. In FIG. 8, first, “0” is set to the bank address, “0” is set to both the row address and the column address, and image data for 8 pixels from the 0th to the 7th is burst transferred. . Specifically, the image data for 8 pixels stored in the block area A _0,0 of bank 0 shown in FIG. 9 is read. In FIG. 8, Bank ADDRESS indicates a bank address signal, and ADDRESS indicates a row and column address signal. Bank0 and Bank1 indicate the access timing of data to bank 0 and bank 1, respectively, and the contents of the transferred data. The data contents (numbers such as 0, 1) indicate the pixel numbers described above.

On the other hand, as shown in FIG. 8, at the timing when the readout process for the image data of the block area A _0,0 is being performed, the bank address is set to "1", termination process of reading from the block area A _0,0 Thereafter, image data for 8 pixels from the 8th to the 15th is burst transferred. Specifically, the image data for 8 pixels stored in the block area B _0,0 of bank 1 shown in FIG. 10 is read.

Further, as shown in FIG. 8, at the timing when the image data read processing of the block area B _0,0 is performed, the bank address is set to “0” and the row address is set to “1”. After the reading process from the block area B _{0,0 is} completed, the image data for 8 pixels from the 320th to the 327th is burst transferred. Specifically, the image data for 8 pixels stored in the block area _A1,0 of the bank 0 shown in FIG. 9 is read. The block area A _1,0 is an area composed of memory areas a _1,0 , a _1,1 , a _1,2 , a _1,3 . Here, for bank 0, access processing for block area A _1,0 is performed after access processing for block area A _0,0 , so it is necessary to switch the row address to be accessed. Since the row address is switched at the timing when the data transfer with respect to B _0,0 is performed, the data reading process is efficiently executed without generating a free time.

Then, at the timing when the readout processing of the image data of the block area A _{1, 0} is being performed, "1" is set to a row address together with the bank address is set to "1", the block area A _{1, 0} After the reading process ends, image data for 8 pixels from the 328th to the 335th is burst transferred. Specifically, the image data for 8 pixels stored in the block area _B1,0 of the bank 1 shown in FIG. 10 is read. The block area B _1,0 is an area composed of memory areas b _1,0 , b _1,1 , b _1,2 , b _1,3 . Similarly, for bank 1, access processing for block area B _1,0 is performed after access processing for block area B _0,0 , so it is necessary to switch the row address to be accessed. Since the row address is switched at the timing when the data transfer for A _{1, 0} is performed, the data reading process is efficiently executed without generating a free time.

Through the above processing, from the 0th stored in block areas A _0,0 and A _1,0 of bank ₀ and block areas B _0,0 and B _1,0 of bank 1 shown in FIGS. The image data for 16 pixels up to the 15th and the image data for 16 pixels from the 320th to the 335th are read out. When this image data is made to correspond to the image image of FIG. 2, the row direction is 16 pixels, and the column direction is image data for two rows in the same column. That is, after that, similarly, while switching between bank 0 and bank 1, the image data is burst transferred in units of 8 pixels, and sequentially read out the image data in the same column with the row direction of 16 pixels. Therefore, it is possible to continuously read out image data of various blocks. By executing such processing for 16 rows, it is possible to continuously read out image data corresponding to a macroblock of 16 pixels vertically × 16 pixels horizontally.

FIG. 11 is a diagram illustrating the reading order of macroblocks. In the description using FIG. 8 to FIG. 10, the description has been given to the point where the image data of the block area A _0,0 → B _0,0 → A _1,0 → B _1,0 is read. Thereafter, the image data of the block area in the same row is sequentially read out while alternately switching between the bank 0 and the bank 1, and when the block areas A _15,0 and B _15,0 in the 16th row are read out, the vertical 16 pixels X Image data corresponding to a macroblock of 16 pixels wide can be read out.

  As described above, if the storage rules for bank 0 and bank 1 as shown in FIG. 2 are satisfied, image data of different horizontal lines of the two-dimensional image is stored in the same row of SDRAM 4. Also good. For example, it has been described that the image data of the first line and the second line of the two-dimensional image data may be stored in the memory area of the first row of the SDRAM 4. Also in this case, the data reading process in units of macroblocks can be performed at high speed. That is, by storing image data while switching banks in units of 8 pixels, it becomes possible to switch the row of the other bank while reading image data from one bank. . As a result, even when an access row to the SDRAM 4 is changed, it is possible to perform a read process without causing a free time. Further, as long as the storage rules for bank 0 and bank 1 as shown in FIG. 2 are satisfied, one horizontal line of two-dimensional image data may be stored across a plurality of rows of SDRAM 4. Alternatively, the order in the column direction of each horizontal line of the two-dimensional image may be different from the order in the column direction stored in the SDRAM 4 or may be stored in discrete rows.

As described above, the image data can be read at a high speed in units of macroblocks, but the process of writing the image data in units of macroblocks by the MPEG processing unit 2 is the same. This writing process may also be performed in the access sequence shown in the timing chart shown in FIG. 8, FIG. 9, FIG. 10, and FIG. That is, the image data may be written in the order of the block areas A _0,0 → B _0,0 → A _1,0 → B _1,0 → A _2,0 . As a result, both reading and writing of image data in units of macro blocks can be performed at high speed.

  As described above, according to the present embodiment, even when image data in units of macro blocks necessary for MPEG processing is continuously accessed, an access free time is generated by switching between bank 0 and bank 1. It is possible to efficiently access the SDRAM 4 without making it happen. That is, since the row address of the other bank can be changed while the image data is being accessed in one bank, there is no free time associated with the row address change. In addition, in the writing process of the image data input from the input unit 1 to the SDRAM 4, the image data input in the raster order is stored in the same order, so that the control during the writing process is not complicated.

  Next, a method of storing image data in each memory area according to the type of data will be described with reference to FIG. In MPEG processing, image data in a YUV color space consisting of luminance data (Y data) and color difference data (U, V data) is handled. Here, as shown in FIG. 13, the Y data is information held by all the pixels of the two-dimensional image data. On the other hand, U and V data have fewer numbers than Y data. In the YUV 4: 2: 0 format, as shown in the figure, the numbers of U data and V data are decimated 1/2 in the row direction and ½ in the column direction.

  In the above-described access processing to the SDRAM 4, it has been described without particularly considering whether the type of image data is luminance data or color difference data. Here, in the case of luminance data and color difference data, a method of storing them in the memory area will be described. The image data will be described for the YUV 4: 2: 0 format.

  In the timing chart shown in FIG. 12, the first two burst transfer processes are processes for luminance data. The latter two burst transfer processes are processes for color difference data. First, in the case of luminance data, two Y data are stored in one memory area. That is, the Y data of one pixel is 8 bits, and the memory area corresponding to one address of the SDRAM 4 in this embodiment can store 16 bits of data. It is stored in the area. At this time, among the 16-bit data lines accessing the SDRAM 4, the upper 8 bits are used for one Y data transfer and the lower 8 bits are used for the other Y data transfer. In this way, bank 0 stores Y data for 8 pixels in four memory areas corresponding to four addresses. Subsequently, in bank 1, Y data for 8 pixels is stored in four memory areas corresponding to four addresses.

  Next, a method for storing color difference data will be described. In FIG. 13, one U data and one V data are present for each of four Y data in an area of 2 pixels × 2 pixels indicated by a bold frame. Therefore, the two U data and V data are packed and stored in one memory area.

  As shown in FIG. 12, if two U data and V data are packed and stored in one memory area, four such sets of U data and V data, that is, 8 pixels are included. Burst transfer can be performed. That is, the U data and V data are both 8-bit data per pixel, and the memory area corresponding to one address of the SDRAM 4 in this embodiment can store 16-bit data. Data for two pixels consisting of data is stored in a memory area of one address. At this time, among the 16-bit data lines accessing the SDRAM 4, the upper 8 bits are used for U data transfer, for example, and the lower 8 bits are used for V data transfer. In this way, bank 0 stores color difference data for 8 pixels in four memory areas corresponding to four addresses. Subsequently, in bank 1, color difference data for 8 pixels is stored in four memory areas corresponding to four addresses.

  In this way, by packing U data and V data and storing them in one memory area, the same transfer procedure is executed when accessing SDRAM 4 for luminance data and when accessing SDRAM 4 for color difference data. It becomes possible to do.

  Specifically, first, data access in units of macroblocks is performed on luminance data, and then data access in units of macroblocks is performed on color difference data in the same macroblock region (FIG. 12 shows luminance data). The timing at which the data access process and the data access process for the color difference data are just switched is shown.), The data access for the luminance data and the data access for the color difference data can be made the same procedure.

  However, in the case of the YUV 4: 2: 0 format, the number of U data and V data is halved in the row direction (vertical direction), so the processing for one macroblock is performed with luminance data. Half of the processing is sufficient. If described with reference to FIG. 11, processing for luminance data requires processing for 16 rows, but in the case of color difference data, processing for 8 rows may be sufficient.

  As described above, in the first embodiment, the case where the SDRAM can store 16-bit data in one address has been described as an example. However, the present invention can also be applied to a DRAM capable of storing 8-bit data at one address. In this case, two DRAMs that can store 8-bit data are used to perform the same processing as in the above-described embodiment. That is, the process of storing the image data for 8 pixels at each of the four addresses of the two DRAMs may be a unit process. Then, the same processing as described above may be performed for each DRAM while alternately switching between bank 0 and bank 1.

{Second Embodiment}
Next, a second embodiment of the present invention will be described. The image processing apparatus in the second embodiment is the same as the image processing apparatus described in FIG. However, the SDRAM 4 in the second embodiment can store 4 bytes (32 bits) of data in a memory area of one address. That is, the SDRAM 4 in the second embodiment is a 32-bit SDRAM. The SDRAM 4 is capable of burst transfer processing that continuously accesses data to four consecutive addresses. That is, the SDRAM 4 is capable of burst transfer of 128 bits (4 addresses × 32 bits) of data.

  FIG. 14 is a diagram illustrating a pixel configuration of two-dimensional image data. Here, the two-dimensional image will be described as an example in which the horizontal 320 pixels, that is, the image data of one row (horizontal one line) is 320 pixels.

  In FIG. 14, two-dimensional image data is displayed divided into blocks. The notation rules in this figure are the same as those described in FIG. However, the number of pixels in one block is different from that in FIG. The leftmost block of the uppermost row (0th row) corresponds to the 0th to 15th pixels of the 0th row of the 2D image, and the right block is the 16th row of the 0th row of the 2D image. It corresponds to the pixels from the th to the 31st. The rightmost block of the uppermost row (0th row) corresponds to the 304th to 319th pixels of the 0th row, and the leftmost block of the next row (first row) corresponds to the 320th to 335th pixels. To the first pixel (this corresponds to the 0th to 15th pixels in the first row in the two-dimensional image).

In this way, the two-dimensional image is blocked every 16 pixels in raster order. Furthermore, in this embodiment, as shown in the figure, each of these blocks is assigned to bank 0 and bank 1 in a staggered manner and stored in SDRAM 4. In other words, the bank 0 and the bank 1 are assigned alternately in both the row direction and the column direction of the two-dimensional image. Specifically, in the figure, blocks not shaded are stored in bank 0 of SDRAM 4 and blocks shaded are stored in bank 1 of SDRAM 4. In the figure, the display of C _0,0 , D _0,0 and the like is the same as that described in the first embodiment. That is, the block names of the memory areas (memory areas in the bank 0 and the bank 1) stored when the two-dimensional image data is stored in the SDRAM 4 are shown.

  FIG. 15 is a timing chart when the raster control image data output from the input unit 1 is written into the SDRAM 4 by the memory control unit 3. FIG. 16 is a diagram showing the order of writing to the bank 0 of the SDRAM 4, and FIG. 17 is a diagram showing the order of writing to the bank 1 of the SDRAM 4. FIG. 18 shows the pixel number of image data stored in each memory area of bank 0 (this number is the left end (0th column) of the uppermost row (0th row) of the two-dimensional image as described above. FIG. 19 is a pixel number of image data stored in each memory area of bank 1. FIG. 19 is a number assigned in raster order to all pixels. FIG.

In FIGS. 16 and 17, subscripts such as the memory areas c _0,0 and d _0,0 are the first subscript indicating the row number of the memory area, and the second subscript is the memory area. Indicates the column number. These notation rules are the same as those in the first embodiment. In addition, block areas C _0,0 , D _0,0, etc. in FIG. 16 and FIG. 17 indicate blocks composed of four memory areas. The subscript of the block area corresponds to the row number and column number of the first (leftmost) memory area included in the block area.

In FIG. 15, first, “0” is set to the bank address, “0” is set to both the row address and the column address, and image data for 16 pixels from the 0th to the 15th is burst transferred. . That is, since image data of 1 pixel is 8 bits, image data for 16 pixels (16 pixels × 8 bits) is burst transferred. The image data for 16 pixels is stored in the block area C _0,0 of bank 0 shown in FIG. The block area C _0,0 is an area composed of memory areas c _0,0 , c _0,1 , c _0,2 , c _0,3 . The notation rules in FIG. 15 are the same as those in FIG.

On the other hand, as shown in FIG. 15, the bank address is set to “1” at the timing when image data for 16 pixels from the 0th to the 15th is written in the block area C _0,0 . Then, after writing to the block area C _0,0 , image data for 16 pixels from the 16th to the 31st is burst transferred. The image data for 16 pixels is stored in the block area D _0,0 of bank 1 shown in FIG. The block area D _0,0 is an area composed of memory areas d _0,0 , d _0,1 , d _0,2 , d _0,3 .

Further, the bank address is set to “0” at the timing when the image data for 16 pixels from the 16th to the 31st is written in the block area D _0,0 . Then, after writing to the block area D _0,0 , image data for 16 pixels from the 32nd to the 47th is burst transferred. The image data for 16 pixels is stored in the block area C _0,4 of the bank 0 shown in FIG. 16 by setting “4” as the column address. The block area C _0,4 is an area composed of memory areas c _0,4 , c _0,5 , c _0,6 , c _0,7 .

Then, the bank address is set to “1” at the timing when writing is performed in the block areas C _0,4 . Then, after the writing to the block area C _0,4 is completed, the image data for 16 pixels from the 48th to the 63rd is burst transferred. The image data for 16 pixels is stored in the block area D _0,4 of the bank 1 shown in FIG. 17 by setting “4” as the column address. The block area D _0,4 is an area composed of memory areas d _0,4 , d _0,5 , d _0,6 , d _0,7 .

As a result of the above processing, as shown in FIGS. 18 and 19, the block areas C _0,0 and C _0,4 of the bank ₀ and the block areas D _0,0 and D _0,4 of the bank 1 are changed from the 0th to the 63rd. Up to 64 pixels of image data are stored. Thereafter, similarly, the bank 0 and the bank 1 are switched, and the image data is burst transferred in units of 16 pixels, and the image data is sequentially stored in the SDRAM 4. The arrows in FIGS. 16 and 17 indicate the storage order in bank 0 and bank 1, respectively. After the image data of the 0th row of the two-dimensional image is stored in the direction of the arrow by the above-described procedure, the image data of the first row is similarly stored in the direction of the arrow, and the image data of each row is stored sequentially. The In addition, when the writing procedure for the SDRAM 4 is expressed using a block area, the block area C _0,0 → D _0,0 → C _0,4 → D _0,4 → C _0,8 → D _0,8 → C _{0, The} two-dimensional image data is sequentially stored in the order of ₁₂ →.

  Thus, in the row direction of the two-dimensional image, data is stored in the SDRAM 4 so that the bank 0 and the bank 1 are alternated every 16 pixels. As shown in FIG. 14, in the column direction, the bank 4 and the bank 1 are alternately stored in the SDRAM 4 for each row.

  In the example of this embodiment, the number of pixels in the row direction of the two-dimensional image is 320. Therefore, when the data of the first row is stored after switching the bank 0 and the bank 1 every 16 pixels, the first block of the first row is stored in the bank 0 again. It becomes the order. Therefore, the first block in the first row, that is, the 320th to 335th image data is temporarily stored in the buffer, and the next block, that is, the 336th to 351st image data is stored in the bank 0 first. To do. Next, the buffered 320th to 335th image data is stored in bank 1. As a result, in the column direction, bank 0 and bank 1 are alternately switched for each row to store image data. After the buffered 320th to 335th image data is stored in bank 1, even if the 352nd to 367th image data is stored in bank 1, row address switching does not occur. Access speed will never slow down. After that, if image data is stored while switching bank 0 and bank 1 every 16 pixels in the row direction again, bank 0 and bank 1 are alternately switched for each row in the column direction, and image data is stored. Will be.

  On the other hand, when the number of pixels in the row direction is an odd multiple of 16 pixels, bank 0 and bank 1 are switched in raster order, so that bank 0 and bank 1 are also line by row in the column direction. Since they are stored alternately, there is no need to use a buffer as described above.

  In this way, 2D image data to be subjected to MPEG processing is stored in the SDRAM 4 as a 2D image image while switching between bank 0 and bank 1. Then, in the column direction of the image, the data is stored in the SDRAM 4 so that the bank 0 and the bank 1 are alternated every row. For this reason, when attention is paid to the macro block, the image data is stored across a plurality of rows of the SDRAM 4, but no idle time is generated even when the row to be accessed is switched. Although this access procedure will be described in detail later, the row to be accessed for bank 0 is switched at the timing when data in bank 1 is accessed, and bank 1 is accessed at the timing when data in bank 0 is accessed. This is because it is possible to switch the row to be accessed.

  As shown in FIGS. 18 and 19, the image data for one horizontal line of the two-dimensional image data is stored in the memory area of the same row of bank 0 and the same row of bank 1 of the SDRAM 4 to store the two-dimensional image. When the data line moves to the next line, the storage areas of the bank 0 and bank 1 memory areas are also changed. Such a storage method has a demerit in terms of effective use of the memory area, but has an advantage in that the circuit configuration can be simplified. Therefore, this method is effective when there is a margin in the memory area.

  However, the above storage method is an example, and the present invention is not limited to this. That is, the first line of image data of the two-dimensional image data input in raster order is stored in the first row (bank 0 or bank 1) of the SDRAM 4, and then the image data of the second line is continued. You may take the method of storing in a line. Similarly, in each row of the SDRAM 4, the row to be stored is not changed corresponding to the horizontal line of the image data, and the image data is sequentially packed and stored. Also in this case, the image data for 16 pixels transferred at a time (that is, image data for one burst transfer) may be stored in the same row of the SDRAM 4. Thus, if the row address of the other bank is changed at the timing when one of the data in bank 0 and bank 1 is accessed, the processing speed can be increased. Or, conversely, the data size of one horizontal line of the two-dimensional image may be larger than the size that can be stored in one row of SDRAM 4 (the sum of the sizes that can be stored in one row of bank 0 and bank 1). Also in this case, there is no problem if the image data is stored in the same row of any bank in units of 16 pixels and the row address of each bank is changed in the middle of one horizontal line of the two-dimensional image. . That is, according to the present invention, the image data for 16 pixels in one row constituting the macro block is all stored in the same row in one bank, and the data for 16 pixels in the next row constituting the macro block is essentially stored. All the image data is stored in the same row of the other bank. With such a storage method, even when it is necessary to change the row address of one bank in accessing the image data in units of macroblocks, the access processing for the other bank always intervenes immediately before that. Therefore, the occurrence of idle time can be eliminated by changing the row address in the meantime.

  Next, processing for accessing the image data stored in the SDRAM 4 in units of macro blocks in order for the MPEG processing unit 2 to perform MPEG compression processing will be described. The access process includes a process for reading out image data in units of macroblocks to which the MPEG processing unit 2 performs an MPEG compression process, and a process for writing image data in units of macroblocks.

FIG. 20 is a timing chart of a process for accessing the image data stored in the SDRAM 4 by the memory control unit 3. FIG. 21 is a diagram showing an access order for the bank 0 of the SDRAM 4, and FIG. 22 is a diagram showing an access order for the bank 1 of the SDRAM 4. Further, FIG. 23 and FIG. 24 show a method of subsequently accessing the adjacent macroblock after accessing the macroblock by the method shown in FIG. 21 and FIG. FIG. 23 is a diagram showing an access order of the SDRAM 4 to the bank 0, and FIG. 24 is a diagram showing an access order of the SDRAM 4 to the bank 1. 20 to 24 are diagrams showing common features in the image data reading process and writing process in units of macroblocks. Further, each of the blocks C _0,0 in FIGS. 21 to 24, D _0,0, etc., each of the block areas C _0,0 in FIGS. 16 and 17 corresponds to D _0,0 and the like, described above It is assumed that two-dimensional image data is stored in the arrangement as shown in FIGS. 18 and 19 by the writing process.

First, image data read processing in units of macroblocks will be described. In FIG. 20, first, “0” is set to the bank address, “0” is set to both the row address and the column address, and image data for 16 pixels from the 0th to the 15th is burst transferred. . Specifically, the image data for 16 pixels stored in the block area C _0,0 of bank 0 shown in FIG. 21 is read. Note that the notation rules in FIG. 20 are the same as those in FIG.

On the other hand, as shown in FIG. 20, the bank address is set to “1” and the row address is set to “1” at the timing when the image data in the block area C _0,0 is read. After the reading process from the block area C _{0,0 is} completed, image data for 16 pixels from the 320th to the 335th is burst transferred. Specifically, the image data for 16 pixels stored in the block area _D1,0 of the bank 1 shown in FIG. 22 is read.

Further, as shown in FIG. 20, the bank address is set to “0” and the row address is set to “2” at the timing when the image data of the block area D _1,0 is read. After the reading process from the block area D _{1,0 is} completed, the image data for 16 pixels from the 640th to the 655th is burst transferred. Specifically, the image data for 16 pixels stored in the block area C _2,0 of bank 0 shown in FIG. 21 is read. The block area C _2,0 is an area composed of memory areas c _2,0 , c _2,1 , c _2,2 and c _2,3 . Here, for the bank 0, the access processing for the block area C _2,0 is performed after the access processing for the block area C _0,0 , so it is necessary to switch the row address to be accessed. Since the row address is switched at the timing when the data transfer to D _1,0 is performed, the data reading process is efficiently executed without generating a free time.

Then, at the timing when the readout processing of the image data of the block area C _{2, 0} is being performed, the row address along with the bank address is set to "1" is set to "3", the block area C _{2, 0} After the reading process ends, image data for 16 pixels from the 960th to the 975th is burst transferred. Specifically, the image data for 16 pixels stored in the block area D _3,0 of bank 1 shown in FIG. 22 is read. The block area D _3,0 is an area composed of memory areas d _3,0 , d _3,1 , d _3,2 , d _3,3 . Similarly, for bank 1, since access processing for block area D _3,0 is performed after access processing for block area D _1,0 , it is necessary to switch the row address to be accessed. Since the row address is switched at the timing when the data transfer to C _2,0 is performed, the data reading process is efficiently executed without causing a free time.

Through the above processing, from the 0th stored in the block areas C _0,0 and C _2,0 of the bank ₀ and the block areas D _1,0 and D _3,0 of the bank 1 shown in FIGS. Image data for 16 pixels up to 15th, image data for 16 pixels from 320th to 335th, image data for 16 pixels from 640th to 655th, and data for 16 pixels from 960th to 975th Image data is read out. If this image data is made to correspond to the image image of FIG. 14, it is image data for 4 rows in which the row direction is 16 pixels and the column direction is the same. That is, after that, similarly, the bank 0 and the bank 1 are switched, the image data is burst-transferred in units of 16 pixels, and the image data in the same column is sequentially read out in the row direction of 16 pixels. Therefore, it is possible to continuously read out image data of various blocks. By executing such processing for 16 rows, it is possible to continuously read out image data corresponding to a macroblock of 16 pixels vertically × 16 pixels horizontally.

In the description using FIGS. 20 to 22, the description has been made up to the point where the image data of the block area C _0,0 → D _1,0 → C _2,0 → D _3,0 is read. Thereafter, the image data in the block area in the same row are sequentially read out while alternately switching between the bank 0 and the bank 1. That is, C _0,0 → D _1,0 → C _2,0 → D _3,0 → C _4,0 → D _5,0 → C _6,0 → D _7,0 → C _8,0 → D _{9, 0 → C 10,0 → D 11,0 →} C 12,0 → D 13,0 → C 14,0 → by reading the order in the block area of the D _15,0, 16 vertical pixels × 16 horizontal pixels of the macro Image data corresponding to the block can be read out.

  Further, as described above, if the storage rules for bank 0 and bank 1 as shown in FIG. 14 are satisfied, the image data of different horizontal lines of the two-dimensional image are stored in the same row of the SDRAM 4. Also good. For example, it has been described that the image data of the first line and the second line of the two-dimensional image data may be stored in the memory area of the first row of the SDRAM 4. Also in this case, the data reading process in units of macroblocks can be performed at high speed. That is, by storing the image data while switching the bank in units of 16 pixels, it is possible to switch the row of the other bank while reading the image data from one bank. . As a result, even when an access row to the SDRAM 4 is changed, it is possible to perform a read process without causing a free time. Further, if the storage rules for bank 0 and bank 1 as shown in FIG. 14 are satisfied, one horizontal line of the two-dimensional image data may be stored across a plurality of rows of the SDRAM 4. Alternatively, the order in the column direction of each horizontal line of the two-dimensional image may be different from the order in the column direction stored in the SDRAM 4 or may be stored in discrete rows.

As described above, the image data can be read at a high speed in units of macroblocks, but the process of writing the image data in units of macroblocks by the MPEG processing unit 2 is the same. This writing process may also be performed in the access order shown in the timing chart shown in FIG. 20, FIG. 21, and FIG. That is, the image data may be written in the order of the block areas C _0,0 → D _1,0 → C _2,0 → D _3,0 → C _4,0 . As a result, both reading and writing of image data in units of macro blocks can be performed at high speed.

  A method of accessing an adjacent macroblock after accessing a macroblock of 16 pixels by 16 pixels by the above-described method will be described. Referring to the image in FIG. 14, after accessing a macroblock including the 0th to 15th pixel data, a process of subsequently accessing the macroblock including the 16th to 31st pixel data. It is.

Here, as described above, in the access to the macro block including the 0th to 15th pixel data, the block area to be accessed last is the block area D _15,0 of the bank 1. For this reason, when the macro block including the 16th to 31st pixel data is continuously accessed, since the first 16th to 31st pixel data is also stored in the bank 1, the bank 1 is continuously accessed. There is a need to. When the block area D _15,0 and the block area D _0,0 are in different rows of the SDRAM 4 (stored in different rows in this embodiment), processing for switching the row address occurs. However, the processing speed decreases.

  Therefore, in the present embodiment, when the adjacent macroblock is continuously accessed, the access direction is reversed with respect to the column direction. That is, as shown in FIGS. 23 and 24, the access order in the column direction is reversed for this macroblock as compared with the method shown in FIGS.

Specifically, first, performs access to the block area C _15,0, then accesses the block area D _14,0. Then, the same access is performed while switching between bank 0 and bank 1. In other _{words, C 15,0 → D 14,0 → C} 13,0 → D 12,0 → C 11,0 → D 10,0 → C 9,0 → D 8,0 → C 7,0 → D 6, By reading the block area in the order of ₀ → C _5,0 → D _4,0 → C _3,0 → D _2,0 → C _1,0 → D _0,0 Image data corresponding to the block can be read out. As a result, even when adjacent macroblocks are continuously accessed, access to bank 0 and bank 1 is always alternated throughout the processing, so that while accessing one bank, It is possible to perform processing for switching row addresses.

  Next, a method of storing image data in each memory area according to the type of data will be described with reference to FIG. Here, as shown in FIG. 13, the case where the image data is in the YUV 4: 2: 0 format will be described.

  In the timing chart shown in FIG. 25, the first two burst transfer processes are processes for luminance data. The latter two burst transfer processes are processes for color difference data. First, in the case of luminance data, four Y data are stored in one memory area. That is, the Y data of one pixel is 8 bits, and the memory area corresponding to one address of the SDRAM 4 in this embodiment can store 32 bits of data. Therefore, Y data for four pixels is stored in one address memory. It is stored in the area. At this time, the 32-bit data line for accessing the SDRAM 4 is divided into four equal parts and used for transferring Y data of four pixels. In this way, bank 0 stores 16 pixels of Y data in four memory areas corresponding to four addresses. Subsequently, in bank 1, Y data for 16 pixels is stored in four memory areas corresponding to four addresses.

  Next, a method for storing color difference data will be described. In this embodiment, two sets of U data and V data are packed and stored in one memory area. That is, U data and V data are both 8-bit data per pixel, and the memory area corresponding to one address of SDRAM 4 in this embodiment can store 32-bit data. Data of 4 pixels consisting of data is stored in a memory area of one address. At this time, the 32-bit data line for accessing the SDRAM 4 is divided into four equal parts and assigned to U data and V data for 4 pixels, respectively. In this way, bank 0 stores color difference data for 16 pixels in four memory areas corresponding to four addresses. Subsequently, in bank 1, color difference data for 16 pixels is stored in four memory areas corresponding to four addresses.

  In this way, by packing U data and V data and storing them in one memory area, the same transfer procedure is executed when accessing SDRAM 4 for luminance data and when accessing SDRAM 4 for color difference data. It becomes possible to do.

  Specifically, first, data access in units of macroblocks is performed on luminance data, and then data access in units of macroblocks is performed on color difference data in the same macroblock region (FIG. 25 shows luminance data). The timing at which the data access process and the data access process for the color difference data are just switched is shown.), The data access for the luminance data and the data access for the color difference data can be made the same procedure. However, in the case of the YUV 4: 2: 0 format, the number of U data and V data is halved in the row direction (vertical direction), so the processing for one macroblock is performed with luminance data. Half of the processing is sufficient.

{Third embodiment}
Next, a third embodiment of the present invention will be described. The image processing apparatus in the third embodiment is the same as the image processing apparatus described in FIG. The SDRAM 4 in the third embodiment is capable of storing 2 bytes (16 bits) of data in a memory area of one address. Unlike the first embodiment, the SDRAM 4 has eight consecutive Burst transfer processing that continuously accesses data to addresses is enabled. That is, the SDRAM 4 is a 16-bit DDR (double data rate) SDRAM that enables burst transfer of 128-bit (8 addresses × 16 bits) data.

  Also in this embodiment, a two-dimensional image is divided into blocks every 16 pixels in raster order, and as shown in FIG. 14, these blocks are assigned to banks 0 and 1 in a staggered manner and stored in the SDRAM 4. It will be.

  FIG. 26 is a timing chart when the raster control image data output from the input unit 1 is written into the SDRAM 4 by the memory control unit 3. FIG. 27 is a diagram showing the order of writing to the bank 0 of the SDRAM 4, and FIG. 28 is a diagram showing the order of writing to the bank 1 of the SDRAM 4. 29 is a diagram showing pixel numbers of image data stored in each memory area of bank 0, and FIG. 30 is a diagram showing pixel numbers of image data stored in each memory area of bank 1. is there.

27 and 28, the subscripts such as the memory areas e _0,0 and f _0,0 are the first subscript indicating the row number of the memory area, and the second subscript is the memory area. Indicates the column number. These notation rules are the same as those in the first embodiment. In addition, block areas E _0,0 , F _0,0, etc. in FIGS. 27 and 28 indicate blocks composed of eight memory areas. The subscript of the block area corresponds to the row number and column number of the first (leftmost) memory area included in the block area.

In FIG. 26, first, “0” is set to the bank address, “0” is set to both the row address and the column address, and image data for 16 pixels from the 0th to the 15th is burst transferred. . That is, since image data of 1 pixel is 8 bits, image data for 16 pixels (16 pixels × 8 bits) is burst transferred. The image data for 16 pixels is stored in the block area E _0,0 of bank 0 shown in FIG. The block area E _0,0 is formed from the memory areas e _0,0 , e _0,1 , e _0,2 , e _0,3 , e _0,4 , e _0,5 , e _0,6 , e _0,7. It is an area. The notation rules in FIG. 26 are the same as those in FIG.

On the other hand, as shown in FIG. 26, the bank address is set to “1” at the timing when image data for 16 pixels from the 0th to the 15th is written in the block area E _0,0 . Then, after writing to the block area E _0,0 , image data for 16 pixels from the 16th to the 31st is burst transferred. The image data for 16 pixels is stored in the block area F _0,0 of bank 1 shown in FIG. The block area F _0,0 is formed from the memory areas f _0,0 , f _0,1 , f _0,2 , f _0,3 , f _0,4 , f _0,5 , f _0,6 , f _0,7. It is an area.

Furthermore, the bank address is set to “0” at the timing when the image data for 16 pixels from the 16th to the 31st is written in the block area F _0,0 . Then, after writing to the block area F _0,0 , image data for 16 pixels from the 32nd to the 47th is burst transferred. The image data for 16 pixels is stored in the block area E _0,8 of the bank 0 shown in FIG. 27 by setting “8” as the column address. Block area E _{0, 8,} the memory area _{e 0,8, e 0,9, e 0,10} , e 0,11, e 0,12, e 0,13, e 0,14, from e _{0, 15} It is an area.

The bank address is set to “1” at the timing when writing is performed in the block areas E _0,8 . Then, after writing to the block areas E _0,8 , image data for 16 pixels from the 48th to the 63rd is burst transferred. The image data for 16 pixels is stored in the block area F _0,8 of the bank 1 shown in FIG. 28 by setting “8” as the column address. Block area F _{0, 8,} the memory area _{f 0,8, f 0,9, f 0,10} , f 0,11, f 0,12, f 0,13, f 0,14, from f _{0, 15} It is an area.

Through the above processing, as shown in FIGS. 29 and 30, the 0th to 63rd blocks are _{added to} the block areas E _0,0 and E _0,8 of the bank ₀ and the block areas F _0,0 and F _0,8 of the bank 1. Up to 64 pixels of image data are stored. Thereafter, similarly, the bank 0 and the bank 1 are switched, and the image data is burst transferred in units of 16 pixels, and the image data is sequentially stored in the SDRAM 4. The arrows in FIGS. 27 and 28 indicate the storage order in bank 0 and bank 1, respectively. After the image data of the 0th row of the two-dimensional image is stored in the direction of the arrow by the above-described procedure, the image data of the first row is similarly stored in the direction of the arrow, and the image data of each row is stored sequentially. The Further, if the write procedure for the SDRAM 4 is expressed using a block area, the block area E _0,0 → F _0,0 → E _0,8 → F _0,8 → E _0,16 → F _0,16 → C _{0 , 24} →... Sequentially stores the two-dimensional image data.

  Thus, in the row direction of the two-dimensional image, data is stored in the SDRAM 4 so that the bank 0 and the bank 1 are alternated every 16 pixels. As shown in FIG. 14, in the column direction, the bank 4 and the bank 1 are alternately stored in the SDRAM 4 for each row.

  As described in the second embodiment, when the number of pixels in the row direction is an even multiple of 16 pixels, a two-dimensional image is displayed for each row in the column direction by using a buffer. The bank 0 and the bank 1 are alternately stored. If the number of pixels in the row direction is an odd multiple of 16 pixels, there is no need to use a buffer.

  In this way, 2D image data to be subjected to MPEG processing is stored in the SDRAM 4 as a 2D image image while switching between bank 0 and bank 1. Then, the image is stored in the SDRAM 4 so that the bank 0 and the bank 1 are alternately arranged in the column direction. For this reason, when attention is paid to the macro block, the image data is stored across a plurality of rows of the SDRAM 4, but no idle time is generated even when the row to be accessed is switched. This access processing will be described in detail later. The row to be accessed for bank 0 is switched at the timing when the data in bank 1 is accessed, and bank 1 is accessed at the timing when the data in bank 0 is accessed. This is because it is possible to switch the row to be accessed.

  Further, as described in the first or second embodiment, the image data of the first line of the two-dimensional image data input in the raster order is stored in the first row (bank 0 or bank 1) of the SDRAM 4. Thereafter, a method may be used in which the image data of the second line is continuously stored in the first line of the SDRAM 4. Similarly, in each row of the SDRAM 4, the row to be stored corresponding to the line of the image data is not changed, and the image data may be sequentially packed and stored. Or, conversely, the data size of one horizontal line of the two-dimensional image may be larger than the size that can be stored in one row of SDRAM 4 (the sum of the sizes that can be stored in one row of bank 0 and bank 1). Also in this case, there is no problem if the image data is stored in the same row of any bank in units of 16 pixels and the row address of each bank is changed in the middle of one horizontal line of the two-dimensional image. . That is, according to the present invention, the image data for 16 pixels in one row constituting the macro block is all stored in the same row in one bank, and the data for 16 pixels in the next row constituting the macro block is essentially stored. All the image data is stored in the same row of the other bank.

  Next, processing for accessing the image data stored in the SDRAM 4 in units of macro blocks in order for the MPEG processing unit 2 to perform MPEG compression processing will be described. The access process includes a process for reading out image data in units of macroblocks to which the MPEG processing unit 2 performs an MPEG compression process, and a process for writing image data in units of macroblocks.

FIG. 31 is a timing chart of processing for accessing the image data stored in the SDRAM 4 by the memory control unit 3. FIG. 32 is a diagram showing an access order for the bank 0 of the SDRAM 4, and FIG. 33 is a diagram showing an access order for the bank 1 of the SDRAM 4. Further, FIG. 34 and FIG. 35 show a method of subsequently accessing adjacent macroblocks after accessing the macroblocks by the method shown in FIG. 32 and FIG. FIG. 34 is a diagram showing an access order of SDRAM 4 to bank 0, and FIG. 35 is a diagram showing an access order of SDRAM 4 to bank 1. FIG. 31 to FIG. 35 are diagrams showing features common to image data reading processing and writing processing in units of macroblocks. Further, FIG. 32 to each of the blocks E in FIG. 35 _0,0, F _0,0 and the like, each of the block areas E _0,0 in FIGS. 27 and 28 corresponds to F _0,0 and the like, described above It is assumed that two-dimensional image data is stored in the arrangement as shown in FIGS. 29 and 30 by the writing process.

First, image data read processing in units of macroblocks will be described. In FIG. 31, first, “0” is set to the bank address, “0” is set to both the row address and the column address, and image data for 16 pixels from the 0th to the 15th is burst transferred. . Specifically, the image data for 16 pixels stored in the block area E _0,0 of bank 0 shown in FIG. 32 is read. The notation rules in FIG. 31 are the same as those in FIG.

On the other hand, as shown in FIG. 31, the bank address is set to “1” and the row address is set to “1” at the timing when the image data in the block area E _0,0 is read. After the reading process from the block area E _{0,0 is} completed, the image data for 16 pixels from the 320th to the 335th is burst transferred. Specifically, the image data for 16 pixels stored in the block area _F1,0 of bank 1 shown in FIG. 33 is read.

Further, as shown in FIG. 31, at the timing when the image data read processing of the block area F _1,0 is performed, the bank address is set to “0” and the row address is set to “2”. After the reading process from the block area _{F1,0 is} completed, image data for 16 pixels from the 640th to the 655th is burst transferred. Specifically, the image data for 16 pixels stored in the block area E _2,0 of bank 0 shown in FIG. 33 is read. The block area E _2,0 is obtained from the memory areas e _2,0 , e _2,1 , e _2,2 , e _2,3 , e _2,4 , e _2,5 , e _2,6 , e _2,7. It is an area. Here, for the bank 0, the access processing for the block area E _2,0 is performed after the access processing for the block area E _0,0 , so that it is necessary to switch the row address to be accessed. Since the row address is switched at the timing when the data transfer to F _1,0 is performed, the data reading process is efficiently executed without generating a free time.

Then, at the timing when the readout processing of the image data of the block area E _{2, 0} is being performed, is set to "3" to the row address along with the bank address is set to "1", the block area E _{2, 0} After the reading process ends, image data for 16 pixels from the 960th to the 975th is burst transferred. Specifically, the image data for 16 pixels stored in the block area F _3,0 of bank 1 shown in FIG. 33 is read. The block area F _3,0 includes memory areas f _3,0 , f _3,1 , f _3,2 , f _3,3 , f _3,4 , f _3,5 , f _3,6 , and f _3,7. It is an area. Similarly, for bank 1, since access processing for block area F _3,0 is performed after access processing for block area F _1,0 , it is necessary to switch the row address to be accessed. Since the row address is switched at the timing when the data transfer to E _2,0 is performed, the data reading process is efficiently executed without generating a free time.

Through the above processing, from the 0th stored in the block areas E _0,0 and E _2,0 of the bank ₀ and the block areas F _1,0 and F _3,0 of the bank 1 shown in FIGS. Image data for 16 pixels up to 15th, image data for 16 pixels from 320th to 335th, image data for 16 pixels from 640th to 655th, and data for 16 pixels from 960th to 975th Image data is read out. If this image data is made to correspond to the image image of FIG. 14, it is image data for 4 rows in which the row direction is 16 pixels and the column direction is the same. That is, after that, similarly, the bank 0 and the bank 1 are switched, the image data is burst-transferred in units of 16 pixels, and the image data in the same column is sequentially read out in the row direction of 16 pixels. Therefore, it is possible to continuously read out image data of various blocks. By executing such processing for 16 rows, it is possible to continuously read out image data corresponding to a macroblock of 16 pixels vertically × 16 pixels horizontally.

In the description with reference to FIGS. 31 to 33, the description has been given to the point of reading the image data of the block area E _0,0 → F _1,0 → E _2,0 → F _3,0 . Thereafter, the image data in the block area in the same row are sequentially read out while alternately switching between the bank 0 and the bank 1. That is, E _0,0 → F _1,0 → E _2,0 → F _3,0 → E _4,0 → F _5,0 → E _6,0 → F _7,0 → E _8,0 → F _{9, 0 → E 10,0 → F 11,0 →} E 12,0 → F 13,0 → E 14,0 → by reading the order in the block area of the F _15,0, 16 vertical pixels × 16 horizontal pixels of the macro Image data corresponding to the block can be read out.

  As described above, if the storage rules for bank 0 and bank 1 as shown in FIG. 14 are satisfied, data of a plurality of horizontal lines of the two-dimensional image is stored in the same row of the SDRAM 4. Alternatively, one horizontal line of the two-dimensional image data may be stored across a plurality of rows of the SDRAM 4. Alternatively, the order in the column direction of each horizontal line of the two-dimensional image may be different from the order in the column direction stored in the SDRAM 4 or may be stored in discrete rows.

As described above, the image data can be read at a high speed in units of macroblocks, but the process of writing the image data in units of macroblocks by the MPEG processing unit 2 is the same. This writing process may also be performed in the access order shown in the timing chart shown in FIG. 31, FIG. 32, and FIG. That is, the image data may be written in the order of the block areas E _0,0 → F _1,0 → E _2,0 → F _3,0 → E _4,0 . As a result, both reading and writing of image data in units of macro blocks can be performed at high speed.

  The method for accessing the adjacent macroblocks after accessing the macroblocks of 16 pixels by 16 pixels by the method described above is the same as in the second embodiment. When the adjacent macroblock is subsequently accessed, the access direction is reversed with respect to the column direction. That is, as shown in FIGS. 34 and 35, the access in the column direction is reversed for this macroblock as compared with the method shown in FIGS.

First, access to the block area E _15,0, then accesses the block area F _14,0. Then, the same access is performed while switching between bank 0 and bank 1. In other _{words, E 15,0 → F 14,0 → E} 13,0 → F 12,0 → E 11,0 → F 10,0 → E 9,0 → F 8,0 → E 7,0 → F 6, By reading the block area in the order of ₀ → E _5,0 → F _4,0 → E _3,0 → F _2,0 → E _1,0 → F _0,0 Image data corresponding to the block can be read out. As a result, even when adjacent macroblocks are continuously accessed, access to bank 0 and bank 1 is always alternated throughout the entire process, so the other bank can be accessed while one bank is being accessed. It is possible to perform the process of switching the rows.

  Next, a method for storing image data in each memory area corresponding to the type of data will be described with reference to FIG. Here, as shown in FIG. 13, the case where the image data is in the YUV 4: 2: 0 format will be described.

  In the timing diagram shown in FIG. 36, the first two burst transfer processes are processes for luminance data. The latter two burst transfer processes are processes for color difference data. First, in the case of luminance data, two Y data are stored in one memory area. That is, the Y data of one pixel is 8 bits, and the memory area corresponding to one address of the SDRAM 4 in the present embodiment can store 16 bits of data. It is stored in the area. At this time, the upper 8 bits and the lower 8 bits of the 16-bit data line for accessing the SDRAM 4 are respectively used for Y data transfer for 2 pixels. In this way, bank 0 stores Y data for 16 pixels in eight memory areas corresponding to eight addresses. Subsequently, in bank 1, Y data for 16 pixels is stored in eight memory areas corresponding to eight addresses.

  Next, a method for storing color difference data will be described. In this embodiment, a set of U data and V data is packed and stored in one memory area. That is, U data and V data are both 8-bit data per pixel, and the memory area corresponding to one address of SDRAM 4 in this embodiment can store 16-bit data. Data for two pixels consisting of data is stored in a memory area of one address. At this time, among the 16-bit data lines accessing the SDRAM 4, for example, the upper 8 bits are assigned for U data transfer and the lower 8 bits are assigned for V data transfer. In this way, the bank 0 stores the color difference data for 16 pixels in the eight memory areas corresponding to the eight addresses. Subsequently, in bank 1, color difference data for 16 pixels is stored in eight memory areas corresponding to eight addresses.

  In this way, by packing U data and V data and storing them in one memory area, the same transfer procedure is executed when accessing SDRAM 4 for luminance data and when accessing SDRAM 4 for color difference data. It becomes possible to do.

  Specifically, first, data access in units of macroblocks is performed on luminance data, and then data access in units of macroblocks is performed on color difference data in the same macroblock region (FIG. 36 shows luminance data). The timing at which the data access process and the data access process for the color difference data are just switched is shown.), The data access for the luminance data and the data access for the color difference data can be made the same procedure. However, in the case of the YUV 4: 2: 0 format, the number of U data and V data is halved in the row direction (vertical direction), so the processing for one macroblock is performed with luminance data. Half of the processing is sufficient.

  The three embodiments of the present invention have been described. In each of the above embodiments, the SDRAM is described as an example of the memory. However, the present invention can be applied not only to the SDRAM but also to the DRAM in general.

1 is an overall schematic diagram of an image processing apparatus according to an embodiment. It is a figure which shows the storage image with respect to DRAM of the two-dimensional image data in 1st Embodiment. FIG. 4 is a write timing diagram for the SDRAM in the first embodiment. FIG. 5 is a diagram showing a writing order with respect to bank 0; FIG. 5 is a diagram showing a writing order with respect to bank 1; FIG. 6 is a diagram showing pixel numbers of image data stored in bank 0. FIG. 4 is a diagram showing pixel numbers of image data stored in a bank 1. It is a figure which shows the access timing in the macroblock unit in 1st Embodiment. FIG. 10 is a diagram showing an access order to bank 0. FIG. 5 is a diagram showing an access order to bank 1; It is a figure which shows the access image in the macroblock unit using the bank 0 and the bank 1. FIG. FIG. 10 is a timing diagram specifically showing a writing method for one address. It is a figure which shows a YUV4: 2: 0 format. It is a figure which shows the storage image with respect to DRAM of the two-dimensional image data in 2nd and 3rd Embodiment. FIG. 10 is a write timing diagram for the SDRAM in the second embodiment. FIG. 5 is a diagram showing a writing order with respect to bank 0; FIG. 5 is a diagram showing a writing order with respect to bank 1; FIG. 6 is a diagram showing pixel numbers of image data stored in bank 0. FIG. 4 is a diagram showing pixel numbers of image data stored in a bank 1. It is a figure which shows the access timing in the macroblock unit in 2nd Embodiment. FIG. 6 is a diagram showing an access order to bank 0. FIG. 4 is a diagram showing an access order to bank 1; It is a figure which shows the access order with respect to the bank 0 at the time of accessing an adjacent macroblock. It is a figure which shows the access order with respect to the bank 1 at the time of accessing an adjacent macroblock. FIG. 10 is a timing diagram specifically showing a writing method for one address. FIG. 10 is a write timing diagram for the SDRAM in the third embodiment. FIG. 5 is a diagram showing a writing order with respect to bank 0; FIG. 5 is a diagram showing a writing order with respect to bank 1; FIG. 6 is a diagram showing pixel numbers of image data stored in bank 0. FIG. 4 is a diagram showing pixel numbers of image data stored in a bank 1. It is a figure which shows the access timing in the macroblock unit in 3rd Embodiment. FIG. 10 is a diagram showing an access order to bank 0. FIG. 5 is a diagram showing an access order to bank 1; It is a figure which shows the access order with respect to the bank 0 at the time of accessing an adjacent macroblock. It is a figure which shows the access order with respect to the bank 1 at the time of accessing an adjacent macroblock. FIG. 10 is a timing diagram specifically showing a writing method for one address.

Explanation of symbols

3 Memory control unit 4 SDRAM

Claims (21)

A method for accessing a DRAM comprising a first bank and a second bank, comprising:
A first step of inputting a two-dimensional image to be processed in MPEG in raster order;
The row direction data of the two-dimensional image is stored in the DRAM every eight pixels while alternately switching the first bank and the second bank, and the column direction data of the two-dimensional image is the same as that of the DRAM. A second step of storing in the bank;
A DRAM access method comprising: The DRAM access method according to claim 1, further comprising:
By accessing the image data stored in the second step in units of 8 pixels while alternately switching the first bank and the second bank, a macroblock for MPEG processing of 16 pixels vertically × 16 pixels horizontally The third step of accessing
A DRAM access method comprising: The DRAM access method according to claim 2, comprising:
The third step includes
After accessing 8-pixel image data in the m-th row (m is an integer not smaller than 0 and not larger than 14) in the macroblock stored in the first bank, the next 8 in the raster order stored in the second bank. After accessing the image data of the pixels, and then accessing the image data of 8 pixels in the (m + 1) th row in the macroblock stored in the first bank, the next in the raster order stored in the second bank Accessing 8-pixel image data;
A DRAM access method comprising: The DRAM access method according to claim 1, comprising:
The second step includes
Image data of the nth row (n is an integer of 0 or more) of the two-dimensional image is stored in the storage area of the nth row of the first bank and the second bank, and the image data of the (n + 1) th row is stored. In the storage area of the (n + 1) th row of the first bank and the second bank,
A DRAM access method comprising: The DRAM access method according to claim 4, comprising:
The third step includes
After accessing 8-pixel image data of the m-th row (m is an integer of 0 to 14) in the macroblock stored in the n-th row of the first bank, the n-th row of the second bank Next, the image data of the next 8 pixels is accessed in the raster order stored, and then the image data of 8 pixels of the (m + 1) th row in the macro block stored in the (n + 1) th row of the first bank is accessed. And accessing the next 8-pixel image data in the raster order stored in the (n + 1) th row of the second bank.
A DRAM access method comprising: A DRAM access method according to any one of claims 1 to 5,
The DRAM can store 16-bit data at one address, and each pixel of the two-dimensional image has 8-bit information, so that the first and second banks of the DRAM are the same. A DRAM access method characterized in that image data of 8 pixels is stored for four consecutive addresses in a row. The DRAM access method according to claim 6, comprising:
8. A DRAM access method, wherein 8-pixel image data continuous in a raster order is burst transferred to the DRAM. A DRAM access method according to claim 6 or 7,
When the image data stored in the DRAM is Y (luminance) data, Y data for two pixels is stored for one address of the DRAM. A DRAM access method according to any one of claims 6 to 8, comprising:
When the image data stored in the DRAM is U, Y (color difference) data, a set of U data and V data is stored for one address of the DRAM. Method. A method for accessing a DRAM comprising a first bank and a second bank, comprising:
A first step of inputting a two-dimensional image to be processed in MPEG in raster order;
The row direction data of the 2D image is stored in the DRAM while alternately switching the first bank and the second bank every 16 pixels, and the column direction data of the 2D image is stored for each row. A second step of storing in the DRAM such that the first bank and the second bank alternate;
A DRAM access method comprising: The DRAM access method according to claim 10, further comprising:
By accessing the image data stored in the second step in units of 16 pixels while alternately switching the first bank and the second bank, a macroblock for MPEG processing of 16 pixels vertically × 16 pixels horizontally The third step of accessing
A DRAM access method comprising: The DRAM access method according to claim 11, comprising:
The third step includes
After accessing the image data of 16 pixels in the m-th row (m is an integer not smaller than 0 and not larger than 14) in the macro block stored in the first bank, next, in the macro block stored in the second bank Accessing the image data of 16 pixels in the (m + 1) th row;
A DRAM access method comprising: A DRAM access method according to claim 11 or claim 12,
The third step is characterized in that when accessing adjacent macroblocks on a two-dimensional image continuously, the access order in the column direction is reversed for the adjacent macroblocks. Method. A DRAM access method according to claim 12, comprising:
The third step includes
3. After accessing a macroblock according to the process of claim 2, when continuously accessing a macroblock adjacent to the macroblock, the kth in the macroblock stored in the first bank. After accessing the 16-pixel image data in the row (k is an integer from 1 to 15), next, the 16-pixel image data in the (k−1) -th row in the macroblock stored in the second bank. The process of accessing,
A DRAM access method comprising: The DRAM access method according to any one of claims 10 to 14,
The DRAM can store 32-bit data at one address, and each pixel of the two-dimensional image has 8-bit information, so that the first and second banks of the DRAM are the same. A DRAM access method, wherein 16-pixel image data is stored at four consecutive addresses in a row. The DRAM access method according to any one of claims 10 to 14,
The DRAM can store 16-bit data at one address, and each pixel of the two-dimensional image has 8-bit information, so that the first and second banks of the DRAM are the same. A DRAM access method characterized in that image data of 16 pixels is stored at eight consecutive addresses in a row. The DRAM access method according to claim 15 or 16, comprising:
A DRAM access method characterized in that image data of 16 pixels continuous in raster order is burst transferred to the DRAM. The DRAM access method according to claim 15, comprising:
A DRAM access method, wherein when the image data stored in the DRAM is Y (luminance) data, Y data for four pixels is stored for one address of the DRAM. The DRAM access method according to claim 15 or 18,
If the image data stored in the DRAM is U, Y (color difference) data, two sets of U data and V data are stored for one address of the DRAM. how to access. The DRAM access method according to claim 16, comprising:
When the image data stored in the DRAM is Y (luminance) data, Y data for two pixels is stored for one address of the DRAM. The DRAM access method according to claim 16 or 20,
When the image data stored in the DRAM is U, Y (color difference) data, a set of U data and V data is stored for one address of the DRAM. how to access.

Images