JP2863096B2 - Image decoding device by parallel processing - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding apparatus by parallel processing for decoding coded image signals in parallel.

[0002]

2. Description of the Related Art When digitally represented image data is transmitted or stored, encoding is performed to reduce the amount of data. As an encoding method, there is a method of reducing redundancy by utilizing temporal or spatial correlation of image information (image data).

As a method utilizing the temporal correlation, there are methods of encoding a difference between two consecutive screens (frames) and detecting motion of an image to perform motion compensation.
As a method using spatial correlation, an image is divided into blocks of a predetermined size (for example, 8 pixels each in the vertical and horizontal directions), data in the blocks are subjected to orthogonal transform, and transform coefficients are scan-converted. Some (for example, rearrange from low-frequency components to high-frequency components) and perform variable-length coding. An image coding method (hereinafter, abbreviated as MPEG2), which is being standardized by the Moving Picture Expert Group (MPEG), uses the above two methods in combination.
The provisional recommendation for MPEG2 is “Generic Codingof Moving Pi
ISO / IE entitled “ctuers and Associated Audio”
C13818-2.

FIG. 20 shows an example of the configuration of an image decoding apparatus that decodes data encoded by such a method. In FIG. 20, a buffer control unit 11, a variable length decoder 1
2. The decoding process is performed by the scan converter 13, the inverse quantizer 14, the inverse DCT unit 15, and the motion compensation image reproducing unit 16. Here, the parts 12 to 16 are combined as the decoding processing unit 17. Reference numeral 18 denotes a display control unit. Hereinafter, 10 is referred to as a decoder. Reference numeral 50 denotes a memory, which comprises a buffer memory 51 and frame memories (memory for three I, P, and B frames described later) 52, 53, and 54. Further, reference numeral 100 denotes an input bit stream representing an encoded image, and 200 denotes an output reproduced image. Also,
Dotted lines from the motion compensation image reproducing unit 16 indicate writing.

Next, the operation will be described. The input bit stream 100 is stored in the buffer memory 5 as buffer write data 40 under the control of the buffer controller 11.
1 is stored. The buffer read data 41 read from the buffer memory 51 is subjected to variable length decoding by the variable length decoder 12.

Although not all data are variable-length coded, fixed-length codes are also decoded by the variable-length decoder 12. Next, after the order of the data is rearranged by the scan converter 13, the data is inversely quantized by the inverse quantizer 14. Next, the inverse DCT unit 15 performs an inverse discrete cosine transform. The motion-compensated image reproducing unit 16 performs reproduction in consideration of the motion of the image. In MPEG2, a temporally intermediate frame (here, a B frame) is predicted from both a temporally earlier frame (here, an I frame) and a temporally later frame (here, a P frame). for that reason,
To reproduce the B frame, it is necessary to read out the predicted image read data 42 and 43 of the I frame and the P frame which have been decoded in advance from the frame memories 52 and 53 (MPE).
In G2, a later P frame is decoded prior to a B frame). The B frame is reproduced by the motion-compensated image reproducing unit 16 based on the predicted image read data 42 and 43 and the prediction error output from the inverse DCT unit 15, and is written into the frame memory 54 as reproduced image write data 44. The I, P, and B frames in the frame memories 52, 53, and 54 are read from each memory in a predetermined order (the B frame data 45 is read in FIG. 20), and an output reproduced image 200 is output. In the following description, 40 to 4
5 may be simply data.

[0007] The present invention is applicable to an apparatus for processing any image of MPEG2.
Let us consider a case where an HDTV image defined as a high level is reproduced. One frame of the HDTV image is composed of 1920 horizontal pixels and 1080 vertical lines as shown in FIG. This is divided into 16 pixels both horizontally and vertically. A unit of one division is called a macroblock (hereinafter abbreviated as MB).
HDTV images are 120 MB wide and 68 MB high, 8 in total.
Divided into 160 MB.

One MB is composed of a luminance signal of 16 × 16 pixels (hereinafter abbreviated as Y) and two types of color signals of 8 × 8 pixels of blue and red (hereinafter abbreviated as Cb and Cr). . 16
The Y signal of × 16 pixels is divided into four to form a block of four 8 × 8 pixels. Thus, an MB consists of six 8 × 8 pixel blocks. If one pixel is represented by 8 bits, it becomes 3072 bits per MB. As shown in FIG. 21, 8167 MB per frame has 25067520 bits. As shown in FIG. 20, three frames have 75202560 bits, and when a buffer capacity of 9787392 bits defined by MPEG is added, it becomes 89413632 bits. This corresponds to a capacity of about 5.33 16 Mbit memory elements, and requires six 16 Mbit memory elements.

Now, the decoder 10 shown in FIG.
Estimate the data transfer rate between. The data 40 to be written into the buffer memory 51 has a maximum of 80 Mbit / sec from the high level rule of MPEG2. Assuming that the data 41 read from the buffer memory 51 has a maximum buffer capacity of 9787392 bits in one frame, the maximum transfer rate is 9787392 bits / frame × 30 frames / second =
293621760 bits / sec. Regarding the predicted image read data 42 and 43, the write data 44, and the reproduced image read data 45, assuming integer pixel frame prediction, the transfer rates are all the same, and are as follows. 3072 bits / MB x 8160 MB / frame x 30
Frames / sec = 752025600 bits / sec. The sum of the above results in about 3400 Mbits / sec.
Therefore, when the data bus width between the decoder 10 and the memory 50 is 32 bits, the transfer speed is 100 MHz or more, and when the data bus width is 64 bits, the transfer speed is 50 MHz or more. Thus, very high-speed data transfer is required.

Next, the operation speed of the decoding processing unit 17 is set to the inverse DC
A trial calculation is made using the T unit 15 as an example. The inverse DCT is executed in units of 8 × 8 pixels, that is, in units of blocks. Now, if inverse DCT is performed by inputting data of 64 pixels one clock at a time, 64 clocks per block. Therefore, the operation clock is 8160 MB / frame × 6 blocks / MB × 64 clocks / block × 30 frames / sec = 94 MHz. As described above, HDTV decoding requires high-speed data transfer and high-speed operation.

As a method for realizing high-speed processing, there is parallel processing. This is a method in which the processing is divided into a plurality of parts and each processing speed is reduced. It is possible to perform parallel processing using the features of the input bit stream 100 of MPEG2. As shown in FIG. 21, a group of macroblocks in one horizontal row is called a slice. Further, in the present invention, slices 1 to 12
1 to MB240 are referred to as slice 2. MPE
In G2, one horizontal row of macroblocks can be further divided into a plurality of macroblock groups, each of which is called a slice. In the present invention, the slices are referred to as described above for convenience of explanation. In the case of FIG. 21, one frame is composed of 68 slices.

A feature of the input bit stream 100 of MPEG2 is that each slice has a leading identifier. Therefore, it is possible to divide one frame into a plurality of slice groups and process them in parallel.

FIG. 22 shows a configuration example of such parallel processing. In this example, the screen is divided into upper and lower parts. The partial decoder A processes the upper half screen, and the partial decoder B processes the lower half screen. The memory uses six 16-megabit memory elements as described above, and stores data for the upper half screen in the memory A and data for the lower half screen in the memory B. With this configuration, if the upper and lower screens are decoded simultaneously, the processing speed is reduced.

[0014]

In MPEG, motion compensation prediction is performed. The vertical motion compensation range is set to a maximum of 8 slices at both the upper and lower sides. Therefore, the predicted image read data 4 for the MB to be decoded
The reading of 2,43 (FIG. 20) covers a range of 8 slices above and below.

The parallel processing having the configuration shown in FIG. 22 has the following problems. 8 from the bottom of the upper half screen of the P and B frames
The decoding of the slice range requires not only the memory A but also the predicted image data of the memory B. While the partial decoder A accesses the memory B, the decoding of the lower half screen by the partial decoder B stops. Will be.

Similarly, for decoding in the range of 8 slices from the top of the lower half screen of the P and B frames,
The prediction image data in the memory A is required, and the partial decoder B
Will access the memory A, the decoding of the upper half screen by the partial decoder A will be stopped.

As can be seen from the above-described calculation of the memory data transfer rate, the readout of the predicted image readout data 42 and 43 requires a larger amount of data than the writing of data 40 into the buffer memory 51 and the reading 41 of data 41. It has been found that transfer is required, and stopping the decoding due to contention of memory access for a long period of time lowers the efficiency of parallel processing.

Another problem of the parallel processing according to the configuration of FIG. 22 is that the control of the memory becomes complicated. Although it has already been described that HDTV decoding requires six 16-megabit memory elements, the configuration of FIG.
The memories A and B are used separately for each memory. If the data width of one memory element is 16 bits, the data width of three memory elements is 48 bits. Since one pixel data is represented by 8 bits, 48 bits correspond to 6 pixel data. However, a block serving as a unit of decoding is 8 × 8 pixels,
Not a multiple of six. Therefore, the memory address cannot be divided for each block, and the memory control becomes complicated.

An object of the present invention is to solve the problems in the above-described image decoding apparatus having a parallel configuration, and to provide an image decoding apparatus having a parallel configuration which has less memory contention and is therefore more efficient.

[0020]

An image decoding apparatus based on parallel processing according to the present invention has N partial decoders and at least N + 1 memory groups. N + 1 memory groups are divided and stored so that the upper image is allocated to the small memory group, and the k-th partial decoder can access the k-th memory group and the k + 1-th memory group.

Further, out of the N partial decoders, any two partial decoders perform decoding so that images in the same memory group are not decoded in parallel.

The k-th partial decoder accesses at least the k-th memory group to start decoding, and after completion of image decoding in the k-th memory group, accesses at least the (k + 1) -th memory group. Perform decryption. The (k-1) -th partial decoder accesses at least the (k-1) -th memory group to start decoding, and after completion of image decoding in the (k-1) -th memory group, accesses the at least the k-th memory group. The completion of image decoding in the k-th memory group by the k-th partial decoder is earlier than the completion of image decoding in the (k-1) -th memory group by the (k-1) -th partial decoder. Is decrypted.

When the memory area for storing the reproduced image data being decoded and the memory area for storing the reproduced image data being displayed and output are the same, the data writing of the reproduced image means the data reading to be displayed. Must be controlled so as not to overtake (hereinafter, this is referred to as overtaking control).
Therefore, for frames that do not require overtaking control, the N partial decoders start decoding simultaneously, and when overtaking control is needed, the decoding start of the (k + 1) th partial decoder is started from the kth partial decoding start. The decoding start timing of each partial decoder is controlled so as to be delayed.

In addition, a predetermined amount of memory area for writing reproduced image data is allocated to decoding of a frame that originally requires overtaking control, and advance decoding can be performed without waiting for reading of image data for display. To

The N partial decoders access the N memory groups to perform decoding, and control the decoding so that image data for display output is read from the remaining memory groups.

The decoding start timing is controlled so that the decoding start by the k-th partial decoder is earlier than the decoding start by the (k + 1) -th partial decoder for the decoding of all the frames.

The I, P, and B frame image data are divided and stored in N + 1 memory groups in slice units, and bit stream data for decoding each slice is stored in the same memory group as each slice. Separately store.

Further, all the header information in the bit stream is stored in at least N memory groups for the N partial decoders.

When N = 2, all bit stream data are stored in the first memory group and the third memory group.

When N = 2, the second memory group stores the image data stored in the second memory group and the bits necessary to decode the image data of the upper and lower eight slices. The stream data is stored.

[0031]

According to the present invention, for N partial decoders,
Since there are N + 1 or more memory groups, it is possible to provide timing for the k-th partial decoder to access both the k-th memory group and the k + 1-th memory group.
During that timing, it is possible to read the predicted image data necessary for decoding the lower eight slices of the k-th memory group from the (k + 1) -th memory group, and to decode the upper eight slices of the (k + 1) -th memory group. It is possible to read out predicted image data from the k-th memory group. During this period, the possibility of other partial decoders accessing the k-th and (k + 1) -th memories is reduced, so that the effect of parallel processing can be enhanced.

Further, since a plurality of partial decoders do not decode slices in the same memory group, memory contention due to writing of reproduced image data can be avoided, so that efficient parallel decoding becomes possible.

Further, the completion of image decoding in the k-th memory group by the k-th partial decoder is earlier than the completion of image decoding in the (k-1) -th memory group by the (k-1) -th partial decoder. The operation is as follows. That is, after the k-th partial decoder decodes the upper eight slices of the (k + 1) -th memory group, the k-th partial decoder does not need to read predicted image data from the k-th memory group.
The -1st partial decoder can read predicted image data from the kth memory group.

For frames that do not require overtaking control (especially for I and P frames, overtaking control can be made unnecessary), all N partial decoders have a decoding time for one frame. Therefore, a margin of processing time can be obtained.

In addition, by allocating a memory area for writing reproduced image data for decoding of a frame requiring overtaking control, the decoding time can be extended, so that a margin of processing time can be obtained. Can be.

Further, by reading and writing predicted image data / writing reproduced image data and reading image data for display output by accessing different memory groups, the data transfer efficiency between the decoding device and the memory is improved. Can be improved.

In addition, for decoding of all frames regardless of whether or not the overtaking control is necessary, the decoding start timing is advanced earlier for the partial decoder for decoding the upper slice. Since the required memory area is small and the decoding time for one frame can be given to all of the N partial decoders, a margin for the processing time can be obtained.

Further, since the data of the bit stream for decoding the slices in each memory group is stored in one memory group, the bit stream can be read from the buffer. Competition can be prevented.

Further, by storing the header information in at least N memory groups in a redundant manner, the N partial decoders can individually read the header information when decoding is started.

When N = 2, that is, when two partial decoders and three memory groups are used, the first partial decoder can always access the first memory group, Can always access the third memory group. Therefore, by storing and decoding all the bit stream data in the first and third memory groups, that is, the bit streams of the upper and lower half screens are respectively stored in the first and third memory groups.
By allocating to one memory area, buffer control becomes easy.

When N = 2, the image data (the number of slices) in the first and third memory groups are replaced with the image data (the number of slices) in the second memory group as in the embodiment described later. In some cases, it is better to assign more. At this time, the buffer areas in the first and third memory groups are reduced. In the second memory group, not only the bit stream data necessary for decoding the image data in the second memory group, but also the bit stream data necessary for decoding the upper and lower eight slices of image data. Is stored, the bit stream data to be stored in the first and third memory groups can be reduced.

[0042]

【Example】

Embodiment 1 Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
This will be described below.

FIG. 1 is a basic configuration diagram of the present embodiment. The internal configuration of the partial decoder A101 and the partial decoder B102 is basically the same as the decoder 10 of FIG. Note that FIG.
The same reference numerals indicate the same parts. However, the buffer control unit (FIG. 2 described later) has a function of separating slice data, and the display control unit (FIG. 2 described later) uses the partial decoder A,
It has a function of switching the outputs of B 101 and 102. The memories A501 to C503 are two 16-megabit memory elements each having a data width of 16 bits. Therefore, the bit width of each memory group (hereinafter, simply referred to as memory unless necessary) is 32 bits, and the partial decoders A,
B 101 and 102 each have a memory data width of 64 bits (hereinafter, only partial decoders A and B except when necessary)
).

FIG. 2 schematically shows the operation of the present embodiment. The same input bit stream 100
Is input to the partial decoders A and B. Partial decoders A and B
The header control and slice separation are performed by the buffer control unit in the block.

In this embodiment, 1 to 24 are stored in the memory A501.
It is assumed that image data of slices, image data of 25 to 44 slices are allocated to the memory B502, and image data of 45 to 68 slices are allocated to the memory C503 (hereinafter simply referred to as memories A to C except when necessary). Therefore, the header data and the data of 1 to 24 slices in the input bit stream 100 are stored in the buffer area of the memory A, and the header data and the data of 25 to 44 slices are stored in the buffer area of the memory B. Write to the buffer area of the memory C. The header data is redundantly written to the memories A and B so that the partial decoder A and the partial decoder B can read the header data and start decoding. Since the memory A is always occupied by the partial decoder A, writing to the memory A is performed by the partial decoder A. Similarly, writing to the memory C is performed by the partial decoder B. However, since the memory B has a period obtained by the partial decoder A and a period obtained by the partial decoder B, writing to the memory B is performed by the partial decoder acquiring the memory B. It is assumed that the input bit stream 100 has been written to the memory B by the partial decoder A.
At this time, the partial decoder B also has the same input bit stream 1
Since 00 has been received, the amount of data written by the partial decoder A to the memory B can be analyzed, and the buffer storage amount can be known.

Next, at a predetermined timing, the partial decoder A reads the header data in the memory A,
The stream data for the slice and, if necessary, the predicted image data are read out and decoded by the decoding processing unit. 24
After the decoding up to the slice is completed, the memory B is accessed to perform decoding up to 25 to 34 slices. Similarly, at a predetermined timing, the partial decoder B reads the header data in the memory B, further reads the stream data for 35 to 44 slices and, if necessary, the prediction image data, and decodes the data by the decoding processing unit. When decoding of up to 44 slices is completed, the memory C is accessed to decode 45 to 68 slices.

The image data decoded as described above is
Read from the top line. In a so-called progressive image, all lines are sequentially read from a first line to a 1080th line. In an interlaced image, for example,
First, read only the odd lines to get the odd fields,
Next, only the even lines are read to obtain even fields.
The reading of these data is performed by a partial decoder acquiring a memory storing the data to be read,
By switching the outputs of the two partial decoders, a continuous output reproduced image 200 is obtained.

FIG. 3 shows the timing of the decoding and output reproduction image 200. Here, I, P1, B1,
The data of the input bit stream 100 is received in the order of the B2, P2, and B3 frames, and I, B1, B2, P1, B3
An output reproduction image 200 is obtained in the order of frames. Further, the output assumes interlacing. Also,
The I-frame outputs a reproduced image 1.5 frames after the start of decoding.

In the figure, squares indicated by I, P1, B1, etc. shown in the middle section indicate frame memories 52, 53, 54 in FIG. An arrow pointing to the frame memory indicates that writing is to be performed, and an arrow exiting the frame memory indicates that reading is to be performed. When decoding an I-frame,
Only writing of the decoded reproduced image data is performed. P
At the time of decoding one frame, predicted image data is read from the I frame, and the reproduced image data is written to the P1 frame memory. In the latter half of P1 decoding, reading of odd fields of the I frame is also performed. Note that decoding of each frame may be completed within one frame period. Similarly, when checking the access of the frame memory, when decoding the B frame,
It can be seen that writing and reading are performed on the same frame memory. Explaining the decoding of the B2 frame, in the area where the output of the reproduced image of the B1 frame in the frame memory of the B frame has been completed, the writing of the B2 frame can be performed. In the area where the writing has not been completed, it is necessary to wait for the writing of the B2 frame. As a matter of course, the decoding and writing of the B2 frame must be completed before the output timing of the reproduced image of the B2 frame. In such a case,
As described above, this is called a case where overtaking control is necessary.

In consideration of the above, for the I frame and the P frame, the partial decoder A for decoding the upper half screen and the partial decoder B for decoding the lower half screen start decoding simultaneously,
For B frames that require overtaking control, parallel decoding is possible by delaying the decoding start of the partial decoder B that decodes the lower half screen by 1/4 frame from the decoding start of the partial decoder A that decodes the upper half screen become. As described above, this embodiment has an advantage that the decoding can be performed in parallel only by the frame memories for three frames.

FIG. 4 shows the timing of parallel decoding for I and P frames (see FIG. 3) that do not require overtaking control, and the state of memory access in each period. During the period, the partial decoder A starts decoding the upper half screen while accessing the memory A, and outputs a reproduced image for displaying even-numbered fields. During this period, the partial decoder B starts decoding the lower half screen while accessing the memory B. During this time, the partial decoder B can also access the predicted image data stored in the memory C as needed. In the data transfer diagram corresponding to the period to in FIG. 4, the broken line data 42 and 43 read from the memory C503 by the partial decoder B102 correspond to this. The write data 40 of the input bit stream 100 received during the period is stored in the memory A501 and the memory B50.
2. Since it is not specified which of the memories C503 should be written, this is also shown by a broken line.

The period is the same as the period except that the output reproduced image 200 is output from the memory B502 via the partial decoder B102.

In the period, the output reproduced image 200 is output from the memory C 503 via the partial decoder B 102. The partial decoder B102 decodes the memory C503 while accessing it, and reads out the predicted image data 42 and 43 from the memory B502 as necessary. If the partial decoder A101 performs decoding at a rate that leaves the lower eight slices or more in the memory A501 by the period (there is no need to read out a predicted image for motion compensation from the memory B502), and the partial decoder B102 If decoding is performed at a speed at which decoding of the upper eight slices or more in C503 is completed, it is possible to avoid contention of the memory B502 for reading a predicted image.
Even if the above-described relationship of the decoding speed is not satisfied, even if the partial decoder A101 decodes all the slices in the memory A501 by the period, for example, there is a possibility that the contention of the memory B502 may occur. Very few. This is because the partial decoder A101 has the memory B502
It is necessary to perform motion compensation from the bottom (for example, when an object moves upward) when the predicted image data in
Conversely, the partial decoder B102 needs the predicted image data in the memory B502 when performing motion compensation from the upper side (such as when the object moves downward), and in the opposite direction within one frame. This is because it is unlikely that the motion compensation from the same is required at the same time.

In order to avoid contention, the decoding by the partial decoder A101 is performed by the lower
The slice may be interrupted and resumed later in the period, or the decoding by the partial decoder A101 may be advanced as far as possible by the period, and may be interrupted when a conflict occurs, Further, if a conflict occurs, the memory B
502 may be temporarily switched to the partial decoder A101 to perform decoding without interruption.

In any case, by setting the decoding completion time point a of the slices 35 to 44 in the memory B502 by the partial decoder B102 to a time point before the decoding completion time b of the slice in the memory A501 by the partial decoder A101, memory contention occurs. Can be reduced, thereby enabling efficient parallel decoding (see FIG. 2).

The operation in the period is the same as that in the period, but the memory B502 is mainly accessed by the partial decoder A101.

FIG. 5 shows the timing of the parallel decoding for the B2 frame (see FIG. 3) requiring the overtaking control,
The state of memory access in each period is shown. Note that the storage states of the memories A501 to C503 are indicated not by the slice numbers but by the number of slices.

In the period, the partial decoder A101 starts decoding the upper half screen while accessing the memory A501,
In addition, a reproduced image is output for displaying even-numbered fields.
During the period, the partial decoder A101 continues decoding the upper half screen, and the output reproduced image 200 is output by the partial decoder B102 while accessing the memory B502. In the period, since the lower half screen of the even-numbered field is not displayed, the reproduced image by decoding cannot be overwritten. Therefore, decoding by the partial decoder B102 is performed after the period. As in the case of FIG. 4, by the period, the partial decoder A101 performs decoding at a speed that leaves the lower eight slices or more in the memory A501, and the partial decoder B10
If the decoding is performed at a speed at which the decoding of the upper eight slices in the memory C 503 is completed, the contention of the memory B 502 for reading the predicted image data can be avoided. Even if the above-mentioned relationship of the decoding speed is not satisfied, for example, the partial decoder A 101
Even if the speed of decoding all the slices in the block 501 is the same as that in the memory B502 by the partial decoder B102,
The decoding completion time point a of ~ 44 slices is set to the partial decoder A101.
4, the possibility of contention in the memory B 502 is extremely reduced by setting the time before the completion of the decoding of the slice in the memory A 501 to the same as in the case of FIG.

As described above with reference to FIGS. 1 to 5, according to this embodiment, efficient parallel decoding with very little memory contention access is possible. Embodiment 2 Hereinafter, a second embodiment of the present invention will be described with reference to FIG. Although not shown, the configurations of the partial decoders A101 and B102 connected in parallel are the same as those in FIG.

The present embodiment provides an image decoding apparatus that performs another parallel processing on I and P frames that do not require overtaking control as described in the first embodiment.

FIG. 6 shows the timing of parallel decoding in a period of one frame in which overtaking control is unnecessary, and the state of memory access in each period.

In the period, the partial decoder A101 starts decoding while accessing the memory B502. Further, the partial decoder A101 reads the reproduced image data from the memory A501 and obtains an even field display output. The partial decoder B102 accesses the memory C503 and
Decoding is started from the ninth slice from the top of 03. By doing so, it is possible to avoid contention of the memory B502, and at the same time, two of the three memories can be separated and accessed for parallel decoding, and the other one can be separately accessed for reading the reproduced image data. it can.

In the period, the memory B 502 is accessed for reading the reproduced image data, the memory A 501 is accessed for decoding by the partial decoder A 101, and the memory C 503 is accessed for decoding by the partial decoder B 102.

Similarly, it can be seen that the access for reading the reproduced image data and the access for decoding can be separated in all periods. As described in the description of the conventional example,
By separating the above three accesses that require a high data transfer rate, the efficiency of parallel decoding is significantly improved. Embodiment 3 Hereinafter, a third embodiment of the present invention will be described with reference to FIG.

Although not shown, the configuration of the partial decoders A101 and B102 connected in parallel is the same as in FIG. This embodiment provides an image decoding apparatus by another parallel processing for the B2 frame requiring the overtaking control described in the first embodiment.

FIG. 7 shows the timing of parallel decoding in a period of one frame and the state of memory access in each period. Partial decoder A10
1 is the same as in FIG. In the present embodiment, the decoding performed by the partial decoder B102 is started without waiting for the display of the even field.
In order to prevent undisplayed data from being lost due to overwriting, a predetermined amount of memory area is separately provided only for the B frame. In FIG. 7, areas for storing the first 18 slices (accurately, even field data thereof, and therefore, 18/2 slices thereof) performed by the partial decoder B102 are secured in the memory B502 and the memory C503. By doing so, decoding can be performed prior to display without losing undisplayed data. Therefore, the decoding time for the lower half screen can be lengthened.

FIG. 8 shows another timing of parallel decoding in the third embodiment and a state of memory access in each period. In the example of FIG. 7, the processing speed required for decoding the lower half screen can be reduced, but the processing speed required for decoding the upper half screen is the same as that in FIG. In FIG. 8, the partial decoder B1 having a sufficient processing time is provided.
02 increases the number of slices to be decoded (to 38 slices), and conversely decreases the number of slices to be decoded by the partial decoder A101 (to 30 slices), thereby processing the partial decoder A101 and the partial decoder B102. Equalize the burden.

Further, by setting the switching target timing of the memory B 502 to the period, the required processing speed of the partial decoder A 101 can be reduced. (In FIG. 7, there is a possibility that memory contention will occur if 18 slices are not decoded during the period, but in FIG. 8, if 18 slices are decoded during period, no memory contention will occur.) 14 shows another parallel decoding timing of the embodiment. In this method, I and P frames that do not require overtaking control are decoded at the same timing as in FIG. Fig. 8
(The interval between the period in FIG. 8 and the memory B 502 is set as a target switching timing).
Therefore, both the partial decoder A101 and the partial decoder B102 decode the I and P frames in 34 slices.
For the B frame, the frame memory is allocated so that the partial decoder A101 decodes 30 slices and the partial decoder B102 decodes 38 slices. Embodiment 4 Hereinafter, a fourth embodiment of the present invention will be described with reference to FIGS.

Although not shown, the basic configuration of the partial decoders A101 and B102 connected in parallel is the same as in FIG.

FIG. 10 shows the timing of the decoding and the output of the output reproduced image in this embodiment. As in FIG.
The data of the input bit stream 100 is received in the order of P1, B1, B2, P2, B3 frames, and I, B1, B2
, P1, and B3 frames in this order.

In this embodiment, the decoding by the partial decoder A101 is started 1/4 frame earlier for each frame than the decoding by the partial decoder B102. Output playback image 20
0 is output in an interlace manner with respect to the I frame, with a delay of 1.5 frames from the start of decoding of the lower half screen by the partial decoder B102.

FIG. 10 also shows the access to the frame memory as in FIG. As can be seen from this, there is a period during which writing and reading to the B frame memory are performed simultaneously in B frame decoding, and decoding must be performed so that undisplayed data is not lost due to overwriting. Thus, a predetermined amount of another memory area is allocated only to the B frame in both the upper half screen and the lower half screen. By doing so, the decoding time of the partial decoder A101 and the partial decoder B102 can be assigned to all frames for one frame period, so that the efficiency of parallel processing is greatly improved.

FIG. 11 shows the timing of parallel decoding for one frame according to the present embodiment and the state of memory access in each period. When the upper half screen display of the decoded odd field ends, the partial decoder A101 starts decoding the currently focused frame from the uppermost slice. The partial decoder A101 is connected to the memory A5 for the period.
While accessing 01, the upper half screen is decoded. Furthermore,
Decoding is continued during the period. In the period, it is assumed that the upper half screen display of the decoded even field is performed, and as shown in FIG. 11, the display of the even field is overtaken when the decoding of 10 slices from the top is completed. Assuming this, the reproduction data of the even field of the upper 10 slices cannot be overwritten on the memory area storing the undisplayed even field data, so that another memory area must be allocated. If the decoding is continued so as not to overtake the display of the even-numbered fields for 11 slices or less, it is possible to overwrite the displayed memory area. The subsequent decoding by the partial decoder A101 and the decoding of the lower half screen by the partial decoder B102 are the same as the operations described in FIG.

Although not shown in FIG. 11, the period,
Then, the partial decoder B102 can decode the lower half screen of the previous frame (corresponding to the period in FIG. 11), and in the period, the partial decoder A101 can start decoding the upper half screen of the next frame. . Embodiment 5 Hereinafter, a fifth embodiment of the present invention will be described with reference to FIG.

Although not shown, the basic configuration of the partial decoders A101 and B102 connected in parallel is the same as in FIG.

In this embodiment, the order of decoding in the upper half screen by the partial decoder A101 in the fourth embodiment is changed. Reference numeral 101 denotes a point in time when the display of 24 slices (24 × 16 × 1/2 = 192 lines) of the decoded odd field is completed, in the middle of the upper half screen of the frame of interest (the 25th slice from the top). ) Is accessed by accessing the memory B502 to start decoding. Decoding of 10 slices in the memory B 502 is completed in the period, and decoding is continued by returning to the top slice of the upper half screen in the period. The decoding of the 24 slices in the memory A501 is completed by the subsequent period. In the case of decoding in this order, when the even-numbered fields of the 25 to 34 slices of the currently displayed frame are not displayed, the 25 to 34 slices of the current frame of interest are decoded. Writing cannot be performed, and another memory area needs to be allocated. Since decoding of the lower half screen is performed in the same manner as in the fourth embodiment, 25 to 44 are stored in the memory B 502 for decoding prior to display.
It is sufficient to secure a memory area for 1/2 of a slice (for even fields), that is, for 10 slices.

In this embodiment, as in the fourth embodiment, the decoding time of the partial decoder A 101 and the partial decoder B 102 can be assigned to all the frames for one frame period. Greatly improve. Embodiment 6 Hereinafter, a sixth embodiment of the present invention will be described with reference to FIG.

Although not shown, the basic configuration of the partial decoders A101 and B102 connected in parallel is the same as in FIG. 1, and the timing of decoding and output of the reproduced image is the same as in FIG. .

In this embodiment, the partial decoder A101 always accesses the memory A501 and the partial decoder B102 always accesses the memory C503, and decodes the image data stored in the memory B502. Also, it is possible to access the memory A 501 or the memory C 503 and read the bit stream. That is, as shown in the memory access of FIG. 13, writing of the data 40 to the buffer and reading of the data 41 are always performed by accessing the memory A501 and the memory C503.

In FIG. 13, memory A 501 to memory 50
3, the distribution of the image data to be stored is changed. That is, as shown in FIG. 13, by reducing the number of slices in the memory A 501 and the memory C 503 from the number of slices in the memory B 502, a large buffer area in the memory A 501 and the memory C 503 is secured. In this way, all the bit stream data necessary for decoding the upper half screen (34 slices) is stored in the memory A501, and the lower half screen (34 slices) is stored in the memory A501.
All the bit stream data necessary for decoding the slice) can be stored in the memory C503.
It goes without saying that, for a bit stream having a sufficient buffer capacity that can be secured in the memories A 501 and C 503, the same operation as described above can be realized even with the slice distribution as shown in FIG. 11 (without providing a buffer area in the memory B 502). No. In the present embodiment, the bit stream data of the upper and lower half screens are respectively allocated to one memory area, so that the buffer control becomes easy. Embodiment 7 Hereinafter, a seventh embodiment of the present invention will be described with reference to FIG.

The partial decoders A101 and B1 connected in parallel
02 is the same as that of FIG.

In this embodiment, the memories A501 to C503
The allocation of slices of image data stored in the storage device and the allocation of bit stream data are set differently.

An example of data to be stored in the memories A501 to C503 in FIG. 14 has been shown. That is, the memory A501
Stores the data of 1 to 24 slices of the image data, and the buffer area stores the header in the bit stream and the data of 1 to 16 slices. The memory B 502 stores 25 to 44 slices of the image data, and stores 1 bit in the bit stream in the buffer area.
Data regarding 7 to 52 slices is stored. Memory C
503 stores 45 to 68 slices of the image data, and the buffer area stores 53 to 68 slices in the bit stream.
Stores data about

The operation will be described below using the partial decoder A101 as an example.

The partial decoder A101 decodes 1 to 16 slices while accessing the memory A501.

Next, when decoding 17 to 24 slices, the bit stream is read from the memory B 502, the predicted image data is read from the memory A 501 or the memory B 502, and the reproduced image data is written into the memory A 501. 1
At the time of 7 to 24 slice decoding, the partial decoder A101 has obtained not only the memory A501 but also the memory B502 for predictive image data access, so that the bit stream can be read.

The advantages of this embodiment are as follows. That is,
The memory A501 and the memory C503 store image data for 24 slices, and the memory B502 stores image data for 20 slices. , The buffer area of the memory B502 is large. Memory B
By storing the stream data other than 25 to 44 slices in the buffer area 502, the buffer areas of each memory can be equalized. Embodiment 8 Hereinafter, an eighth embodiment of the present invention will be described with reference to FIG.

In the first to seventh embodiments except for the sixth embodiment, stream data for a predetermined slice in a bit stream is stored in each of the three memories. On the other hand, in the present embodiment, the header and the stream data of the upper half screen (1 to 34 slices) are stored in a buffer area of the memory A 501 and a part of the buffer area of the memory B 502, and the remaining buffer area of the memory B 502 is stored. And the stream data of the lower half screen (35 to 68 slices) are stored in the buffer area of the memory C503. A specific operation example will be described below for the header and the stream data of the upper half screen.

The input bit stream 100 is analyzed by the buffer control unit of the partial decoder A101,
First, data of 34 slices is stored in the buffer area of the memory A501. The header of the next frame and the data of the slices 1 to 34 are stored in the continuation of the buffer area of the memory A501. If the buffer area of the memory A 501 is full, the data is stored in the buffer area of the memory B 502. Since the memory B502 is used by being switched between the partial decoder A101 and the partial decoder B102, when the memory B502 is occupied by the partial decoder B102, the memory B502 is temporarily switched to the partial decoder A101 to write the stream data. May be performed, and since the same stream data is also input to the partial decoder B102, the partial decoder B102
May write stream data to the memory B502. In this way, the data is stored in a predetermined buffer area of the memory B502, and when the area is full, the flow returns to the buffer area of the memory A501. At the time of decoding, the partial decoder A101 is connected to the memory A501 or the memory B
The bit stream data is read from 502. Memory B
When the partial decoder B102 occupies 502,
It is necessary to temporarily switch to the partial decoder A101 and read out.

According to this embodiment, a memory conflict occurs at least at the time of reading the input bit stream 100,
You may have to switch memory. However, as described in the description of the related art, the data transfer rate of the input bit stream 100 to and from the memory is much lower than the data transfer rate of predicted image data, reproduced image data, and the like. Therefore, the switching of the memory hardly lowers the efficiency of the parallel decoding. Conversely, the buffer areas divided into the memories A501 and B502 and the memories B502 and C503 can be integrated, respectively, so that the buffer areas can be used effectively. Embodiment 9 Hereinafter, a ninth embodiment of the present invention will be described with reference to FIGS.
7 will be described.

Although not shown, the basic configuration of the partial decoders A101 and B102 connected in parallel is the same as in FIG.

The present embodiment is an example of parallel decoding of a progressive image (non-interlaced image).

FIG. 16 is a diagram showing the start of decoding for each frame of the input bit stream 100 and the timing of the output reproduced image 200.

At the same time, as indicated by the broken lines, each frame is displayed in order from the top line to the bottom line (output reproduced image in the figure). The decoding of each frame may be completed in a period between two broken lines in the drawing. Taking the decoding of the B2 frame as an example, after outputting the reproduced image of the B1 frame indicated by the broken line,
In addition, decoding is performed before outputting the reproduced image of the B2 frame indicated by the broken line. On the other hand, as shown in FIG. 16, when the output of the upper half of the reproduced image of the B1 frame is completed, the partial decoding of the upper half screen and the partial decoding of the lower half screen are started. Frame, a decoding time of one frame period can be secured.

FIG. 17 is a diagram showing the parallel decoding timing of an arbitrary frame. Upper half screen partial decoder A101
Starts decoding from the upper slice while accessing the memory A501, and decodes at a speed that leaves the lower eight slices of the image slices in the memory A501 during the period. During this time,
The lower half screen partial decoder B102 accesses the memory B502 and starts decoding from the center of the screen, and the memory C50.
The upper 8 slices or more in 3 are decoded. Thereby, the memory B5 is connected between the partial decoder A101 and the partial decoder B102.
02, there is no competition, and parallel decoding is possible. Similarly, no memory conflict occurs during the period. The partial decoder A10
As in the first embodiment, parallel decoding can be performed without significantly lowering the efficiency even when the relationship between 1 and the decoding speed of the partial decoder B102 is not satisfied. Embodiment 10 Hereinafter, a tenth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS.

FIG. 18 shows the configuration of this embodiment. Here, three partial decoders 101, 102, 1 of A, B, and C are used.
03 and four memories 501, 50 of A, B, C, D
2,503,504 are used. The memory A501 stores image data corresponding to a predetermined number of slices at the top of the screen, the memory B502 stores image data corresponding to a predetermined number of slices following the slice in the memory A501, and so on. And the memories C503 and D504 also store image data corresponding to a predetermined number of slices. Also, a buffer area is secured in each memory. With this configuration, the partial decoder A101 includes the memory A501 and the memory B5.
02, the partial decoder B102 is a memory B502, a memory C
503, the partial decoder C103 executes decoding while accessing the memory C503 and the memory D504.

FIG. 19 is a diagram showing how one frame is decoded. Here, the case where the decoding of the partial decoders 101, 102, and 103 of the partial decoders A, B, and C are started at the same time assuming that the overtaking control is not required is shown. The partial decoder A101 has a memory A5
The decoding starts from the first slice in 01, the partial decoder B102 starts decoding from the middle slice in the memory B502, and the partial decoder C103 starts decoding from the middle slice in the memory C503. Partial decoder C103
When decoding is performed, predicted image data can be read from the memory D504. Next, assuming that a point in time at which the slice in the memory C503 to be decoded by the partial decoder C103 is to be decoded is a, the partial decoder C103 decodes the slice in the memory D504 after a. In some cases, predicted image data can be read from the memory C503. Next, when decoding by the partial decoder B102 proceeds, the partial decoder B102 reads predicted image data from the memory C503 as necessary. Assuming that a point in time at which the slice in the memory B 502 to be decoded by the partial decoder B 102 is to be decoded is b, the partial decoder B 102 decodes the upper slice in the memory C after b. In some cases, the predicted image data can be read from the memory B502.
Similarly, a point in time at which the partial decoder A101 completes decoding the slice in the memory A501 is defined as c. At this time, if decoding is performed at the timing when a becomes earliest, then b and then c,
It is possible to prevent the partial decoders A to C 101 to 103 from decoding slices in the same memory.

As described above, in the present embodiment, efficient parallel decoding with very little memory contention by three partial decoders is possible.

Incidentally, if the embodiment shown in FIGS. 1 and 18 is generally displayed, the partial decoder is N
And the memory group uses N + 1, and the k-th partial decoder is configured to access the k-th memory group and the k + 1-th memory.

When this is applied to the first embodiment of FIG. 1, the number of partial decoders N = 2, the memory group N + 1 = 3, and the partial decoder A101 of k = 1 accesses the memory A501 and the memory B502. The second partial decoder B102 accesses the memory B502 and the memory C503. Also, when applied to the tenth embodiment in FIG. 18, the number of partial decoders N = 3 The memory group N + 1 = 4 The partial decoder A101 with k = 1 accesses the memory A501 and the memory B502 and the partial decoding with k + 1 = 2 The decoder B102 accesses the memory B502 and the memory C503. The partial decoder C103 of k + 2 = 3 accesses the memory C503 and the memory D504. Thus, general display can be performed using N and k.

[0101]

As described above in detail, according to the image decoding apparatus of the present invention, the k-th partial decoder has k partial decoders by having N partial decoders and N + 1 or more memory groups. It is possible to provide timing for simultaneously accessing both the memory group of the #th and the memory group of the (k + 1) th.
During this period, the prediction image data necessary for decoding of one memory group can be read from the other memory group, and highly efficient parallel decoding can be performed.

Further, since the plurality of partial decoders do not decode the image data in the same memory group, the contention of the memory caused by writing the plurality of reproduced image data to the same memory can be completely avoided. Since the image data is also usually in the vicinity of the image data to be decoded, memory contention due to reading of the predicted image data can be extremely reduced.
The efficiency is significantly improved.

When each partial decoder performs decoding from top to bottom in the picture, the completion of image decoding in the k-th memory group by the k-th partial decoder is determined by the (k-1) -th partial decoding. By setting the time point earlier than the completion of the image decoding in the (k-1) th memory group, it becomes easy to control the plurality of partial decoders so as not to decode the image data in the same memory group.

For frames that do not require overtaking control, the N partial decoders are simultaneously started to decode. When overtaking control is required, the decoding of the (k + 1) th decoder is started at the kth decoding start. To further delay, parallel decoding can be performed only in the frame memory area for three frames.

Further, since a memory area for writing reproduced image data for a frame requiring overtaking control is provided separately from the memory area for the three frames, decoding can be performed prior to output of a display image. , A margin of processing time can be obtained.

Further, since reading of predicted image data / writing of reproduced image data and reading of image data for display output are performed by accessing different memory groups, the data transfer efficiency between the decoding device and the memory is improved. be able to.

For decoding all frames,
In order to make the partial decoder that decodes the upper slice start decoding earlier than the partial decoder that decodes the lower slice, a decoding time for one frame can be secured in all of the N partial decoders. A margin of processing time is obtained.

Further, since the data for the slice in the bit stream for decoding the slice in each memory group is stored in the same memory group, even when the bit stream is read from the buffer, the memory between the partial decoders is used. Does not occur, and efficient parallel decoding becomes possible.

Further, since the header information is redundantly stored in at least N memory groups, the N partial decoders can individually read the header information when starting decoding.

When two partial decoders and three memory groups are used, all bit stream data is stored and decoded in the first and third memory groups, so that buffer control is facilitated. .

When two partial decoders and three memory groups are used, not only the bit stream data necessary for decoding the image data in the second memory group but also the In addition, since the bit stream data necessary for decoding the image data of up to eight slices above and below is stored, the amount of bit stream data to be stored in each memory group can be equalized.
As a whole, a margin of the buffer area can be secured.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing data transfer between a partial decoder and a memory in the first embodiment.

FIG. 3 is a timing chart of decoding and output of an output reproduced image in the first embodiment.

FIG. 4 is a diagram illustrating a first example of parallel decoding and memory access in the first embodiment.

FIG. 5 is a diagram illustrating a second example of parallel decoding and memory access in the first embodiment.

FIG. 6 is a diagram illustrating an example of parallel decoding and memory access in the second embodiment.

FIG. 7 is a diagram illustrating a first example of parallel decoding and memory access in the third embodiment.

FIG. 8 is a diagram illustrating a second example of parallel decoding and memory access according to the third embodiment.

FIG. 9 is a diagram illustrating a third example of parallel decoding in the third embodiment.

FIG. 10 is a timing chart of decoding and output of an output reproduced image in the fourth embodiment.

FIG. 11 is a diagram illustrating an example of parallel decoding and memory access in a fourth embodiment.

FIG. 12 is a diagram illustrating an example of parallel decoding and memory access in a fifth embodiment.

FIG. 13 is a diagram illustrating an example of parallel decoding and memory access in a sixth embodiment.

FIG. 14 is a schematic diagram illustrating data transfer between a partial decoder and a memory according to a seventh embodiment.

FIG. 15 is a schematic diagram showing data transfer between a partial decoder and a memory in the eighth embodiment.

FIG. 16 is a timing chart of decoding and output reproduced images in the ninth embodiment.

FIG. 17 is a diagram illustrating an example of parallel decoding in the ninth embodiment.

FIG. 18 is a basic configuration diagram of a tenth embodiment.

FIG. 19 is a diagram illustrating an example of parallel decoding in the tenth embodiment.

FIG. 20 is a general configuration diagram of an image decoding device.

FIG. 21 is a macroblock division diagram of an HDTV image.

FIG. 22 is a diagram showing a configuration example of a conventional technique.

[Explanation of symbols]

 Reference Signs List 10 decoder 11 buffer control unit 12 variable length decoder 13 scan converter 14 inverse quantizer 15 inverse DCT unit 16 motion compensation image reproducing unit 17 decoding processing unit 18 display control unit 40 buffer write data 41 buffer read data 42 prediction image Read data 43 Predicted image read data 44 Reproduced image write data 45 Reproduced image read data 50 Memory 51 Buffer memory 52 Frame memory 53 Frame memory 54 Frame memory 100 Bit stream input 101 Partial decoder A 102 Partial decoder B 103 Partial decoder C 200 Playback image output 501 Memory A 502 Memory B 503 Memory C 504 Memory D

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Ryuji Saito 4-36-19 Yoyogi, Shibuya-ku, Tokyo Inside Graphics Communication Laboratories Co., Ltd. (72) Inventor Yoshikazu Kawamura Shibuya-ku, Tokyo 4-36-19 Yoyogi Inside Graphics Communication Laboratories Co., Ltd. (72) Inventor Norihiko Nagai 4-36-19 Yoyogi Shibuya-ku, Tokyo Graphics Communication Co., Ltd. Within Laboratories (72) Inventor Tomoyuki Shindo 4-36-19 Yoyogi, Shibuya-ku, Tokyo Inside Graphics Communication Laboratories (72) Inventor Shigeru Komatsu 4-36-19 Yoyogi, Shibuya-ku, Tokyo No. Graphics Communication Co., Ltd.・ Laboratories (56) References JP-A-6-303590 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N ^7/ 24-7/68

Claims (11)

(57) [Claims] 1. An apparatus for predicting an image frame from a plurality of predicted frames and decoding encoded image data, comprising: N partial decoders; and at least N + 1 or more memory groups, wherein the image is divided. Then, the upper screen is allocated to the memory group with the smaller number and stored in N + 1 memory groups. The k-th partial decoder accesses the k-th memory group and the k + 1-th memory group. By
An image decoding apparatus by parallel processing, wherein an image divided and allocated is decoded in parallel. 2. The parallel processing according to claim 1, wherein no two of the N partial decoders decode images in the same memory group in parallel. Image decoding device. 3. The k-th partial decoder starts decoding a picture stored in a k-th memory group, and after completion of decoding of a predetermined picture in a k-th memory group, a k + 1-th partial decoder. The decoding is performed on the image stored in the memory group, and k−1
The first partial decoder starts decoding the image stored in the (k-1) th memory group, and after completion of decoding of the predetermined image in the (k-1) th memory group, The decoding of the predetermined image in the k-th memory group by the k-th partial decoder is performed by performing decoding on the image stored in the k-th partial decoder. 2. The image decoding apparatus according to claim 1, wherein the decoding is performed so that the decoding of the predetermined image in the memory group before the decoding is completed. 4. For a frame in which a memory area for storing reproduced image data decoded by the N partial decoders and a memory area for storing image data to be output for display are different, The decoding of N partial decoders is started at the same time, and the decoding of the (k + 1) th partial decoder is started after the decoding of the kth partial decoder starts for the frames having the same two memory areas. The image decoding apparatus according to claim 1, wherein decoding is performed. 5. A method according to claim 1, wherein the memory area for storing the reproduced image data decoded by the partial decoder and the memory area for storing the image data to be output for display are the same. 2. The image decoding by parallel processing according to claim 1, wherein a predetermined amount of memory area for storing image data is separately provided, and decoding is started without waiting for reading image data for display from the memory. apparatus. 6. The parallel decoder according to claim 1, wherein the N partial decoders access the N memory groups to perform decoding, and output image data for display from the remaining memory groups. Image decoding device by processing. 7. The image according to claim 1, wherein the decoding of the k-th partial decoder is started before the decoding of the (k + 1) -th partial decoder for all frames. Decoding device. 8. The method according to claim 1, wherein bit stream data for decoding the image data divided and stored in the (N + 1) memory groups is divided and stored in the same memory group as the image data. An image decoding device based on the parallel processing described above. 9. The image decoding apparatus according to claim 1, wherein all header information in the bit stream is stored in at least N memory groups. 10. The image decoding apparatus according to claim 1, further comprising two partial decoders, wherein the data of the entire bit stream is divided and stored only in the first and third memory groups. . 11. A second memory group which decodes image data stored in the second memory group and image data of up to 8 slices above and below the second memory group. 2. The image decoding apparatus according to claim 1, wherein data in a bit stream necessary for the decoding is stored.