JPH0870457A - Image decoding device by parallel processing - Google Patents

Abstract

PURPOSE: To improve efficiency by reducing the contention of a memory in an image decoding device with parallel configuration. CONSTITUTION: A partial decoder A101 reads header data in the memory A501, reads stream data as against slices 1-24 and prediction picture data and executes decoding in a decoding processing part. After decoding till the 24 slice, the memory B502 is accessed and 25-34 slices are decoded. Header data in the memory B502 is read by a prescribed timing, stream data as against the 34-44 slices is decoded and, then, 45-68 slices are decoded. Thus, a system is constituted in such a way that a parallel processing is enabled in the memories A501-C503 for the portion of three framed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding apparatus by parallel processing for decoding encoded image signals in parallel.

[0002]

2. Description of the Related Art When transmitting or storing digitally represented image data, encoding is performed to reduce the amount of data. As an encoding method, there is a method of reducing redundancy by utilizing temporal or spatial correlation of image information (image data).

As a method of utilizing the temporal correlation, there is a method of encoding a difference between two consecutive screens (frames) or detecting a motion of an image to perform motion compensation.
As a method of utilizing spatial correlation, an image is divided into blocks of a predetermined size (for example, 8 pixels in each of the vertical direction and the horizontal direction), the data in each block is orthogonally converted, and the conversion coefficient is scan-converted. However, there is one that performs variable length coding (for example, rearranges in order from low frequency components to high frequency components). An image coding method (hereinafter abbreviated as MPEG2), which is being standardized by the Moving Picture Experts Group (MPEG), uses the above two methods together.
The provisional recommendation for MPEG2 is "Generic Coding of Moving Pi
ISO / IE entitled "ctuers and Associated Audio"
It is described in C13818-2.

FIG. 20 shows an example of the structure of an image decoding apparatus for decoding data coded by such a method. 20, a buffer control unit 11 and a variable length decoder 1
2. Decoding processing is executed by the scan converter 13, the inverse quantizer 14, the inverse DCT unit 15, and the motion compensation image reproducing unit 16. Here, the portions 12 to 16 are grouped as the decoding processing unit 17. Reference numeral 18 is a display control unit. Further, hereinafter, 10 is called a decoder. Reference numeral 50 denotes a memory, which includes a buffer memory 51 and a frame memory (three I, P, and B frame memories described later) 52, 53, and 54. In addition, 100 indicates an input bit stream representing an encoded image, and 200 indicates an output reproduced image. Also,
The dotted line extending from the motion compensation image reproducing unit 16 indicates writing.

Next, the operation will be described. Under the control of the buffer control unit 11, the input bitstream 100 is stored in the buffer memory 5 as the buffer write data 40.
Accumulated in 1. The buffer read data 41 read from the buffer memory 51 is variable length decoded by the variable length decoder 12.

Although not all data is variable length coded, it is assumed that the fixed length code is also decoded by the variable length decoder 12. Next, the order of the data is rearranged by the scan converter 13 and then dequantized by the dequantizer 14. Next, the inverse DCT unit 15 performs inverse discrete cosine transform. The motion-compensated image reproduction unit 16 performs reproduction in consideration of the movement of the image. In MPEG2, a temporally intermediate frame (here, B frame) is predicted from both a temporally previous frame (here, I frame) and a temporally later frame (here, P frame). for that reason,
In order to reproduce the B frame, it is necessary to read out the predicted image read data 42 and 43 of the I frame and the P frame which have been decoded in advance from the frame memories 52 and 53 (MPE).
In G2, the temporally later P frame is decoded before the B frame). The B frame is reproduced by the motion compensation image reproducing unit 16 by the prediction image read data 42, 43 and the prediction error output from the inverse DCT unit 15, and is written in the frame memory 54 as reproduced image write data 44. The I, P, and B frames in the frame memories 52, 53, and 54 are read from each memory in a predetermined order (B frame data 45 is read in FIG. 20), and the output reproduced image 200 is output. In the following description, 40-4
5 may be simply referred to as data.

The present invention can be applied to an apparatus for processing all images of MPEG2, but for example, MPEG2
Consider the case of reproducing an HDTV image defined as the high level of. As shown in FIG. 21, one frame of an HDTV image is composed of 1920 horizontal pixels and 1080 vertical lines. This is divided horizontally and vertically into 16 pixels each. A unit of one division is called a macroblock (hereinafter abbreviated as MB).
HDTV image is 120MB in width, 68MB in height, 8 in total
It is divided into 160 MB.

One MB is composed of a luminance signal of 16 × 16 pixels (hereinafter abbreviated as Y) and two types of color signals of 8 × 8 pixels of blue and red (hereinafter abbreviated as Cb and Cr). . 16
The Y signal of x16 pixels is divided into four to form four blocks of 8x8 pixels. Therefore, the MB consists of 6 blocks of 8 × 8 pixels. If one pixel is represented by 8 bits, there are 3072 bits per MB. As shown in FIG. 21, there are 25067520 bits for 8160 MB per frame. As shown in FIG. 20, three frames have 75202560 bits, and when the buffer capacity of 9787392 bits defined by MPEG is added, the number of bits becomes 89413632 bits. This is a capacity of about 5.33 16 megabit memory elements, requiring 6 16 megabit memory elements.

Now, the decoder 10 and the memory 50 shown in FIG.
Estimate the data transfer rate between the two. The data 40 to be written in the buffer memory 51 has a maximum of 80 megabits / second according to the high level regulation of MPEG2. If the data 41 read from the buffer memory 51 has a maximum buffer capacity of 9787392 bits read in one frame, the maximum transfer rate is 9787392 bits / frame × 30 frames / second =
It is 293621760 bits / second. The predicted image read data 42 and 43, the written data 44, and the reproduced image read data 45 all have the same transfer rate assuming integer pixel frame prediction, and are as follows. 3072 bits / MB x 8160 MB / frame x 30
Frames / second = 752025600 bits / second The above sum is approximately 3400 megabits / second.
Therefore, if the data bus width between the decoder 10 and the memory 50 is 32 bits, the transfer speed is 100 MHz or more, and if the data bus width is 64 bits, the transfer speed is 50 MHz or more. Thus, very high speed data transfer is required.

Next, the operation speed of the decoding processing unit 17 is set to the inverse DC.
A trial calculation is made using the T section 15 as an example. The inverse DCT is executed in 8 × 8 pixel units, that is, in block units. Now, if the inverse DCT is performed by inputting data of 64 pixels one clock at a time, one block will have 64 clocks. Therefore, the operation clock is 8160 MB / frame × 6 blocks / MB × 64 clocks / block × 30 frames / sec = 94 MHz. As described above, HDTV decoding requires high-speed data transfer and high-speed calculation.

Parallel processing is a method for realizing high-speed processing. This is a method of dividing the process into a plurality of processes and relaxing the processing speed of each process. Parallel processing can be performed by utilizing the characteristics of the input bitstream 100 of MPEG2. As shown in FIG. 21, a group of horizontal one-row macroblocks is called a slice. Further, in the present invention, MB1 to MB120 are slice 1, MB12.
1 to MB240 are called like slice 2. MPE
In G2, one horizontal row of macroblocks can be further divided into a plurality of macroblock groups, and each macroblock is called a slice, but in the present invention, it is called as described above for convenience of explanation. In the case of FIG. 21, one frame is composed of 68 slices.

A feature of the MPEG2 input bitstream 100 is that each slice has a leading identifier. Therefore, it becomes possible to divide one frame into a plurality of slice groups and process each in parallel.

FIG. 22 shows an example of the configuration of such parallel processing. In this example, the screen is vertically divided into two. The partial decoder A processes the upper half screen, and the partial decoder B processes the lower half screen. As described above, six 16-megabit memory elements are used as the memory, and the data for the upper half screen is stored in the memory A and the data for the lower half screen is stored in the memory B. With this configuration, if the upper and lower screens are simultaneously decoded, the processing speed will be reduced.

[0014]

In MPEG, motion compensation prediction is performed. The maximum vertical motion compensation range is set to 8 slices in both the upper and lower directions. Therefore, the predicted image read data 4 for the MB to be decoded is
The reading of 2, 43 (FIG. 20) covers the range of the upper and lower 8 slices.

The parallel processing with the configuration shown in FIG. 22 has the following problems. 8 from the bottom of the upper half screen of P and B frames
Prediction image data in not only the memory A but also the memory B is required for decoding the slice range, and while the partial decoder A accesses the memory B, decoding of the lower half screen by the partial decoder B is stopped. It will be.

Similarly, not only the memory B is used for decoding the range of 8 slices from the top of the lower half screen of P and B frames,
The predicted image data in the memory A is needed, and the partial decoder B
While the memory A accesses the memory A, the decoding of the upper half screen by the partial decoder A is stopped.

As can be seen from the above-mentioned trial calculation of the memory data transfer rate, the reading of the predicted image read data 42 and 43 is larger than the writing of the data 40 to the buffer memory 51 and the reading 41 of the data 41. It has been found that the transfer is necessary, and that stopping the decoding due to long-term memory access contention reduces the efficiency of parallel processing.

Another problem of the parallel processing with the configuration of FIG. 22 is that the control of the memory becomes complicated. Although it has already been described that HDTV decoding requires six 16-megabit memory elements, the configuration of FIG.
It is used as memories A and B separately for each. When the data width of one memory element is 16 bits, the data width of three memory elements is 48 bits. Since 1 pixel data is represented by 8 bits, 48 bits are equivalent to 6 pixel data. However, the block that is the unit of decoding is 8 × 8 pixels,
It is not a multiple of 6. Therefore, the memory address cannot be divided for each block, and the memory control becomes complicated.

It is an object of the present invention to solve the problems in the image decoding apparatus having the parallel configuration as described above, and to provide the image decoding apparatus having the parallel configuration having less memory competition and therefore being efficient.

[0020]

An image decoding apparatus using parallel processing according to the present invention has N partial decoders and at least N + 1 memory groups, divides an image into slices, and divides the image into slices. The upper image is allocated to a small memory group and stored in N + 1 memory groups so that the kth partial decoder can access the kth memory group and the k + 1th memory group.

Further, of the N partial decoders, any two partial decoders perform decoding so that images in the same memory group are not decoded in parallel.

Further, the kth partial decoder accesses at least the kth memory group to start decoding, and after the image decoding in the kth memory group is completed, accesses the at least k + 1th memory group. Decrypt. The k−1 th partial decoder accesses at least the k−1 th memory group to start decoding, and after the image decoding in the k−1 th memory group is completed, accesses the at least k th memory group. The image decoding in the kth memory group by the kth partial decoder is completed earlier than the image decoding in the k-1th memory group by the k-1th partial decoder. Decrypt to.

Further, when the memory area for storing the reproduced image data being decoded and the memory area for storing the reproduced image data being displayed and output are the same, the data reading of the reproduced image data should be displayed. Must be controlled not to overtake (hereinafter referred to as overtaking control).
Therefore, for frames that do not require overtaking control, N partial decoders start decoding at the same time, and when overtaking control is required, start decoding of the k + 1th partial decoder from the kth partial decoding start. The decoding start timing of each partial decoder is controlled so as to be delayed.

Further, for decoding of a frame which originally requires overtaking control, a predetermined amount of memory area for writing reproduced image data is allocated, and preceding decoding can be performed without waiting for reading of image data for display. To

Further, the N partial decoders access the N memory groups to perform decoding, and control the decoding so that the image data for display output is read from the remaining memory groups.

For the decoding of all frames, the decoding start timing is controlled so that the decoding start by the kth partial decoder is earlier than the decoding start by the k + 1th partial decoder.

Further, the I, P, and B frame image data are divided and stored in N + 1 memory groups in units of slices, and bit stream data for decoding each slice is stored in the same memory group as each slice. Separate and store.

Further, for all N partial decoders, all the header information in the bit stream is stored in at least N memory groups.

When N = 2, all bit stream data are stored in the first memory group and the third memory group.

When N = 2, the second memory group has bits necessary for decoding the image data stored in the second memory group and the image data for the upper and lower eight slices. Store stream data.

[0031]

According to the present invention, for N partial decoders,
Since there are N + 1 or more memory groups, it becomes possible for the kth partial decoder to provide timing for accessing both the kth memory group and the k + 1th memory group.
During that timing, the predicted image data necessary for decoding the lower 8 slices of the kth memory group can be read from the k + 1th memory group, and is necessary for decoding the upper 8 slices of the k + 1th memory group. It is possible to read various predicted image data from the kth memory group. During this period, it is less likely that another partial decoder will access the kth memory and the k + 1th memory, so that the effect of parallel processing can be enhanced.

Further, since the plurality of partial decoders do not decode the slices in the same memory group, the memory contention due to the writing of the reproduced image data can be avoided, so that the efficient parallel decoding becomes possible.

Further, the completion of image decoding in the kth memory group by the kth partial decoder can be made earlier than the completion of image decoding in the k-1th memory group by the k-1th partial decoder. The operation is as follows. That is, after the k-th partial decoder has decoded the upper 8 slices of the k + 1-th memory group, the k-th partial decoder does not need to read the predicted image data from the k-th memory group.
The -1st partial decoder can read the predicted image data from the kth memory group.

For frames that do not require overtaking control (especially, I and P frames do not require overtaking control), all N partial decoders have a decoding time of one frame. Therefore, it is possible to obtain a margin of processing time.

Further, for decoding a frame requiring overtaking control, by allocating a memory area for writing reproduced image data, the decoding time can be lengthened, so that a processing time margin can be obtained. You can

Further, by reading the predicted image data / writing the reproduced image data and reading the image data for display output by accessing different memory groups, the data transfer efficiency between the decoding device and the memory can be improved. Can be improved.

In order to write the reproduced image data, the decoding start timing is set earlier for the partial decoders for decoding all the frames regardless of whether or not the overtaking control is necessary. Since the required memory area is small and the decoding time for one frame can be given to all the N partial decoders, a margin of processing time can be obtained.

Further, since the data of the bitstream for decoding the slices in each memory group is stored in one memory group, the memory of the memory between the partial decoders is also read in order to read the bitstream from the buffer. You can avoid conflicts.

Further, by overlapping the header information in at least N memory groups, the N partial decoders can individually read the header information when starting the decoding.

When N = 2, that is, when two partial decoders and three memory groups are used, the first partial decoder can always access the first memory group and the second partial decoder. The partial decoder of can always access the third memory group. Therefore, by storing all bitstream data in the first and third memory groups and decoding, that is, the bitstreams of the upper and lower half screens are respectively set to 1
By allocating to one memory area, control of the buffer becomes easy.

When N = 2, the image data (the number of slices) in the first and third memory groups are converted to the image data (the number of slices) in the second memory group as in the embodiment described later. It may be better to allocate more. At this time, the buffer areas in the first and third memory groups are reduced. In the second memory group, not only the bitstream data necessary for decoding the image data in the second memory group, but also the bitstream data necessary for decoding the image data of 8 slices above and below Can be stored to reduce the bitstream data to be stored in the first and third memory groups.

[0042]

【Example】

[Embodiment 1] Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
Will be described.

FIG. 1 is a basic configuration diagram of this embodiment. The internal configurations of the partial decoder A101 and the partial decoder B102 are basically the same as the decoder 10 of FIG. Note that FIG.
The same reference numerals denote the same parts. However, the buffer control unit (FIG. 2 described later) has a function of separating slice data, and the display control unit (FIG. 2 described later) uses the partial decoder A,
It has a function of switching the outputs of B 101 and 102. The memories A501 to C503 are two 16-megabit memory elements each having a data width of 16 bits. Therefore, the bit width of each memory group (hereinafter, simply referred to as a memory unless necessary) is 32 bits, and the partial decoder A,
Each of 101 and 102 of B has a memory data width of 64 bits (hereinafter, the partial decoders A and B are simply used except when necessary).
That).

FIG. 2 schematically shows the operation of this embodiment. The same input bitstream 100
Is input to the partial decoders A and B. Partial decoders A and B
The internal buffer control unit decodes the header and separates the slices.

In this embodiment, 1 to 24 are stored in the memory A 501.
It is supposed that the image data of slices, the image data of 25 to 44 slices in the memory B502, and the image data of 45 to 68 slices in the memory C503 are allocated (hereinafter, simply referred to as memories A to C unless necessary). Therefore, the header data and the data of 1 to 24 slices in the input bit stream 100 are stored in the buffer area of the memory A, the header data and the data of 25 to 44 slices are stored in the buffer area of the memory B, and the data of 45 to 68 slices are stored. Write to the buffer area of memory C. The header data is redundantly written in the memory A and the memory B so that the partial decoder A and the partial decoder B can respectively read the header data and start decoding. Since the memory A is always occupied by the partial decoder A, writing to the memory A is performed by the partial decoder A. Similarly, writing to the memory C is performed by the partial decoder B. However, since the memory B has a period acquired by the partial decoder A and a period acquired by the partial decoder B, writing to the memory B is performed by the partial decoder acquiring the memory B. Now, it is assumed that the partial decoder A writes the input bitstream 100 to the memory B.
At this time, the partial decoder B also has the same input bitstream 1
Since 00 is received, the amount of data written in the memory B by the partial decoder A can be analyzed, and the buffer storage amount can be known.

Next, the partial decoder A reads the header data in the memory A at a predetermined timing, and further 1 to 24
The stream data for the slice and, if necessary, the predicted image data are read out and decoded by the decoding processing unit. 24
When the decoding up to the slice is completed, the memory B is accessed and the decoding up to the slices 25 to 34 is performed. Similarly, the partial decoder B reads the header data in the memory B at a predetermined timing, further reads the stream data for 35 to 44 slices and, if necessary, the predicted image data, and the decoding processing unit performs decoding. After decoding up to 44 slices, the memory C is accessed to decode 45 to 68 slices.

The image data decoded as described above is
It is read from the top line. In the so-called progressive image, all the lines from the first line to the 1080th line are read in order, and in the interlaced image, for example,
First, read only the odd lines to get the odd fields,
Then only the even lines are read to get the even fields.
The reading of these data is performed by the partial decoder acquiring the memory storing the data to be read,
A continuous output reproduced image 200 is obtained by switching the outputs of the two partial decoders.

FIG. 3 shows the timing of decoding and output reproduced image 200. Here, I, P1, B1,
The data of the input bit stream 100 is received in the order of B2, P2, B3 frames, and I, B1, B2, P1, B3 are received.
The output reproduced image 200 is obtained in the order of frames. Furthermore, the output assumes interlacing. Also,
For the I frame, the reproduced image is output 1.5 frames after the start of decoding.

In the figure, the squares designated by I, P1, B1, etc. shown in the middle section indicate the frame memories 52, 53, 54 in FIG. The arrow pointing to the frame memory indicates that writing is performed, and the arrow exiting the frame memory indicates that reading is performed. When decoding I frame,
Only the decrypted reproduced image data is written. P
At the time of decoding one frame, the predicted image data is read from the I frame and the reproduced image data is written in the P1 frame memory. In the latter half of P1 decoding, the odd field of the I frame is also read. Decoding of each frame may be completed within one frame period. Similarly, when checking the access to the frame memory, when decoding the B frame,
It can be seen that writing and reading are performed on the same frame memory. Describing the decoding of the B2 frame, the B2 frame can be written in the area in the frame memory of the B frame where the output of the reproduced image of the B1 frame has finished, but the output of the reproduced image of the B1 frame does In the unfinished area, it is necessary to make the writing of the B2 frame wait. As a matter of course, it is necessary to complete the decoding and writing of the B2 frame before the output timing of the reproduced image of the B2 frame. In this case,
As described above, this is called a case where overtaking control is required.

Considering the above, for I frame and P frame, the partial decoder A for decoding the upper half screen and the partial decoder B for decoding the lower half screen are simultaneously started to be decoded,
Parallel decoding is possible by delaying the decoding start of partial decoder B, which decodes the lower half screen, from the decoding start of partial decoder A, which decodes the upper half screen, by 1/4 frame for B frames that require overtaking control. become. As described above, the present embodiment has the advantage that parallel decoding can be performed using only the frame memory for three frames.

FIG. 4 shows the state of parallel decoding timing for I-frames and P-frames (see FIG. 3) that do not require overtaking control, and the state of memory access during each period. During the period, the partial decoder A starts decoding the upper half screen while accessing the memory A, and outputs the reproduced image for displaying the even field. During this period, the partial decoder B starts decoding the lower half screen while accessing the memory B. During this time, the partial decoder B can also access the predicted image data stored in the memory C as needed. In the data transfer diagram shown in FIG. 4 corresponding to the periods 1 to 4, the broken line data 42 and 43 read from the memory C 503 by the partial decoder B 102 correspond to this. Further, the writing data 40 of the input bit stream 100 received in the period is the memory A 501 and the memory B 50.
2. Which of the memories C503 should be written is not defined, and therefore this is also indicated by a broken line.

The period is the same as the period except that the output reproduced image 200 is output from the memory B502 via the partial decoder B102.

In the period, the output reproduced image 200 is output from the memory C503 via the partial decoder B102. Further, the partial decoder B102 performs decoding while accessing the memory C503, and reads out the predicted image data 42 and 43 from the memory B502 as necessary. If the partial decoder A101 performs decoding at a rate that leaves the lower 8 slices or more in the memory A501 by the time period (the predicted image for motion compensation need not be read from the memory B502), the partial decoder B102 stores the memory. If the decoding is performed at a speed at which the decoding of the upper 8 slices or more in C503 is completed, the contention of the memory B502 for reading the predicted image can be avoided.
Even if the above-described decoding speed relationship is not satisfied, even if the partial decoder A101 is at a speed at which all the slices in the memory A501 are decoded by the period, there is a possibility that contention of the memory B502 will occur. Very few. Because the partial decoder A101 is the memory B502
The prediction image data in is needed when motion compensation is performed from the lower side (such as when an object moves upward).
On the contrary, the partial decoder B102 needs the predicted image data in the memory B502 when motion compensation is performed from the upper side (such as when the object moves downward) and the opposite directions in one frame. This is because it is unlikely that motion compensation from the same will be required at the same time.

In order to avoid contention, the decoding by the partial decoder A101 is performed by the lower part 8 in the memory A501 by the period.
It may be interrupted by leaving the slice, and the subsequent processes may be restarted in a period, or the decoding by the partial decoder A101 may be advanced as much as possible by the period and interrupted at the time when a conflict occurs, Furthermore, if contention occurs, memory B
502 may be temporarily switched to the partial decoder A101 to perform decoding without interruption.

In any case, by setting the decoding completion time point a of the 35 to 44 slices in the memory B502 by the partial decoder B102 to the decoding completion time point b of the slice in the memory A501 by the partial decoder A101, memory competition occurs. Can be reduced, so that efficient parallel decoding can be performed (see FIG. 2).

The period is similar to the period, but the memory B502 is mainly accessed by the partial decoder A101.

FIG. 5 shows the state of the parallel decoding timing for the B2 frame (see FIG. 3) which requires overtaking control,
The state of memory access in each period is shown. The storage states of the memories A501 to C503 are indicated by the number of slices, not the slice number.

In the period, the partial decoder A101 starts decoding the upper half screen while accessing the memory A501,
Also, the reproduced image is output for displaying the even field.
During the period, the partial decoder A101 continues to decode the upper half screen, and the output reproduced image 200 is output by the partial decoder B102 while accessing the memory B502. In the period, since the lower half screen of the even field is not displayed, the reproduced image by decoding cannot be overwritten. Therefore, the decoding by the partial decoder B102 is performed after the period. As in the case of FIG. 4, by the time period, the partial decoder A101 performs decoding at a speed that leaves the lower 8 slices or more in the memory A501, and the partial decoder B10
If the decoding is performed at the speed at which 2 finishes decoding the upper 8 slices or more in the memory C503, the contention of the memory B502 for reading the predicted image data can be avoided. Even if the above-described decoding speed relationship is not satisfied, for example, the partial decoder A101 may be used by the memory A by the time period.
Even if all the slices in 501 are to be decoded, the partial decoder B102 can store 35 slices in memory B502.
The partial decoding unit A101 indicates the decoding completion time point a of ~ 44 slices.
As in the case of FIG. 4, the possibility of contention of the memory B502 is extremely reduced by setting the time point before the decoding completion time b of the slice in the memory A501 by the above.

As described above with reference to FIGS. 1 to 5, according to the present embodiment, efficient parallel decoding with extremely few memory contention accesses is possible. [Second Embodiment] A second embodiment of the present invention will be described below with reference to FIG. Although not shown, the configurations of the partial decoders A101 and B102 connected in parallel are the same as those in FIG.

The present embodiment provides an image decoding apparatus by another parallel processing for I frames and P frames which do not require the overtaking control described in the first embodiment.

FIG. 6 shows the state of the parallel decoding timing in the period for one frame which does not require the overtaking control and the state of the memory access in each period.

In the period, the partial decoder A101 starts decoding while accessing the memory B502. Further, the partial decoder A101 reads the reproduced image data from the memory A501 and obtains an even field display output. The partial decoder B102 accesses the memory C503 and
Decoding is started from the ninth slice from the top of 03. By doing this, contention of the memory B502 can be avoided, and at the same time, two of the three memories can be separately accessed for parallel decoding, and the remaining one can be separately accessed for reading the reproduced image data. it can.

In the period, the memory B502 is accessed for reading the reproduced image data, the memory A501 is accessed by the partial decoder A101, and the memory C503 is accessed by the partial decoder B102.

Similarly, it can be seen that the access for reading the reproduced image data and the access for decoding can be separated in all periods. As mentioned in the explanation of the conventional example,
Separating the above three accesses, which require a high data transfer rate, significantly improves the efficiency of parallel decoding. [Third Embodiment] A third embodiment of the present invention will be described below with reference to FIG.

Although not shown, the configurations of the partial decoders A101 and B102 connected in parallel are the same as those in FIG. This embodiment provides an image decoding apparatus by another parallel processing for the B2 frame which requires the overtaking control described in the first embodiment.

FIG. 7 shows the state of the parallel decoding timing in the period of one frame and the state of the memory access in each period. Partial decoder A10
The decoding performed by 1 is the same as in FIG. In this embodiment, the decoding performed by the partial decoder B102 is started without waiting for the display of the even field.
In order to prevent undisplayed data from being lost by overwriting, a predetermined amount of memory area is separately provided only for the B frame. In FIG. 7, an area for storing the first 18 slices performed by the partial decoder B102 (correctly, even field data thereof, therefore 18/2 slices) is secured in the memory B502 and the memory C503. By doing so, it is possible to perform decoding prior to display without losing undisplayed data. Therefore, the decoding time for the lower half screen can be lengthened.

FIG. 8 shows another parallel decoding timing of the third embodiment and the memory access in each period. In the example of FIG. 7, the processing speed required for decoding the lower half screen can be relaxed, but the processing speed required for decoding the upper half screen is the same as in the case of FIG. In FIG. 8, the partial decoder B1 having a sufficient processing time
Processing of partial decoder A101 and partial decoder B102 is performed by increasing the number of slices decoded by 02 (making 38 slices) and decreasing the number of slices decoded by partial decoder A101 (making 30 slices). Equalize the burden of.

Further, by setting the switching target timing of the memory B502 between the period and the period, the required processing speed of the partial decoder A101 can be relaxed. (In FIG. 7, if 18 slices are not decoded for the period, memory conflict may occur, but in FIG. 8, if 18 slices are decoded for the period ,, memory conflict does not occur.) FIG. 9 shows another parallel decoding timing of the embodiment. In this method, I and P frames that do not require overtaking control are decoded at the same timing as in FIG. 4 (the period between the periods in FIG. 4 is set as the switching target timing of memory B502), and overtaking control is required. B2 frame in Figure 8
Decoding is performed at the same timing as the above (the period of FIG. 8 is set as the switching target timing of the memory B502).
Therefore, for the I and P frames, both the partial decoder A101 and the partial decoder B102 decode 34 slices each.
The B frame is allocated in the frame memory so that the partial decoder A101 decodes 30 slices and the partial decoder B102 decodes 38 slices. [Fourth Embodiment] A fourth embodiment of the present invention will be described below with reference to FIGS.

Although not shown, the basic configuration of the partial decoders A101 and B102 connected in parallel is the same as that of FIG.

FIG. 10 shows the timing of decoding and output of an output reproduced image in this embodiment. As in FIG. 3, I,
The data of the input bit stream 100 is received in the order of P1, B1, B2, P2, B3 frames, and I, B1, B2 are received.
, P1 and B3 frames are output in this order.

In the present embodiment, the decoding by the partial decoder A101 is started 1/4 frame earlier than the decoding by the partial decoder B102 for each frame. Output playback image 20
0 is output in interlace with respect to the I frame with a delay of 1.5 frames from the start of decoding of the lower half screen by the partial decoder B102.

Similar to FIG. 3, access to the frame memory is also shown in FIG. As can be seen from this, the B frame decoding has a period in which writing to and reading from the B frame memory are simultaneously performed, and it is necessary to perform decoding so that undisplayed data is not lost by overwriting. Therefore, a predetermined amount of another memory area is allocated only to the B frame in both the upper half screen and the lower half screen. By doing so, the decoding time of the partial decoder A101 and the partial decoder B102 can be allocated to all the frames for one frame period, so that the efficiency of parallel processing is greatly improved.

FIG. 11 shows a state of timing of parallel decoding for one frame and a state of memory access in each period according to this embodiment. The partial decoder A101 starts decoding the currently focused frame from the uppermost slice when the upper half screen display of the decoded odd field is finished. Depending on the period, the partial decoder A101 has a memory A5
While accessing 01, the upper half screen is decrypted. Furthermore,
Continue decryption even during the period. In the period, it is assumed that the upper half-screen display of the decoded even field is performed, and as shown in FIG. 11, the display of the even field is overtaken when the decoding for 10 slices from the top is completed. Assuming this, the reproduction data of the even field of the upper 10 slices cannot be overwritten in the memory area storing the undisplayed even field data, so that another memory area needs to be allocated. If the decoding is continued so that the display of even fields is not overtaken for 11 slices or less, the displayed memory area can be overwritten. The subsequent decoding by the partial decoder A101 and the decoding of the lower half screen by the partial decoder B102 are the same as the operation described in FIG.

Although not shown in FIG. 11, the period,
Then, the partial decoder B102 can decode the lower half screen of the previous frame (corresponding to the period of FIG. 11), and during the period, the partial decoder A101 can start decoding the upper half screen of the next frame. . [Fifth Embodiment] A fifth embodiment of the present invention will be described below with reference to FIG.

Although not shown, the basic configuration of the partial decoders A101 and B102 connected in parallel is the same as that of FIG.

In this embodiment, the decoding order in the upper half screen by the partial decoder A101 in the fourth embodiment is changed. Reference numeral 101 indicates the time when the display of 24 slices (24 × 16 × 1/2 = 192 lines) of the decoded odd field is completed, and halfway through the upper half screen of the frame of interest (the 25th slice from the top). ) To access the memory B502 and start decoding. Decoding of 10 slices in the memory B502 is completed in a period, and decoding is continued by returning to the uppermost slice of the upper half screen in a period. By the period thereafter, the decoding of 24 slices in the memory A501 is completed. In the case of decoding in this order, when the even field of 25 to 34 slices of the frame being displayed is not displayed, 25 to 34 slices of the frame currently being focused on are decoded, so that the same memory area is overwritten. It cannot be written and needs to allocate another memory area. Since the decoding of the lower half screen is performed in the same manner as in the fourth embodiment, 25 to 44 are stored in the memory B502 for the decoding preceding the display.
It suffices to secure a memory area corresponding to ½ of slices (for even fields), that is, for 10 slices.

Also in the present embodiment, as in the fourth embodiment, the decoding time of the partial decoder A101 and the partial decoder B102 can be assigned to one frame period for all frames, so that the efficiency of parallel processing is improved. Greatly improved. [Sixth Embodiment] A sixth embodiment of the present invention will be described below with reference to FIG.

Although not shown, the basic configuration of the partial decoders A101 and B102 connected in parallel is the same as that of FIG. 1, and the timing of decoding and reproduction image output is the same as that of FIG. .

In this embodiment, the partial decoder A101 can always access the memory A501, and the partial decoder B102 can always access the memory C503, so that the image data stored in the memory B502 can be decoded. Also, when it is necessary, the memory A 501 or the memory C 503 can be accessed to read the bitstream. That is, as shown in the memory access of FIG. 13, the writing of the data 40 to the buffer and the reading of the data 41 are always performed by accessing the memory A501 and the memory C503.

In FIG. 13, memories A 501 to 50
The distribution of the image data stored in 3 is changed. That is, as shown in FIG. 13, by reducing the number of slices in the memories A501 and C503 to be smaller than the number of slices in the memory B502, a large buffer area is secured in the memories A501 and C503. In this way, all bitstream data necessary for decoding the upper half screen (34 slices) is stored in the memory A 501 and the lower half screen (34 slices).
It becomes possible to store in the memory C503 all bitstream data necessary for decoding (slice).
It is needless to say that, for a bit stream having a sufficient buffer capacity that can be secured in the memory A501 and the memory C503, the slice distribution as shown in FIG. 11 (without providing the buffer area in the memory B502) can realize the same as above. Yes. In this embodiment, since the bit stream data of the upper and lower half screens are respectively allocated to one memory area, buffer control becomes easy. [Seventh Embodiment] A seventh embodiment of the present invention will be described below with reference to FIG.

Partial decoders A101 and B1 connected in parallel
The basic configuration of 02 is the same as that of FIG.

In this embodiment, the memories A501 to C503 are used.
The slice distribution of the image data stored therein is set to be different from the distribution of the bit stream data.

An example of data to be stored in the memories A501 to C503 of FIG. 14 is shown. That is, the memory A501
In the buffer area, 1 to 24 slices are stored, and in the buffer area, data related to the header and 1 to 16 slices in the bit stream is stored. 25 to 44 slices of the image data are stored in the memory B502, and 1 in the bitstream is stored in the buffer area.
Store data for 7-52 slices. Memory C
45 to 68 slices of the image data are stored in 503, and 53 to 68 in the bit stream are stored in the buffer area.
Store data about.

The operation will be described below by taking the partial decoder A101 as an example.

The partial decoder A101 decodes 1 to 16 slices while accessing the memory A501.

Next, when decoding 17 to 24 slices, the bit stream is read from the memory B502, the predicted image data is read from the memory A501 or the memory B502, and the reproduced image data is written in the memory A501. 1
At the time of 7 to 24 slice decoding, the partial decoder A101 has acquired not only the memory A501 but also the memory B502 for predictive image data access, so that the bit stream can be read.

The advantages of this embodiment are as follows. That is,
Image data for 24 slices is stored in the memory A 501 and memory C 503, and image data for 20 slices is stored in the memory B 502. Therefore, if the memory capacities are the same, compared to the memory A 501 and the memory C 503. , The buffer area of the memory B502 is large. Memory B
By storing stream data other than 25 to 44 slices in the buffer area 502, the buffer areas of the respective memories can be equalized. [Embodiment 8] Hereinafter, an eighth embodiment of the present invention will be described with reference to FIG.

In the first to seventh embodiments except the sixth embodiment, the stream data for a predetermined slice in the bit stream is stored in each of the three memories. On the other hand, in the present embodiment, the header and the stream data of the upper half screen (1 to 34 slices) are stored in the buffer area of the memory A 501 and a part of the buffer area of the memory B 502, and the rest of the buffer area of the memory B 502 is stored. The header and the stream data of the lower half screen (35 to 68 slices) are stored in the buffer area of the memory C503. A specific operation example will be described below with respect to the header and upper half screen stream data.

The input bit stream 100 is analyzed by the buffer control unit of the partial decoder A101, and the header and 1
The data of 34 slices is first stored in the buffer area of the memory A501. The header of the next frame and the data of slices 1 to 34 are stored in the continuation of the buffer area of the memory A501. When the buffer area of the memory A 501 is filled in this way, the buffer area of the memory B 502 is next stored. Since the memory B502 is used by being switched between the partial decoder A101 and the partial decoder B102, when the memory B502 is exclusively used by the partial decoder B102, it is temporarily switched to the partial decoder A101 to write the stream data. May be performed, or since the same stream data is input to the partial decoder B102, the partial decoder B102
Stream data may be written from the memory to the memory B502. In this way, the data is stored in the predetermined buffer area of the memory B502, and when the area is full, the buffer area of the memory A501 is restored. At the time of decoding, the partial decoder A101 uses the memory A501 or the memory B.
The bitstream data is read from 502. Memory B
If the partial decoder B102 occupies 502,
It is necessary to temporarily switch to the partial decoder A101 for reading.

According to the present embodiment, memory conflict occurs at least when reading the input bit stream 100,
You may have to switch memory. However, as described in the description of the related art, the data transfer rate of the input bit stream 100 with the memory is very low as compared with the data transfer rate of predicted image data, reproduced image data, and the like. Therefore, the above memory switching does not deteriorate the efficiency of parallel decoding. On the contrary, since the buffer areas divided into the memories A501 and B502 and the memories B502 and C503 can be respectively integrated, it is possible to effectively use the buffer areas. [Ninth Embodiment] A ninth embodiment of the present invention will now be described with reference to FIGS.
7 will be described.

Although not shown, the basic configuration of the partial decoders A101 and B102 connected in parallel is the same as that of FIG.

The present embodiment is an example of parallel decoding for a progressive image (non-interlaced image).

FIG. 16 is a diagram showing the timing of decoding start and output reproduced image 200 for each frame of the input bit stream 100.

At the same time, as indicated by broken lines, each frame is displayed in order from the top line to the bottom line (output reproduced image in the figure). The decoding of each frame may be completed in the period between the two broken lines in the figure. Taking B2 frame decoding as an example, after outputting the reproduced image of B1 frame shown by the broken line,
In addition, decoding is performed before outputting the reproduced image of the B2 frame shown by the broken line. On the other hand, as shown in FIG. 16, if the upper half screen partial decoding and the lower half screen partial decoding are started at the time when the output of the upper half surface of the reproduced image of the B1 frame is completed, both of them are all processed. It is possible to secure the decoding time for one frame period with the frame.

FIG. 17 is a diagram showing the parallel decoding timing of an arbitrary frame. Upper half screen partial decoder A101
Starts decoding from the upper slice while accessing the memory A501, and performs decoding at a rate of leaving the lower eight slices in the image slices in the memory A501 during the period. During this time,
The partial decoder B102 of the lower half screen accesses the memory B502 to start decoding from the central portion of the screen, and the memory C50
Decode the upper 8 slices or more in 3. This allows the memory B5 to be connected between the partial decoder A101 and the partial decoder B102.
Parallel decoding is possible without 02 competition. Similarly, no memory contention occurs during the period. The partial decoder A10
Similar to the first embodiment, even if the relationship between the decoding speed of 1 and the decoding speed of the partial decoder B102 is not satisfied, parallel decoding can be performed without significantly degrading the efficiency. [Embodiment 10] Hereinafter, a tenth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to 8 and 19.

FIG. 18 shows the configuration of this embodiment. Here, three partial decoders A, B, and C 101, 102, 1
03 and four memories A, B, C and D 501, 50
2, 503 and 504 are used. The memory A501 stores image data corresponding to a predetermined number of slices at the top of the screen, the memory B502 stores image data corresponding to a predetermined number of slices following the slice in the memory A501, and so on. Image data corresponding to a predetermined number of slices are also stored in the memories C503 and D504. Also, a buffer area is secured in each memory. With this configuration, the partial decoder A101 has the memory A501 and the memory B5.
02, partial decoder B102 is memory B502, memory C
503 and the partial decoder C103 execute decoding while accessing the memory C503 and the memory D504.

FIG. 19 is a diagram showing how one frame is decoded. Here, the case where the decoding of the partial decoders 101, 102, and 103 is started at the same time assuming that the overtaking control is not necessary is shown. The partial decoder A101 is a memory A5
Decoding starts from the first slice in 01, the partial decoder B102 starts decoding from an intermediate slice in the memory B502, and the partial decoder C103 starts decoding from an intermediate slice in the memory C503. Partial decoder C103
When decoding, the predicted image data can be read from the memory D504. Next, assuming that the time when the slice in the memory C503 to be decoded by the partial decoder C103 is completed is a, the partial decoder C103 decodes the slice in the memory D504 after a. In some cases, the predicted image data can be read from the memory C503. Next, when the decoding by the partial decoder B102 proceeds, the partial decoder B102 reads the predicted image data from the memory C503 as necessary. Assuming that the time when the slice in the memory B502 to be decoded by the partial decoder B102 is completed is b, the partial decoder B102 decodes the upper slice in the memory C after b. In some cases, the predicted image data can be read from the memory B502.
Similarly, the time when the partial decoder A101 completes decoding the slice in the memory A501 is c. At this time, if decoding is performed at the timing when a is the earliest, then b, and then c,
It is possible to prevent the partial decoders A to C 101 to 103 from decoding slices in the same memory.

As described above, according to the present embodiment, efficient parallel decoding with extremely little memory contention by the three partial decoders is possible.

If the embodiments shown in FIGS. 1 and 18 are generally displayed, the partial decoder is N
, N + 1 memory groups are used, and the k-th partial decoder accesses the k-th memory group and the k + 1-th memory.

When this is applied to the first embodiment of FIG. 1, the number of partial decoders N = 2 memory group N + 1 = 3 partial decoder A101 of k = 1 accesses memory A501 and memory B502 k + 1 = The second partial decoder B102 accesses the memory B502 and the memory C503. When applied to the tenth embodiment of FIG. 18, the number of partial decoders N = 3 memory group N + 1 = 4 partial decoder A101 with k = 1 accesses memory A501 and memory B502 partial decoding with k + 1 = 2 The device B102 accesses the memory B502 and the memory C503. The partial decoder C103 of k + 2 = 3 accesses the memory C503 and the memory D504. In this way, general display can be performed using N and k.

[0101]

As described above in detail, according to the image decoding apparatus of the present invention, the k-th partial decoder has k partial decoders by having N partial decoders and N + 1 or more memory groups. It is possible to provide a timing for simultaneously accessing both the th memory group and the (k + 1) th memory group.
During this period, the predicted image data required for decoding of one memory group can be read from the other memory group, and highly efficient parallel decoding becomes possible.

Further, since the plurality of partial decoders do not decode the image data in the same memory group, the memory contention caused by writing the plurality of reproduced image data in the same memory can be completely avoided, and further prediction is possible. Since the image data is usually in the vicinity of the image data to be decoded, the contention of the memory due to the reading of the predicted image data can be extremely reduced,
The efficiency is significantly improved.

When each partial decoder decodes from the top to the bottom in the screen, the completion of image decoding in the kth memory group by the kth partial decoder is determined by the k-1th partial decoding. By setting the time point earlier than the completion of the image decoding in the (k-1) th memory group, it becomes easy to control so that the plurality of partial decoders do not decode the image data in the same memory group.

For frames that do not require overtaking control, N partial decoders start decoding at the same time, and when overtaking control is required, start decoding by the k + 1th decoder and start kth decoding. In order to further delay, parallel decoding is possible only in the frame memory area for 3 frames.

Further, since the memory area for writing the reproduced image data for the frame requiring the overtaking control is provided separately from the memory area for the above three frames, the decoding can be performed prior to the output of the display image. Therefore, the processing time can be afforded.

Further, since reading of predicted image data / writing of reproduced image data and reading of image data for display output are executed by accessing different memory groups, the data transfer efficiency between the decoding device and the memory is improved. be able to.

For decoding all frames,
Since the partial decoder that decodes the upper slice starts decoding earlier than the partial decoder that decodes the lower slice, the decoding time for one frame can be secured for all N partial decoders. A processing time margin can be obtained.

Further, since the data for the slice in the bitstream for decoding the slice in each memory group is stored in the same memory group, even when the bitstream is read out from the buffer, the memory between the partial decoders is large. , And efficient parallel decoding becomes possible.

Since the header information is redundantly stored in at least N memory groups, the N partial decoders can individually read the header information when starting decoding.

When two partial decoders and three memory groups are used, all bitstream data is stored in the first and third memory groups and decoded, so that control of the buffer becomes easy. .

When two partial decoders and three memory groups are used, not only the bit stream data necessary for decoding the image data in the second memory group are stored in the second memory group. In addition, since the bit stream data necessary for decoding the image data for up to 8 slices at the bottom is stored, the amount of bit stream data to be stored in each memory group can be equalized.
The buffer area can be secured as a whole.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing data transfer between a partial decoder and a memory in the first embodiment.

FIG. 3 is a timing chart of decoding and output of an output reproduced image in the first embodiment.

FIG. 4 is a diagram showing a first example of parallel decoding and memory access in the first embodiment.

FIG. 5 is a diagram showing a second example of parallel decoding and memory access in the first embodiment.

FIG. 6 is a diagram showing an example of parallel decoding and memory access in the second embodiment.

FIG. 7 is a diagram showing a first example of parallel decoding and memory access in the third embodiment.

FIG. 8 is a diagram showing a second example of parallel decoding and memory access in the third embodiment.

FIG. 9 is a diagram illustrating a third example of parallel decoding according to the third embodiment.

FIG. 10 is a timing diagram of decoding and output of an output reproduced image according to the fourth embodiment.

FIG. 11 is a diagram showing an example of parallel decoding and memory access in the fourth embodiment.

FIG. 12 is a diagram showing an example of parallel decoding and memory access in the fifth embodiment.

FIG. 13 is a diagram showing an example of parallel decoding and memory access in the sixth embodiment.

FIG. 14 is a schematic diagram showing data transfer between a partial decoder and a memory in the seventh embodiment.

FIG. 15 is a schematic diagram showing data transfer between a partial decoder and a memory in the eighth embodiment.

FIG. 16 is a timing diagram of decoding and output reproduced image in the ninth embodiment.

FIG. 17 is a diagram showing an example of parallel decoding in the ninth embodiment.

FIG. 18 is a basic configuration diagram of a tenth embodiment.

FIG. 19 is a diagram showing an example of parallel decoding in the tenth embodiment.

FIG. 20 is a general configuration diagram of an image decoding device.

FIG. 21 is a macroblock division diagram of an HDTV image.

FIG. 22 is a diagram showing a configuration example of a conventional technique.

[Explanation of symbols]

 10 Decoder 11 Buffer Control Unit 12 Variable Length Decoder 13 Scan Converter 14 Inverse Quantizer 15 Inverse DCT Unit 16 Motion Compensated Image Reproduction Unit 17 Decoding Processing Unit 18 Display Control Unit 40 Buffer Write Data 41 Buffer Read Data 42 Prediction Image Read data 43 Predicted image read data 44 Reproduced image write data 45 Reproduced image read data 50 Memory 51 Buffer memory 52 Frame memory 53 Frame memory 54 Frame memory 100 Bit stream input 101 Partial decoder A 102 Partial decoder B 103 Partial decoder C 200 Reproduced image output 501 Memory A 502 Memory B 503 Memory C 504 Memory D

Front Page Continuation (72) Inventor Ryuji Nishito 4-36-19 Yoyogi, Shibuya-ku, Tokyo Within Graphics Communication Laboratories, Inc. (72) Inventor Kaiku Kawamura 4-36-19 Yoyogi, Shibuya-ku, Tokyo No. Incorporated Graphics Communications Laboratories (72) Inventor Norihiko Nagai 4-36-19 Yoyogi, Shibuya-ku, Tokyo Incorporated Graphics Communications Laboratories (72) Inventor Tomoyuki Shindo Shibuya, Tokyo 4-36-19, Yoyogi-ku, within Graphics Communications Laboratories, Inc. (72) Inventor Shigeru Komatsu 4-36-19, Yoyogi, Shibuya-ku, Tokyo Within Graphics Communications Laboratories, Inc.

Claims (11)

[Claims] 1. An apparatus for predicting an image frame from a plurality of prediction frames and decoding encoded image data, comprising N partial decoders and at least N + 1 or more memory groups, and dividing an image. Then, it is divided into N + 1 memory groups so that the upper screen is allocated to the memory group with a smaller number, and the k-th partial decoder accesses the k-th memory group and the k + 1-th memory group. Due to
An image decoding apparatus using parallel processing, characterized in that the divided and allocated images are decoded in parallel. 2. The parallel processing according to claim 1, wherein none of the N partial decoders decodes the images in the same memory group in parallel. Image decoding device. 3. The kth partial decoder starts decoding for the image stored in the kth memory group, and after the decoding of a predetermined image in the kth memory group is completed, The image stored in the memory group is decoded, and k-1
The th partial decoder starts decoding for the image stored in the k−1th memory group, and after decoding of a predetermined image in the k−1th memory group, completes the kth memory group. The image stored in the sub-decoder is decoded, and the decoding of the predetermined image in the k-th memory group by the k-th partial decoder is completed by k-1 by the k-1 -th partial decoder. The image decoding apparatus by parallel processing according to claim 1, wherein the decoding is performed so as to be before the completion of decoding of the predetermined image in the th memory group. 4. A frame in which a memory area for storing reproduced image data decoded by N partial decoders and a memory area for storing image data to be output for display are different from each other, Start decoding of N partial decoders at the same time so that, for a frame in which the two memory areas are the same, the decoding start of the k + 1th partial decoder is after the decoding start of the kth partial decoder. The image decoding apparatus according to claim 1, wherein the image decoding apparatus performs decoding. 5. The reproduced image data for a frame in which the memory area for storing the reproduced image data decoded by the partial decoder and the memory area for storing the image data to be output for display are the same. 2. The image decoding by parallel processing according to claim 1, wherein a predetermined amount of memory area for storing the image data is separately provided, and the decoding is started without waiting for reading the image data for display from the memory. apparatus. 6. The parallel according to claim 1, wherein N partial decoders access the N memory groups to perform decoding, and output image data for display from the remaining memory groups. Image decoding device by processing. 7. The image by parallel processing according to claim 1, wherein, for decoding of all frames, the decoding start by the k-th partial decoder is before the decoding start by the k + 1-th partial decoder. Decoding device. 8. The data of a bit stream for decoding image data divided and stored in N + 1 memory groups is divided and stored in the same memory group as the image data. An image decoding device by the parallel processing described. 9. The image decoding apparatus according to claim 1, wherein all the header information in the bitstream is stored in at least N memory groups. 10. The image decoding apparatus by parallel processing according to claim 1, further comprising two partial decoders, wherein the data of all bit streams are divided and stored only in the first and third memory groups. . 11. The second memory group has two partial decoders, and the second memory group decodes image data stored in the second memory group and image data for upper and lower maximum eight slices. The image decoding apparatus by parallel processing according to claim 1, characterized in that data in a bit stream necessary for performing the processing is stored.