JPS60251763A - Magnifying and reducing circuit of facsimile information - Google Patents

Abstract

PURPOSE:To improve a converting speed by decoding facsimile information subject to run length coding, and outputting a run length data in parallel to use a parallel data thereby magnifying the pattern. CONSTITUTION:A run length decoding circuit 101 extracts facimile information 10 from a storage device 1 and outputs a run length data 202 in parallel. The data 202 is added with a numeral value stored in the 1st register 103 at an adder circuit 102 and stored again in the register 103. Thus, an accumulated value of the picture element number is stored in the register 103. A prescribed magnification factor is multiplied with the accumulated value outputted from the register 103 by a mapping circuit 104. The output of the circuit 104 is stored in the 2nd register 105 and a subtraction circuit 106 outputs a value representing the said run length by subtracting the run length sum up to the preceding value stored in the register 105. The magnified binary run length data 207 is inputted to a run length coding circuit 107, where it is subject to run length coding and magnified facsimile information 16 is transmitted to the storage device 1 together with a write clock 17.

Description

TECHNICAL FIELD The present invention relates to a facsimile information enlargement/reduction circuit for enlarging or reducing the screen size of run-length encoded facsimile information.

A conventional run-length line stores 1'' of converted facsimile information and converts the screen size as an additional service when performing a store-and-forward service. For example, A
The facsimile information of the 4th version is converted into the facsimile information of the B4 version. The number of pixels in one scanning line is 1728 for A4 size and 2048 for B4 size, so
In this case, the run length will be converted to 0:, which is expanded by 20413/1728 times. However, since the run-length code encodes only the integer 1, the fractions below the decimal point must be complemented by some method.

The first IN is a block diagram showing an example of a conventional facsimile information enlargement/reduction circuit. That is, the run-length decoding circuit 2 reads the run-length encoded facsimile information 10 from the storage device 1 using the read clock 11.
and decipher the run length for each black or white,
It is converted into a normal binary facsimile signal 12 having the number of pixels corresponding to the run length and inputted into the memory 3. memory 3
has a capacity for two scanning lines, and performs writing and reading alternately by switching the switch 5. reads out the binary facsimile signal 13 from the memory 3 and converts it into a binary facsimile signal whose size has been converted.For example, when converting the size from A41i to 84 edition, the number of missing pixels (2048-1728=
320 pixels) are allocated and inserted at equal intervals in one scanning line,
The screen is enlarged by setting the signal of each inserted pixel to the same value as the previous pixel. The run length encoding circuit 7 inputs the enlarged and converted binary facsimile signal 14 output from the size conversion circuit 6, counts the number of pixels for each black and white, calculates the run length, and corresponds to the run length. Convert to the code. The run-length encoded facsimile information 1B is sent to the storage device 1 together with the write clock 17 and is stored therein.

In order to convert the screen size, the conventional circuit described above first decodes run-length encoded facsimile information and converts it into a normal binary serial facsimile signal string, and then calculates the number of bits per line of the facsimile signal. After converting the size by increasing or decreasing the size, run-length encoding is performed again, so the conversion speed is slow. Run-length encoding takes advantage of the statistical properties of facsimile signals.
It suppresses redundancy, and is usually compressed to about 175 to 1/10 of a binary facsimile signal string. Therefore, the second facsimile signal 12 output from the run-length decoding circuit 2 has data five to ten times larger than the facsimile information 10. 2 input to the run length encoding circuit 7
The same applies to the value far-facsimile signal 14. When transmitting size-converted facsimile information using a device that stores and exchanges a large amount of information, the processing capacity of the conversion circuit has a significant impact on economic efficiency and serviceability. Most of the processing is consumed for serial conversion of pixel signals and their reorganization, which slows down the transfer speed and degrades serviceability.

Purpose of invention [1] The present invention solves the above-mentioned conventional drawbacks.

An object of the present invention is to provide a facsimile information enlargement/reduction circuit capable of high-speed processing of size conversion of facsimile information.

Structure of the Invention The facsimile information scaling circuit of the present invention includes a run-length decoding circuit that inputs run-length encoded facsimile information and decodes it into binary run-length data, and a run-length decoding circuit that accumulates output values of the run-length decoding circuit. a mapping circuit that multiplies the output value of the first register by a predetermined coefficient; a second register that holds the output of the mapping circuit; The present invention is characterized in that it includes a subtraction circuit that subtracts the value held in the register, and a run-length encoding circuit that converts the output of the subtraction circuit into a run-length code.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.

That is, the run-length decoding circuit 101 reads the facsimile information 10 from the storage device l using the read clock 11.
is extracted, decoded, converted into a multi-bit binary value representing a run length for each black or white, and outputted in parallel as binary run length data 202. The binary run length data 202 is.

In the adder circuit 102, the binary value stored in the first register 103 is added to the first register 103.
The binary value held in the first register 103 is updated. Therefore, the output 203 of the adder circuit 102
indicates the sum of the binary run lengths successively restored from the starting point of the l line, that is, the absolute coordinate value, and the first register 103 contains the cumulative value (absolute coordinate values) will be stored. The absolute coordinate value 204 output from the first register 103 is multiplied by a predetermined expansion coefficient in the mapping circuit 104 . for example,
When enlarging an A4 size to an 84th size, the expansion coefficient is 2048/1728. The mapping circuit +04 is
It can also be configured with a multiplier or a read-only memory that uses the cumulative output 204 as an address input and stores a value multiplied by an expansion coefficient. Further, the fraction under the decimal point of the multiplication result is, for example, a whole number rounded to the nearest 5.

The output of the mapping circuit 104 is held in the second register 105, and the subtracting circuit In receives the output 2 of the mapping circuit 104.
By subtracting the previous run length total value held in the second register 105 from 05, a value indicating the run length is output. The enlarged binary run length data 207 output from the subtraction circuit 10fi is input to the run length encoding circuit 107, and the run length encoding circuit 107 encodes the input data into a run length to generate an enlarged and converted facsimile. The information 16 is sent together with the write clock 17 to the storage device l.

In this embodiment, the run length decoding circuit 101 is
Decode the Lanrenge encoded facsimile information,
Multiple-bit run length data indicating the run length of each piece is output in parallel, and subsequent conversion for screen enlargement and the like can be processed at high speed using the parallel data. Therefore, the time required for screen size conversion processing can be sufficiently reduced compared to the data transfer speed between the storage device 1 and the run-length decoding circuit 101 or the run-length saving circuit 107. Note that it is obvious that by changing the coefficients of the mapping circuit 104, the magnification ratio or reduction conversion can be easily performed.

Effects of the Invention As described above, in the present invention, run-length encoded facsimile information is
The absolute value of the coordinate is determined by accumulating the value of the binary run length f-1, and from the enlarged coordinate value obtained by multiplying the current coordinate value by a predetermined enlargement coefficient, the immediately preceding The system is configured to take the enlarged run length by the value obtained by subtracting the enlarged coordinate value, and convert the enlarged run length into run length encoded facsimile information and output it. Conversion processing can be quickly performed using parallel data, and a high-speed facsimile information scaling circuit can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional facsimile information enlargement/reduction circuit, and FIG. 2 is a block diagram showing an embodiment of the present invention.・(, 3. Memory ・ 5゛ switch ・ 6. Sci-facsimile information, 11: Read clock, +2.13: Binary facsimile signal, 14: Expanded binary facsimile signal string, 15: Read clock, 16: Facsimile information, 17: write clock, 101: run length decoding circuit, 102: addition circuit, 103: first register, 1
04: Mapping circuit, 105: Second register, 106 Two-subtraction circuit, 107: Run length encoding circuit. Applicant NEC Corporation Agent Patent Attorney Toshimune ITJ

Claims (1)

[Claims] a run-length decoding circuit for inputting facsimile information converted into run-length code j+ and decoding it into binary run-length data; a first register for accumulating 111 output values of the run-length decoding circuit; a Kenni image circuit that multiplies the output value of the register by a predetermined coefficient; a second register that holds the output of the mapping circuit; 1. A circuit for enlarging/reducing facsimile information, comprising: a subtraction IC circuit for subtracting a value obtained by subtraction; and a run-length encoding circuit for converting the output of the subtraction circuit into a run-length code.