KR0180163B1 - An inverse scanner in an image decoder - Google Patents

Abstract

The present invention relates to an inverse scan device of an image decoder, comprising: an address generator (31); An address decoder 33 for decoding the output address of the address generator 31 and enabling the output of the corresponding register; A plurality of shift registers 34-1 to 34-6 which receive the scanned image data, shift the input data every clock, and enable the output according to the output of the address decoder 33; And an output register 35 that buffers the output of the shift register and outputs reversely scanned image data, thereby restoring to a DCT block before scanning, thereby reducing the number of memories required and reducing manufacturing costs and delaying for reverse scanning. There is an effect that can reduce the time it takes.

Description

Reverse scan device of video decoder

1 is a block diagram showing a general video decoder.

2 is a block diagram showing a conventional reverse scan device.

3 is a block diagram showing a reverse scan device according to the present invention.

4 is an operation timing diagram of the reverse scanning apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

1: Variable length decoder 2: Run-length decoder

3: reverse scanning unit 4: inverse quantization unit

5: inverse discrete cosine conversion unit 12: first RAM

14: second RAM 16, 31: address generator

32: shift register set 33: address decoder

34-1 to 34-6: Register 35: Output register

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal decoding technique, and more particularly, to an inverse scanning apparatus of an image decoder for inversely scanning an image data scanned in an image signal encoding process and restoring an original block.

In general, when processing video signals digitally, a large amount of memory is required, so compression of video data is a major concern in storing, retrieving, and transmitting video information. MPEG-1, 2, etc. have been proposed and widely used. As shown in FIG. 1, a video decoder is a variable that receives a bit stream encoded by a predetermined Huffman table and outputs it at run and level. A chapter decoder 1; A run-length decoder (2) which receives the run and level values of the variable length decoder (1) and decodes them into predetermined bit values; An inverse scan unit (3) which receives the output of the run-length decoder (2) and performs the inverse scan; An inverse quantization unit (4) for receiving the inversely scanned data and inversely quantizing the inversely scanned data; The inverse discrete cosine transform unit 5 receives the output of the inverse quantization unit 4 to inverse discrete cosine transform and receives the received image data and outputs decoded image data.

In this case, the transmitting side encoding the image data scans and transmits the quantized 8x8 DCT coefficient block in order to increase the compression efficiency. Therefore, the receiving side must reverse scan to restore the original block. As described above, the conventional inverse scanning apparatus for reverse scanning in the decoder stores the image data in the RAM 12 and 14 in units of blocks as shown in FIG. 2, and then generates the generated blocks in the address generator 16 for the stored blocks. Memory for storing at least two blocks was needed because addressed in reverse scan order according to address and outputted back-scanned data. Control circuit is complicated because read and write are alternately read and written to the two memories. There is a problem in that 1 block is delayed.

That is, the conventional reverse scan device alternately stores the scanned data in block units according to the write address input from the address generator 16, and alternately reads the pair of RAMs 12 which read the stored data according to the read address. , 14); An address generator 16 for generating the write address and the read address, and when writing the scanned data to the first RAM 12, the reverse scanned data is read from the second RAM 14, and the second When writing the scanned data to the RAM 14, the block data already stored from the first RAM 12 is read in the reverse scanning order.

Accordingly, an object of the present invention is to provide an inverse scan apparatus of an image decoder for outputting data descanned in units of blocks using one shift register group.

In order to achieve the above object, an apparatus of the present invention is an inverse scan apparatus of an image decoder which receives an image data scanned during an image encoding process and performs a reverse scan in a predetermined order, wherein the address for the predetermined reverse scan order is used. An address generator for generating a; And a shift register group that receives and stores the scanned image data, shifts them by a clock, and outputs reversely scanned image data in a selected order according to the output address of the address generator.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

The reverse scan device according to the present invention includes an address generator 31 for generating an address for a predetermined reverse scan order as shown in FIG. The shift register group 32 receives and stores scanned image data, shifts it by a clock, and outputs reverse scanned image data in a selected order according to the output address of the address generator 31.

In addition, the shift register group 32 includes an address decoder 33 for decoding the output address of the address generator 31 and enabling the output of a corresponding register; A plurality of shift registers 34-1 to 34-6 which receive the scanned image data, shift the input data every clock, and enable the output according to the output of the address decoder 33; And an output register 35 that buffers the output of the shift register and outputs reversely scanned image data.

In addition, in the embodiment of the present invention, the shift registers are implemented as 55 from R55 to R1, and after the inversely scanned data is input from R55, one shift is shifted by one register for each clock, and then shifted to R1, and the data according to the output enable signal. Outputs

Next, operation of the apparatus of the present invention will be described with reference to the timing of FIG. 4 and FIG.

First, in the embodiment of the present invention, the inverse scan operation is described assuming that the coefficients of the 8x8 DCT block are zigzag scanned as shown in Table 1 below in the encoding process. However, the technical idea of the present invention is to scan in any order. Applicable

Table 1 shows the order of zigzag scanning 8x8 DCT blocks in the encoding process. 64 DCT coefficients are numbered from 0 to 63 (that is, from low frequency with relatively large coefficient values to high frequency with zero values). Scanning improves the compression efficiency in run-length and variable length coding.

Meanwhile, the image data zigzag scanned in the encoding process as described above should be inversely scanned to restore the original order in decoding.

That is, in Table 1, the temporal order of the actual data is in the order of row numbers 0 to 1, 2, 3, and the order of column numbers 0 to 1, 2, 3, and so on, unlike the order of scanning and outputting the data. . For example, in Table 1, the temporal order of actual data is 0, 1, 5, 6, 14, 15, 27. 28, 2, 4, 7, 13, 16, 26, 29, 42 ..... 35, 36, 48, 49, 57, 58, 62, 63.

Thus, in the case of using 55 shift registers as in the embodiment of the present invention, the generated address generated by the address generator 31 for reverse scanning is 000001 (1) to 110111 (55), which is 8x8 DCT. When arranged in blocks, it is shown in Table 2.

As shown in Table 2, when the address generator 31 generates an address and outputs it to the address decoder 33, the address decoder 33 enables the output of the corresponding register so that the data scanned back through the output buffer is output. To be.

That is, FIG. 4 is a timing diagram showing the operation timing of the inverse scanning apparatus according to the present invention, where CLK represents a clock and a number written on the clock represents a cycle of consecutive clocks. Further, R27 to R32, R37 to R39, R48 to R50, R54, and R55 each represent a part of 55 shift registers, and the data of the shift register is stored from the R55 register 34-6 to the R1 register 34- according to the clock. Shift to 1). In addition, the number written in each shift register is a DCT coefficient data zigzag scanned in an 8x8 block, and is given as a number from 0 to 63 as shown in Table 1 above.

In FIG. 4, the 0th DCT coefficient data of 8x8 blocks is input to the R55 register by the first clock, and the 0th DCT coefficient in the R55 register is shifted to the R54 register by the second clock. DCT coefficient is input. Subsequently, the second DCT coefficient is input to the R55 register to the third clock, and the first DCT coefficient of R55 is shifted and input to the R54 register, and the 0 th DCT coefficient of R54 is shifted to the R53 register although not shown. When this operation is repeated in the same way and becomes the 28th clock, the 27th DCT coefficient is input in the R55 register, the 20th DCT coefficient is input in the R48 register, and the 1st DCT coefficient is input in the R29 register. The 0th DCT coefficient is input to the R28 register.

At this time, the inverse scanning apparatus according to the present invention generates the address 28 to enable the output of the R28 register, so that the 0th DCT coefficient is input to the output register.

In the same way, the 29th clock enables the output of the R28 register to output the first DCT coefficient, and the 30th clock enables the output of the R31 register to output the fifth DCT coefficient, and the 31st clock also registers the R31 register. Enable the output of and output the 6th DCT coefficient.

That is, when the address generator generates 28, 28, 31, 31, 38, 38, 49, and 49 addresses every clock starting from the 28th clock, as shown in Table 2, the corresponding register is enabled to be hatched in FIG. Like the part, 0, 1, 5, 6, 14, 15, 27, 28th DCT coefficients are output, and addresses 22, 23, 25, 30, 16, 41, 43, 55 from 36th clock to 43rd clock. To generate the 2nd, 4th, 7th, 13th, 16th, 26th, 29th, and 42nd DCT coefficients, and backscan in the same manner to restore the original 8x8 DCT block.

As described above, the inverse scan apparatus according to the present invention uses a plurality of shift registers to repeat the shift every clock, generates a predetermined address, enables the output of the register, and restores the DCT block before scanning. Reducing the number of memories required reduces manufacturing costs, as well as reducing the delay time for reverse scanning.

Claims (3)

An inverse scanning apparatus of an image decoder that receives input image data scanned in an image encoding process and performs reverse scanning in a predetermined order, comprising: an address generator (31) for generating an address for the predetermined reverse scanning order; Inverter of image decoder composed of shift register group 32 which receives and stores scanned image data, shifts by clicker, and outputs reverse-scanned image data in a selected order according to the output address of the address generator 31. Scan device. 2. The apparatus according to claim 1, wherein said shift register group (32) comprises: an address decoder (33) for decoding the output address of said address generator (31) to enable the output of a corresponding register; A plurality of shift registers 34-1 to 34-6 which receive the scanned image data, shift the input data every clock, and enable the output according to the output of the address decoder 33; And an output register (35) for buffering the output of the shift register and outputting the reversely scanned image data. The inverse scan apparatus of an image decoder according to claim 2, wherein 55 shift registers are implemented.