KR100238733B1 - Circuit and method for transforming scanning having data packing function of mpeg decoder - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Scan conversion circuit of MPEG decoder and method thereof

2. The technical problem to be solved by the invention

A scan conversion circuit having a function of scanning conversion of input data and packing invalid data components of the input data is implemented.

3. Summary of Solution to Invention

The scan conversion circuit according to the present invention comprises a write address generating means for counting a predetermined bit value when the input data is valid data and generating the counted value as a write address, and in response to the input data being written by a predetermined bit. Counting the bit value and converting the counted value as a read address corresponding to the scan mode, the lead address generating means and the value counted by the lead address generating means are delayed for a predetermined time to count, and the read value is read. A read clock generation means generated by a clock, a storage means, and input data are written to the storage means according to the generated write address, and the data written to the storage means is outputted according to the generated read clock and read address. Characterized in that the data processing means.

4. Important uses of the invention

EMPEG decoder.

Description

Scan conversion circuit having a data packing function of an amp decoder and its conversion method

1 is a diagram showing the structure of a conventional scan matrix.

FIG. 2 is a diagram showing an operation of writing data into the memory of the MPEG decoder, reading the written data, and performing scan conversion.

3 is a block diagram of a scan conversion circuit according to the present invention.

4 is a detailed configuration diagram of the light address generation unit in the configuration of FIG.

5 is a detailed configuration diagram of the lead address generation unit in the configuration of FIG.

6 is a detailed block diagram of the address multiplexing unit in FIG.

7 is a detailed block diagram of the control signal generator of FIG.

8 is a detailed block diagram of the write data processing unit and the read data processing unit in the configuration of FIG.

9 is an operational waveform diagram according to the present invention.

<Explanation of symbols for main parts of drawing>

100: light address generator 200: lead address generator

300: address multiplexer 400: control signal generator

500: light data processing unit 600: lead data processing unit

700: static RAM

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan conversion circuit of an MPEG decoder and a conversion method thereof, and more particularly, to a scan conversion circuit having a data packing function and a conversion method thereof.

With the recent expansion of digital communication technology and the integration of high-density semiconductor (VLSI) and signal processing (DSP) technologies, video data, audio data, and other data that have been generated and processed heterogeneously and independently in the past have been used as information sources and media. It can be processed and used in a wide variety of forms without distinction. In such an environment, the need for standardization of international data transmission standards for digital data for the smooth transmission and sharing of information between different devices has emerged, and according to these needs, the control picture (Joint Picture Experts Group) and moving picture transmission for the transmission of still pictures Moving Picture Experts Group (hereinafter referred to as "MPEG") has been standardized.

According to the MPEG standardization, a method of compressing and multiplexing and transmitting digital video data and audio data, and a method of decoding compressed and transmitted video data and audio data, and the like are specified. According to this provision, digital data is discrete cosine transformed and quantized, and DCT coefficients, which have been quantized, are rearranged into one-dimensional arrays to facilitate data transmission. The rearrangement of the DCT coefficients into one-dimensional arrays is called a scan. The scanned data is finally further compressed by Variable Length Coding. The compressed and transmitted data is then decoded by an MPEG decoder such as a run length decoder.

In general, the order of the data converted by the run length decoder can be divided in two ways for each block (number of 8x8 pixels). The first method is a normal scan defined as scan [0] [U] [V] (aka Zigzag Scan; Zigzag Scan, and the second method is an alternative defined as scan [1] [U] [V]). (Alternative Scan) The order of the data converted by the normal scan and the alternative scan is shown in Fig. 1. (a) of Fig. 1 shows the order of the data converted according to the normal scan. (B) of FIG. 1 shows the order of data converted according to the alternative scan, for example, if a series of input data is normally scanned, the first data is [0, 0], the second data is [0, 1], and the third is The data is output in the order of [1, 0] and the fourth data in the order of [2, 0.] In contrast, when a series of input data is alternatively scanned, the first data is [0, 0] and the second data is [1, 0]. , The third data is [2, 0], the fourth is [3, 0] Is output.

The most common implementation of this scan conversion circuit is shown in FIG. That is, as shown in (a) of FIG. 2, the input data is written to the memory according to the write address, which is a value counted by the counter, and then the value counted by the counter is shown as shown in (b) of FIG. The scan conversion is performed by reading data written in the memory according to the read address, which is a value modified by the deforming unit. Referring to FIGS. 1 and 2, the read addresses are sequentially [0, 1, 2, 3,. . . 63] does not increase but depends on the scan mode. In other words, in normal mode the lead address is [0, 1, 8, 16, 9, 2, 3, 10,. . . 63], and the lead address in alternative mode is [0, 8, 16, 32, 1, 9, 2, 10,. . . 63]. The address mapping may be implemented as a read only memory (ROM), a programmable logic array (PLA), or a logic gate (end gate, or o gate).

However, according to the prior art, a series of scan operations for sequentially writing input data into a memory and reading them out of order according to an address mapping state are performed by different clocks. In addition, when an invalid data element is included in the input data, an invalid data element exists in the data output after the scan conversion.

Accordingly, an object of the present invention is to provide a scan conversion circuit and a conversion method for performing a read operation and a write operation using a single clock.

Another object of the present invention is to provide a scan conversion circuit having a function of scanning and converting input data and packing invalid data components among the input data, and a conversion method thereof.

According to the present invention for achieving the above objects, a series of operations for sequentially writing input data into a memory and reading out of sequence according to an address mapping state is performed by a single clock, and reads an invalid state of the input data. It is directed to a scan conversion circuit that packs during operation to ensure that there is no invalid data in the output data.

The scan decoder circuit of the MPEG decoder according to the present invention includes a write address generating means for counting a predetermined bit value when the input data is valid data and generating the counted value as a write address, and the input data being written by a predetermined bit. In response to counting a predetermined bit value and converting the counted value into a read address corresponding to the scan mode, the lead address generating means and the value counted by the read address generating means are delayed for a predetermined time and counted. A read clock generation means for generating a read clock value, a storage means, and input data to the storage means according to the generated write address, and data written to the storage means and the generated read clock; Data processing means to output according to the lead address It is composed.

In addition, the scan conversion method according to the present invention includes a data writing process of writing the input data at any level of a system clock having the "low" level and the "high" level when the input data is valid data. A data read process of reading the written data at another level of the system clock after being written by a predetermined bit; and if the input data is not valid data, the previously written data is maintained and invalid data is stored. It consists of a process that does not light.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In addition, in the following description, many specific details such as components of specific circuits are shown, which are provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific details. It will be obvious to those skilled in the art. In the following description of the present invention, if it is determined that detailed descriptions of related known functions or configurations may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

First, according to the present invention, a scan conversion method of sequentially writing input data into a memory and reading the data out of order will be described.

The input data according to the present invention will be assumed to be 12 bits for convenience, and this data is synchronized with scan conversion and packing using a BS (Block Start) signal indicating the start of a block. The incoming data is written to the memory at the system clock CLK (eg 27 MHz) and simultaneously read to the modified address. To this end, in the present invention, the read operation is set in the section of the "high" level of the system clock CLK, and the write operation is performed in the section of the "low" level. Alternatively, the read operation may be performed in the section of the "low" level of the system clock CLK, and the write operation may be performed in the section of the "high" level.

According to the write operation of the present invention, it is possible to determine whether the input data is valid or invalid as the VALID signal. That is, if the VALID is at the "high" level, the input data is written because it is normal data. If the VALID is at the "low" level, it is not written. On the other hand, according to the read operation of the present invention, the read operation of the data has a structure that starts after all 64 write data have been written. By doing so, the timing can be stabilized as compared with the structure of the prior art in which bank switching is performed using the block start signal, and no additional circuit is required for the last block.

Accordingly, the overall delay amount depends on the invalid number of input data. However, after the last pixel of the block is written, the first data can be packed and read after 4 clocks. This results in pure data without invalid data for the next 64 data, which can be used directly for inverse quantization and inverse discrete cosine transformation.

Next, the configuration of the scan conversion circuit according to the present invention will be described.

The scan conversion circuit according to the present invention is configured as shown in FIG. 3, and with reference to FIG. 3, the write address generator 100, the read address generator 200, the address multiplexer 300, and the control signal generation are described. The unit 400, the write data processing unit 500, the read data processing unit 600, and a static RAM (hereinafter, referred to as "SRAM") 700 which is a memory are included.

4 is a diagram showing the detailed configuration of the light address generation unit 100 in the configuration of FIG.

In FIG. 4, the 6-bit counter 110 sequentially counts values from 0 to 32 according to the signal VALID indicating whether the input data is valid, the signal BS indicating the start of the block, the reset signal RESET, and the system clock CLK. To generate the write address WADDR [5: 0]. In this case, when "32" is counted, the decoder 112 decodes it and outputs it to wcnt_En for enabling the operation of the 6-bit counter 110. The enable signal wcnt_En is output as a signal Last PEL via the flip-flop 114, the flip-flop 116, the inverter 118, and the AND gate 120, and the output signal Last PEL is input data to be written. Is a signal indicating that the last pixel is.

5 is a diagram showing the detailed configuration of the lead address generation unit 200 in the configuration of FIG.

In FIG. 5, the 6-bit counter 208 sequentially counts values from 0 to 32 according to the signal Last PEL generated by the write address generator 100, the reset signal RESET, and the system clock CLK. At this time, the counted value rcnt [5: 0] is applied to the read address converting ROM (ROM) 212 and is converted into the read address according to the scan mode and output. The read address converted and output in this manner is output to the read address RADDR [5: 0] through the 6-bit registers 214 and 218.

On the other hand, if the value counted by the 6-bit counter 208 is "32", the decoder 210 decodes it and outputs it to the enable signal rcnt_En of the 6-bit counter 208. The enable signal rcnt_En is also output to the read clock RCLK via the flip-flops 220, 222, 226 and the NAND gates 228, 230.

FIG. 6 is a diagram showing the detailed configuration of the address multiplexer 300 in FIG.

In FIG. 6, the multiplexer (MUX) multiplexes the write address WADDR [5: 0] and the lead address RADDR [5: 0] according to the system clock CLK to provide the address ADDR [5: 0] of the SRAM 700. do.

FIG. 7 is a diagram showing a detailed configuration of the control signal generator 400 in FIG.

In FIG. 7, the reset signal RESET is provided as the chip enable signal CE of the SRAM 700, and the signal VALID and the system clock CLK indicating whether the input data is valid are NAND after passing through the flip-flop 402 and the inverter 404. It is provided as a write enable signal WE of the SRAM 700 via the gate 406.

8 is a diagram showing the detailed configuration of the write data processing unit 500 and the read data processing unit 600 in the configuration of FIG.

In FIG. 8, input data DATA_IN [11: 0] is inputted and written to the Din terminal of the SRAM 700 via the 12-bit registers 502 and 506, and data written to the SRAM 700 is written to the Dout terminal. After being output, it is output as output data DATA_OUT [11: 0] through 12-bit registers 602 and 604. At this time, the write operation of the input data is controlled by the system clock CLK, and the read operation is controlled by the read clock RCLK and the system clock CLK.

9 is a view showing an operating waveform according to the present invention, which is an operating waveform according to the configuration shown in FIG.

Referring to FIG. 9, the write operation and the read operation are controlled and performed by a single system clock CLK. Invalid data mixed with the input data is packed so that only valid data is written and then read.

As described above, when the scan conversion is performed according to the present invention, the write operation and the read operation are controlled by a single system clock, and the invalid data mixed in the input data is packed and processed, so that only valid components are output to the data output thereafter. There are advantages that can be included.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (8)

In the MPEG decoder scan conversion circuit, if the input data is valid data, the predetermined bit value is counted and the counted value is generated as the ride address (write address generating means), and the input data is written by the predetermined bit. Counts a predetermined bit value, converts the counted value into a read address corresponding to the scan mode (with the lead address generating means), and counts the value counted by the read address generating means by a predetermined time delay. The input data is written to the storage means according to the read clock generation means, the storage means, and the generated write address, and the data written to the storage means is read. Outputs data according to the generated lead clock and lead address Scanning conversion circuit, characterized by name. The scan conversion circuit according to claim 1, wherein the write address generating means is a first counter that generates a count value by writing a predetermined bit value according to a system clock when the input data is valid data. The decoder of claim 2, further comprising: a decoder for decoding a value counted by the first count and outputting a predetermined bit value as a signal for enabling the operation of the counter when a predetermined bit value is decoded, and outputting the decoder for a predetermined time. And delay means for delaying and outputting a signal indicating that input data has been written by a predetermined bit. The method of claim 3, wherein the read address generating means comprises: a second counter that is cleared according to the output of the delay means and counts a predetermined bit value according to a system clock, and converts the output of the second counter according to a scan mode. A scan conversion circuit comprising a read address converting means for outputting as a read address. The scan conversion circuit according to claim 4, wherein the read address converting means is a ROM, a PLA or a logic gate. 5. The scan conversion circuit according to claim 4, wherein the lead clock generating means comprises a series of delay elements which are generated as lead clocks by delaying a value counted by the second counter by a predetermined time. In the method of scan-converting the compressed and input data, when the input data is valid data, a write address generation process of counting a predetermined bit value and generating the counted value as a write address, and writing the input data by a predetermined bit In response to this, a predetermined bit value is counted and the count value is converted into a read address corresponding to the scan mode, and the read address generation process and the value counted in the read address generation process are delayed and counted. A lead clock generation process of generating a counted value as a read clock, a data line process of writing input data to a predetermined storage means according to the generated write address, and data written to the storage means from the generated read clock; Output according to lead address A scan conversion method characterized in that it consists of a data read process. A method of scanning and converting compressed data, comprising: a data writing process of writing the input data at one level of a system clock having a "low" level and a "high" level when the input data is valid data; A data read process of reading the written data at another level of the system clock after the data has been written by a predetermined bit, and maintaining the previously written data if the input data is not valid data Scan conversion method, characterized in that the data is composed of a process that does not write.