KR100247977B1 - Video decoder having an extensible memory - Google Patents

Abstract

The present invention discloses a video decoder with expandable memory. The present invention provides a video decoder capable of decoding both high definition (HD) television signals and standard (SD) television signals, comprising: a memory controller and a memory control signal for generating a memory control signal for each mode in response to an SH / HD mode signal; It can be used according to various digital video formats including external memory which can be expanded. In particular, in the case of a specific format (SD), only a small memory can be connected to the video decoder to efficiently use the memory.

Description

Video decoder with expandable memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to video decoders, and more particularly, to a video decoder capable of expanding the size of a memory to correspond to various digital image formats.

The MP @ ML (Main Profile at Main Level) video decoder proposed by the Moving Pictures Experts Group of the International Standards Organization (MPEG), an international standard for recently developed two-dimensional video encoding and transmission technology, is SDTV (Standard Definition Television). As digital broadcasting and various multimedia devices are introduced, commercialized chips related to MP @ ML video decoders have been widely used.

However, development for HDTV (High Definition Television) with a resolution of MP @ HL (Main Profile at High Level) is underway, and its practical use is expected in the next few years. At present, MP @ ML level digital broadcasting is being carried out not only in Korea but also in the US and Japan, and HDTV broadcasting at MP @ HL level is expected in the future, and SDTV broadcasting and HDTV broadcasting are expected to coexist. Therefore, the MP @ ML video decoder is expected to coexist for a considerable time even if the MP @ HL video decoder is used.

Here, a memory capacity of about 2.5-3 frames is required to decode data compressed using MPEG-1 or MPEG-2 in HDTV, SDTV, and the like. However, since the HDTV signal has about 6 times more pixels than the SDTV signal, the memory capacity required for decoding should also be about 6 times larger. In the commercially available SD (MP @ ML) level video decoder, the frame memory required for video decoding is used as an external memory. However, MP @ HL video decoders are currently being developed in various countries, but are not yet commercially available.

In order to cope with the coexistence between SDTV broadcasting and HDTV broadcasting, it is inefficient to separate the SD video decoder and the HD video decoder so that the structure of decoding both the SD signal and the HD signal, for example, the HD video decoder decodes the SD signal The structure which makes it possible is also preferable. However, even in this case, when the video decoder is limited to decoding the SD signal, there is an uneconomical problem when a large memory for decoding the HD signal is used for decoding the SD signal.

Accordingly, an object of the present invention is to provide a video decoder that can expand the size of a memory to correspond to various digital video formats, and efficiently use the memory by using only a small amount of memory for a specific video format having a resolution of SD. There is.

In order to achieve the above object, the video decoder according to the present invention is a video decoder capable of decoding both a high definition (HD) television signal and a standard (SD) television signal, the memory for each mode in response to the SH / HD mode signal The memory controller is configured to generate a control signal and is driven according to the memory control signal, and includes an expandable external memory.

1 is a block diagram according to an embodiment of a video decoder according to the present invention.

FIG. 2 is an example of a memory controller and an external memory shown in FIG. 1.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of a video decoder with an expandable memory according to the present invention.

First, the standardized digital television format in the United States is classified into the HDTV format and the SDTV format. The formats are as follows.

HDTV

⋅ 1280 × 720 progressive (60 / 59.94 frame / sec)

⋅ 1280 × 720 progressive (30 / 29.97 frame / sec)

⋅ 1280 × 720 progressive (24 / 23.98 frame / sec)

⋅ 1920 × 1080 interlaced (60 / 59.94 field / sec)

⋅ 1920 × 1080 progressive (30 / 29.97 frame / sec)

⋅ 1920 × 1080 progressive (24 / 23.98 frame / sec)

SDTV

⋅ 640 × 480 progressive (60 / 59.94 frame / sec)

⋅ 640 × 480 interlaced (60 / 59.94 field / sec)

⋅ 640 × 480 progressive (30 / 29.97 frame / sec)

⋅ 640 × 480 progressive (24 / 23.98 frame / sec)

⋅ 720 × 480 progressive (60 / 59.94 frame / sec)

⋅ 720 × 480 progressive (30 / 29.97 frame / sec)

Where 720 × 480 × The progressive format belongs to MP @ HL but is included in the SDTV input format for convenience.

In order to decode all of the above digital image formats, one frame area of the external frame memory of the video decoder may be × 1080 bits), and a small amount of frame memory is required to decode an SD signal rather than to decode an HD signal. In the conventional HDTV video decoder, when the SD signal is decoded, only a part of the frame memory for decoding the HD signal is used, which makes the use of the memory inefficient.

Therefore, in the video decoder capable of decoding both SD and HD signals, in the case of a dedicated decoding mode for the SD signals, only a small capacity external memory for decoding the SD signals is used, and the decoding for the HD signals is performed. In the case of the mode, the external memory is expanded to correspond to the decoding of the HD signal.

1 is a block diagram according to an embodiment of a video decoder according to the present invention. In FIG. 1, an input bitstream may be input to the preprocessor 102 in the form of an elementary stream (ES) or a packetized elementary stream (PES). When PES is input to the preprocessor 102, the PES packet header is removed. The video elementary stream extracted from the PES is stored in the bit buffer area of the external memory 106 through the memory controller 104. In addition, the preprocessor 102 extracts the PTS (Presentation Time Stamp) and the DTS (Decoding Time Stamp) from the PES packet header and outputs them to the display processor 116 via the bus.

The external memory 106 has a bit buffer region for storing the video bit stream output from the preprocessor 102 before the variable length decoding, and if the decoding time and the presentation time do not coincide with each other according to the picture type, There is a frame storage area for storing about 2.5-3 frames of decoded data to display the decoded data based thereon.

Data stored in the bit buffer area of the external memory 106 is read out and applied to the variable length decoder 108 under the control of the memory controller 104. The variable length decoder 108 parses various header information necessary for decoding and discrete cosine transform (DCT) coefficients, and outputs the analyzed DCT coefficients to an inverse quantization (IQ) / inverse discrete transform (IDCT) block 110. do. In addition, the variable length decoder 108 outputs header information necessary for system control to a system controller (not shown) through the host interface 118.

The block 110 performs inverse quantization, inverse DCT and mismatch control of the DCT coefficients output from the variable length decoder 108, and outputs the result to the motion compensator (MC) 114. If the output of the block 110 is an I (Intra-coded) picture, the motion compensator 114 stores the data in the frame storage area of the external memory 106 through the memory controller 104, and the output of the block 110 is P ( In the case of a Predicted-coded (Bidirectionally-coded) picture or a B (Bidirectionally-coded) picture, the data stored in the frame storage area of the external memory 106 is added to the output of the block 110 to restore the restored data through the memory controller 104 again. In the frame storage area of 106). The display processor 116 reads the data of the last restored frame stored in the external memory 106 through the memory controller 104 and controls the display timing based on the PTS output from the preprocessor 102.

The address generator 112 generates an address for driving the external memory 106 according to the SD / HD mode signal output from the system controller through the host interface 118. The address generator 112 also reads a write address for storing the output of the preprocessor 102 in the bit buffer area of the external memory 106 and reads the data stored in the bit buffer area to the variable length decoder 108. A read address for storing the output of the motion compensator 114 in the frame storage region, a read address for reading the decoded data stored in the frame storage region and applying the decoded data to the motion compensator 114, and stored in the frame storage region. A read address or the like for reading the decoded data and applying it to the display processor 116 is generated.

FIG. 2 is a diagram for describing the memory controller 104 and the external memory 106 shown in FIG. 1. In FIG. 2, the memory controller 104 uses the SD / HD mode signal generated by the system controller through the address generator 112, that is, the external memory 106 by using a mode signal indicating whether the SD decoding mode or the HD decoding mode is used. Configure memory map for each region of.

In this case, in the SD-only decoding mode, since the external memory 106 can decode the SD signal using only the first memory BANK0: 120, the memory controller 104 drives the memory control signal for driving the first memory 120. (RAS0, CAS) is generated. That is, in the SD-only decoding mode, since the second memories BANK1 122 are not configured, RAS1 of the address control signals generated by the memory controller 104 is in an inactive state.

In the HD decoding mode, since both the first and second memories 120 and 122 are connected to the memory controller 104, the memory controller 104 outputs active memory control signals RAS0, RAS1, and CAS. In this case, each of the memories 120 and 122 includes four 16 Mbits of RAM, one of which is used for the bit buffer, and the other three, which is used as the frame memory for decoding. The memory capacity of this 64Mbits is 1280 × The progressive format of 720 is also decodable.

Accordingly, in the embodiment of the present invention, only the first memory 120 having a capacity of 64 Mbits is mounted and driven in the SD decoding mode, and both the first and second memories 120 and 122 are mounted and driven in the HD decoding mode. However, other memory may be expanded and mounted in the memory controller 104 as needed, and in this case, the memory controller 106 may include a memory control signal for controlling driving of the extended external memory 106 in software. .

As described above, the present invention can expand the configuration of an external memory connected to the video decoder in a video decoder capable of decoding both SD and HD signals, corresponding to various digital video formats, and in particular, to a specific format ( In the case of SDTV only or progressive only), the memory can be efficiently used by only connecting a small amount of memory to the video decoder.

Claims (9)

In a video decoder capable of decoding both high definition (HD) signals and standard definition (SD) signals: A memory controller for generating a memory control signal for each mode in response to the SH / HD mode signal; And And a scalable external memory driven according to the memory control signal. The method of claim 1, wherein the external memory And a first memory driven in both SD and HD modes according to the memory control signal. The method of claim 2, wherein the external memory And a second memory driven only in the HD mode according to the memory control signal. The method of claim 1, wherein the external memory A video decoder comprising a bit buffer region for variable length decoding and a frame storage region for video decoding. The method of claim 4, wherein A preprocessor extracting the video elementary stream and the presentation information from an input bitstream and outputting the video elementary stream to a bit buffer storage area of the external memory; A variable length decoder for reading data stored in the bit buffer area under the control of the memory controller and analyzing the discrete cosine transform (DCT) coefficients; A block for performing an operation such as inverse quantization of the DCT coefficient, inverse DCT, and mismatch control; A motion compensator for outputting the output of the block to a frame storage area of the external memory and reconstructing a frame image by adding the output of the block and decoded data stored in the frame storage area; A display processor for controlling display of the decoded data stored in the frame storage area according to the presentation information by controlling the memory controller; And And an address generator for generating a write / read address for writing and reading the address required for driving the external memory and the data required for each unit in accordance with the SD / HD mode signal. Decoder. A receiver comprising a system controller for generating a control signal according to an input image format: An external memory expandable to correspond to various input image formats; And And a memory controller for generating a memory control signal for driving the external memory in response to a control signal indicating the input image format. The method of claim 6, wherein the external memory And a first memory configured to store input data in a standard video format and a high resolution video format according to the memory control signal. The method of claim 7, wherein the external memory And a second memory configured to store input data of a high resolution image format according to the memory control signal. The method of claim 7, wherein the external memory And a bit buffer region for variable length decoding of the input data, and a frame storage region for video decoding.

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