KR970009407A - Reverse scan device of video decoder - Google Patents

Reverse scan device of video decoder Download PDF

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Publication number
KR970009407A
KR970009407A KR1019950022592A KR19950022592A KR970009407A KR 970009407 A KR970009407 A KR 970009407A KR 1019950022592 A KR1019950022592 A KR 1019950022592A KR 19950022592 A KR19950022592 A KR 19950022592A KR 970009407 A KR970009407 A KR 970009407A
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KR
South Korea
Prior art keywords
output
address
image data
decoder
shift
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Application number
KR1019950022592A
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Korean (ko)
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KR0180163B1 (en
Inventor
이상일
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배순훈
대우전자 주식회사
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Priority to KR1019950022592A priority Critical patent/KR0180163B1/en
Publication of KR970009407A publication Critical patent/KR970009407A/en
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Publication of KR0180163B1 publication Critical patent/KR0180163B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/625—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using discrete cosine transform [DCT]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/129—Scanning of coding units, e.g. zig-zag scan of transform coefficients or flexible macroblock ordering [FMO]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Discrete Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Compression Of Band Width Or Redundancy In Fax (AREA)

Abstract

본 발명은 영상복호기의 역스캔장치에 관한 것으로, 어드레스발생기(31)와; 어드레스 발생기(31)의 출력어드레스를 디코딩하여 해당되는 레지스터의 출력을 인에이블시키는 어드레스 디코더(33); 스캔된 영상데이타를 입력받아 매 클럭마다 입력된 데이타를 시프트시키며 상기 어드레스 디코더(33)의 출력에 따라 출력을 인에이블시키는 다수개의 시프트 레지스터(34-1 ~ 34-6); 및 상기 시프트 레지스터의 출력을 버퍼링하여 역스캔된 영상데이타를 출력하는 출력레지스터(35)로 구성되어 스캔전의 DCT 블럭으로 복원하므로 소요되는 메모리 수를 줄여 제조비용을 절감함과 아울러 역스캔을 위해 지연되는 시간을 감소시킬 수 있는 효과가 있다.The present invention relates to an inverse scan device of an image decoder, comprising: an address generator (31); An address decoder 33 for decoding the output address of the address generator 31 and enabling the output of the corresponding register; A plurality of shift registers 34-1 to 34-6 which receive the scanned image data, shift the input data every clock, and enable the output according to the output of the address decoder 33; And an output register 35 that buffers the output of the shift register and outputs reversely scanned image data, thereby restoring to a DCT block before scanning, thereby reducing the number of memories required and reducing manufacturing costs and delaying for reverse scanning. There is an effect that can reduce the time it takes.

Description

영상복호기의 역스캔장치Reverse scan device of video decoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 역스캔장치를 도시한 블럭도, 제4도는 본 발명에 따른 역 스캔장치의 동작 타이밍도이다.3 is a block diagram showing an inverse scan device according to the present invention, and FIG. 4 is an operation timing diagram of the reverse scan device according to the present invention.

Claims (3)

영상부호화 과정에서 스캔된 영상 데이타를 입력받아 소정의 순서로 역스캔하는 영상복호화기의 역스캔장치에 있어서, 상기 소정의 역스캔순서를 위한 어드레스를 발생하는 어드레스 발생기(31)와; 스캔된 영상데이타를 입력받아 저장하며 클러에 의해 시프트한후 상기 어드레스 발생기(31)의 출력어드레스에 따라 선택된 순서대로 역스캔된 영상데이타를 출력하는 시프트 레지스터군(32)으로 구성되는 영상복호기의 역스캔장치.An inverse scanning apparatus of an image decoder that receives input image data scanned in an image encoding process and performs reverse scanning in a predetermined order, comprising: an address generator (31) for generating an address for the predetermined reverse scanning order; Inverter of image decoder composed of shift register group 32 which receives and stores scanned image data, shifts by clicker, and outputs reverse-scanned image data in a selected order according to the output address of the address generator 31. Scan device. 제1항에 있어서, 상기 시프트 레지스터군(32)은 상기 어드레스 발생기(31)의 출력어드레스를 디코딩하여해당되는 레지스터의 출력을 인에이블시키는 어드레스 디코더(33)와; 스캔된 영상데이타를 입력받아 매 클럭마다 입력된데이타를 시프트시키며 상기 어드레스 디코더(33)의 출력에 따라 출력을 인에이블시키는 다수개의 시프트 레지스터(34-1~ 34-6); 및 상기 시프트 레지스터의 출력을 버퍼링하여 역스캔된 영상데이타를 출력하는 출력레지스터(35)로 구성되는것을 특징으로 하는 영상복호기의 역스캔장치.2. The apparatus according to claim 1, wherein said shift register group (32) comprises: an address decoder (33) for decoding the output address of said address generator (31) and enabling the output of a corresponding register; A plurality of shift registers 34-1 to 34-6 which receive the scanned image data and shift the input data every clock and enable the output according to the output of the address decoder 33; And an output register (35) for buffering the output of the shift register and outputting reversely scanned image data. 제2항에 있어서, 상기 시프트레지스터가 55개로 구현된 것을 특징으로 하는 영상복호기의 역스캔장치.The inverse scan apparatus of an image decoder according to claim 2, wherein 55 shift registers are implemented. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950022592A 1995-07-27 1995-07-27 An inverse scanner in an image decoder KR0180163B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950022592A KR0180163B1 (en) 1995-07-27 1995-07-27 An inverse scanner in an image decoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950022592A KR0180163B1 (en) 1995-07-27 1995-07-27 An inverse scanner in an image decoder

Publications (2)

Publication Number Publication Date
KR970009407A true KR970009407A (en) 1997-02-24
KR0180163B1 KR0180163B1 (en) 1999-05-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102224698B1 (en) * 2020-08-11 2021-03-05 주식회사 신세계아이앤씨 Basket loading system for checkout

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102224698B1 (en) * 2020-08-11 2021-03-05 주식회사 신세계아이앤씨 Basket loading system for checkout

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KR0180163B1 (en) 1999-05-01

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