KR940010770A - Aspect ratio conversion output device - Google Patents

Aspect ratio conversion output device Download PDF

Info

Publication number
KR940010770A
KR940010770A KR1019920019744A KR920019744A KR940010770A KR 940010770 A KR940010770 A KR 940010770A KR 1019920019744 A KR1019920019744 A KR 1019920019744A KR 920019744 A KR920019744 A KR 920019744A KR 940010770 A KR940010770 A KR 940010770A
Authority
KR
South Korea
Prior art keywords
signal
timing generating
control signal
receiving
output signal
Prior art date
Application number
KR1019920019744A
Other languages
Korean (ko)
Other versions
KR960012484B1 (en
Inventor
김영환
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019920019744A priority Critical patent/KR960012484B1/en
Publication of KR940010770A publication Critical patent/KR940010770A/en
Application granted granted Critical
Publication of KR960012484B1 publication Critical patent/KR960012484B1/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00Television systems
    • H04N7/01Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)
  • Picture Signal Circuits (AREA)

Abstract

본 발명은 텔레비젼의 대화면화에 따른 화면의 종횡비(ASPECT) 변환 출력 장치에 관한 것이다.The present invention relates to an aspect ratio (ASPECT) conversion output device of a screen according to a large screen of a television.

따라서, 본 발명은 읽기 제어 신호와 쓰기 제어 신호를 발생하는 타이밍 발생수단(5)과, 상기 타이밍 발생수단(5)으로부터의 신호를 인가받아 저장하기 위한 프레임 메모리 수단(1)과, 상기 프레임 메모리 수단(1)으로부터 출력되는 신호와 상기 타이밍 발생수단(5)으로부터의 쓰기 제어 신호를 인가받아 출력신호를 내는 제1시프트 레지스터 수단(2)과, 상기 제1시프트 레지스터 수단(2)으로부터의 레지스터 수단(2)으로부터의 출력신호와 상기 타이밍 발생수단(5)이 출력신호를 인가받아 논리 연산하기 위한 연산 수단(3)과, 상기 연산 수단(3)에 의해 연산된 신호를 인가받고 상기 타이밍 발생수단(5)으로 부터 읽기 제어 신호를 인가 받는 제2시프트 레지스터 수단(4)으로 구비한 것을 특징으로 하다.Accordingly, the present invention provides a timing generating means 5 for generating a read control signal and a write control signal, a frame memory means 1 for receiving and storing a signal from the timing generating means 5, and the frame memory. First shift register means (2) for receiving an output signal from the means (1) and a write control signal from the timing generating means (5) to produce an output signal, and a register from the first shift register means (2) An output signal from the means 2 and the arithmetic means 3 for logic calculation by the timing generating means 5, and a signal calculated by the arithmetic means 3 to receive the output signal And second shift register means 4 for receiving a read control signal from the means 5.

Description

종횡비 변환 출력장치Aspect ratio conversion output device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명의 블럭 구성도,5 is a block diagram of the present invention;

제6도는 제5도의 본 발명의 설명하기 위한 타이밍도,6 is a timing diagram for explaining the present invention of FIG.

제7도는 제5도의 연산부에 실시되는 연산과정의 일예를 예시하는 도면.FIG. 7 is a diagram illustrating an example of a calculation process performed in the calculation unit of FIG. 5.

Claims (1)

읽기 제어 신호와 쓰기 제어 신호를 발생하는 타이밍 발생수단(5)과, 상기 타이밍 발생수단(5)으로부터의 신호를 인가받아 저장하기 위한 프레임 메모리 수단(1)과, 상기 프레임 메모리 수단(1)으로부터 출력되는 신호와 상기 타이밍 발생수단(5)으로부터의 쓰기 제어 신호를 인가받아 출력신호를 내는 제1시프트 레지스터 수단(2)과, 상기 제1시프트 레지스터 수단(2)으로부터의 레지스터 수단(2)으로 부터의 출력신호와 상기 타이밍 발생수단(5)이 출력신호를 인가받아 논리 연산하기 위한 연산 수단(3)과, 상기 연산 수단(3)에 의해 연산된 신호를 인가받고 상기 타이밍 발생수단(5)으로부터 읽기 제어 신호를 인가 받는 제2시프트 레지스터 수단(4)으로 구비한 것을 특징으로 하는 종횡비 변환 출력 장치.Timing generating means (5) for generating a read control signal and a write control signal, a frame memory means (1) for receiving and storing a signal from said timing generating means (5), and from said frame memory means (1) A first shift register means 2 for receiving an output signal and a write control signal from the timing generating means 5 and outputting an output signal, and a register means 2 from the first shift register means 2; The output signal and the timing generating means (5) for receiving the output signal and calculating the logic means (3), the signal calculated by the calculating means (3) receives the timing generating means (5) And a second shift register means (4) for receiving a read control signal from the apparatus. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920019744A 1992-10-26 1992-10-26 Aspect ratio conversion apparatus KR960012484B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920019744A KR960012484B1 (en) 1992-10-26 1992-10-26 Aspect ratio conversion apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920019744A KR960012484B1 (en) 1992-10-26 1992-10-26 Aspect ratio conversion apparatus

Publications (2)

Publication Number Publication Date
KR940010770A true KR940010770A (en) 1994-05-26
KR960012484B1 KR960012484B1 (en) 1996-09-20

Family

ID=19341766

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920019744A KR960012484B1 (en) 1992-10-26 1992-10-26 Aspect ratio conversion apparatus

Country Status (1)

Country Link
KR (1) KR960012484B1 (en)

Also Published As

Publication number Publication date
KR960012484B1 (en) 1996-09-20

Similar Documents

Publication Publication Date Title
KR890017977A (en) Video signal conversion device
KR970003207A (en) Clock generator of semiconductor memory device
KR900002647A (en) Super Infos Device
KR910001771A (en) Semiconductor memory device
KR970008876A (en) Pulse Width Modulation Circuit
KR910017759A (en) Sequence Action Logic Device
KR970029883A (en) Test circuit and method of semiconductor memory device with high frequency operation
KR940010770A (en) Aspect ratio conversion output device
KR960036681A (en) Motion compensation device to eliminate blocking
JPS5787288A (en) Video signal processing device
SU1113845A1 (en) Device for digital magnetic recording
KR850005112A (en) Video display control device
SU1746393A1 (en) Device for training operators
KR930017410A (en) Video signal processing device
KR930014509A (en) High resolution video signal processing device using low frequency oscillator
KR960042370A (en) Block light control circuit and block light control method of semiconductor memory device
KR970049578A (en) Memory control circuit
KR910006909A (en) Display controller
KR960042337A (en) Random number generator using linear feedback shift register with changeable order
KR960011762A (en) Control Circuit of Image Processing Dedicated Device
KR970029301A (en) Liquid crystal display signal processing circuit of data enable signal priority processing
KR970002653A (en) Random Accessible FIFO
TW264548B (en) Device for scaling and overlaying video with computer graphic display
KR960030680A (en) TV's field frequency conversion circuit
KR950030676A (en) Image data storage device for display and its storage method

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19990831

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee