KR940010770A - Aspect ratio conversion output device - Google Patents
Aspect ratio conversion output device Download PDFInfo
- Publication number
- KR940010770A KR940010770A KR1019920019744A KR920019744A KR940010770A KR 940010770 A KR940010770 A KR 940010770A KR 1019920019744 A KR1019920019744 A KR 1019920019744A KR 920019744 A KR920019744 A KR 920019744A KR 940010770 A KR940010770 A KR 940010770A
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- timing generating
- control signal
- receiving
- output signal
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Systems (AREA)
- Picture Signal Circuits (AREA)
Abstract
본 발명은 텔레비젼의 대화면화에 따른 화면의 종횡비(ASPECT) 변환 출력 장치에 관한 것이다.The present invention relates to an aspect ratio (ASPECT) conversion output device of a screen according to a large screen of a television.
따라서, 본 발명은 읽기 제어 신호와 쓰기 제어 신호를 발생하는 타이밍 발생수단(5)과, 상기 타이밍 발생수단(5)으로부터의 신호를 인가받아 저장하기 위한 프레임 메모리 수단(1)과, 상기 프레임 메모리 수단(1)으로부터 출력되는 신호와 상기 타이밍 발생수단(5)으로부터의 쓰기 제어 신호를 인가받아 출력신호를 내는 제1시프트 레지스터 수단(2)과, 상기 제1시프트 레지스터 수단(2)으로부터의 레지스터 수단(2)으로부터의 출력신호와 상기 타이밍 발생수단(5)이 출력신호를 인가받아 논리 연산하기 위한 연산 수단(3)과, 상기 연산 수단(3)에 의해 연산된 신호를 인가받고 상기 타이밍 발생수단(5)으로 부터 읽기 제어 신호를 인가 받는 제2시프트 레지스터 수단(4)으로 구비한 것을 특징으로 하다.Accordingly, the present invention provides a timing generating means 5 for generating a read control signal and a write control signal, a frame memory means 1 for receiving and storing a signal from the timing generating means 5, and the frame memory. First shift register means (2) for receiving an output signal from the means (1) and a write control signal from the timing generating means (5) to produce an output signal, and a register from the first shift register means (2) An output signal from the means 2 and the arithmetic means 3 for logic calculation by the timing generating means 5, and a signal calculated by the arithmetic means 3 to receive the output signal And second shift register means 4 for receiving a read control signal from the means 5.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제5도는 본 발명의 블럭 구성도,5 is a block diagram of the present invention;
제6도는 제5도의 본 발명의 설명하기 위한 타이밍도,6 is a timing diagram for explaining the present invention of FIG.
제7도는 제5도의 연산부에 실시되는 연산과정의 일예를 예시하는 도면.FIG. 7 is a diagram illustrating an example of a calculation process performed in the calculation unit of FIG. 5.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920019744A KR960012484B1 (en) | 1992-10-26 | 1992-10-26 | Aspect ratio conversion apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920019744A KR960012484B1 (en) | 1992-10-26 | 1992-10-26 | Aspect ratio conversion apparatus |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940010770A true KR940010770A (en) | 1994-05-26 |
KR960012484B1 KR960012484B1 (en) | 1996-09-20 |
Family
ID=19341766
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920019744A KR960012484B1 (en) | 1992-10-26 | 1992-10-26 | Aspect ratio conversion apparatus |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960012484B1 (en) |
-
1992
- 1992-10-26 KR KR1019920019744A patent/KR960012484B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR960012484B1 (en) | 1996-09-20 |
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E701 | Decision to grant or registration of patent right | ||
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FPAY | Annual fee payment |
Payment date: 19990831 Year of fee payment: 4 |
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