KR970004740A - Load Clock Generator for Rearrange Data in PDTV - Google Patents

Load Clock Generator for Rearrange Data in PDTV Download PDF

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Publication number
KR970004740A
KR970004740A KR1019950018654A KR19950018654A KR970004740A KR 970004740 A KR970004740 A KR 970004740A KR 1019950018654 A KR1019950018654 A KR 1019950018654A KR 19950018654 A KR19950018654 A KR 19950018654A KR 970004740 A KR970004740 A KR 970004740A
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KR
South Korea
Prior art keywords
parallel
image data
digital image
shift register
hexadecimal
Prior art date
Application number
KR1019950018654A
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Korean (ko)
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KR0159373B1 (en
Inventor
박원정
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배순훈
대우전자 주식회사
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Priority to KR1019950018654A priority Critical patent/KR0159373B1/en
Publication of KR970004740A publication Critical patent/KR970004740A/en
Application granted granted Critical
Publication of KR0159373B1 publication Critical patent/KR0159373B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
    • H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/91—Television signal processing therefor

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

본 발명은 PDP(Plasma Display Panel) 표시 장치를 구비한 TV에 있어서, 특히 디지탈화된 영상 데이타를 재배열하여 PDP표시 장치에 출력하는 데이타 재배열 장치의 데이타 재배열 순서를 제어하는 로드 클럭(load clock) 생성기에 관한 것으로, 병렬로 입력되는 디지탈 영상 데이타를 직렬로 변환하여 출력하는 8비트 시프트 레지스터 8개가 병렬로 구성된 제1시프트 레지스터군(301 내지 308)과, 상기 제1시프트 레지스터군(301 내지 308)과 병렬로 연결되어 병렬로 입력되는 디지탈영상 데이타를 직렬로 변환하여 출력하는 8비트 시프트 레지스터 8개가 병렬로 구성된 제2시프트 레지스터군(309 내지 316)으로 구성되어 입력되는 디지탈 영상 데이타의 저장과 저장된 디지탈 영상 데이타의 출력을 교번적으로 수행하는 PDP-TV의 데이타 재배열 장치에 있어서; 기 설정 주기를 갖는 클록 신호(CLK)를 16진 카운트하여 출력하는 16진 카운터(501), 상기 16진 카운터(501)의 각 카운터값에 대응하는 하나의 출력단자에 상기 제1 및 제2시프트 레지스터군(301 내지 316)에 디지탈 영상 신호가 순차적으로 저장되도록 제어하는 로드 신호를 발생하는 디코더(502)를 구비하여 구성한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load clock for controlling a data rearrangement order of a data rearrangement apparatus for rearranging digitalized image data and outputting the digitalized image data to a PDP display apparatus in a TV having a plasma display panel (PDP) display apparatus. A first shift register group (301 to 308) and eight first shift register groups (301 to 308) configured to parallelly convert and output digital video data inputted in parallel in series. Storage of digital image data, which is composed of second shift register groups 309 to 316 configured in parallel to eight 8-bit shift registers connected in parallel to the digital image data input in parallel and serially converted and output. A data rearrangement apparatus of a PDP-TV which alternately performs output of stored digital image data; The hexadecimal counter 501 for hexadecimal counting and outputting a clock signal CLK having a predetermined period, and the first and second shifts to one output terminal corresponding to each counter value of the hexadecimal counter 501. And a decoder 502 for generating a load signal for controlling digital image signals to be sequentially stored in the register groups 301-316.

Description

피디피 티브이의 데이타 재배열을 위한 로드 클럭 생성기Load Clock Generator for Rearrange Data in PDTV

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명의 실시예를 나타내는 상세 회로도, 제6도는 본 발명의 실시예에 따른 타이밍도.5 is a detailed circuit diagram illustrating an embodiment of the present invention, and FIG. 6 is a timing diagram according to an embodiment of the present invention.

Claims (3)

병렬로 입력되는 디지탈 영상 데이타를 직렬로 변환하여 출력하는 8비트 시프트 레지스터 8개가 병렬로 구성된 제1시프트 레지스터군(301 내지 308)과, 상기 제1시프트 레지스터군(301 내지 308)과 병렬로 연결되어 병렬로 입력되는 디지탈 영상 데이타를 직렬로 변환하여 출력하는 8비트 시프트 레지스터 8개가 병렬로 구성된 제2시프트 레지스터군(309 내지 316)으로 구성되어 입력되는 디지탈 영상 데이타의 저장과 저장된 디지탈 영상 데이타의 출력을 교번적으로 수행하는 PDP-TV의 데이타 재배열 장치에 있어서, 기 설정 주기를 갖는 클록 신호(CLK)를 16진 카운트하여 출력하는 16진카운터(501), 상기 16진 카운터(501)의 각 카운터값에 대응하는 하나의 출력단자에 상기 제1 및 제2시프트 레지스터군(301 내지 316)에 디지탈 영상 신호가 순차적으로 저장되도록 제어하는 로드 신호를 발생하는 디코더(502)를 구비하여 구성하는 로드 신호 발생 장치.Eight 8-bit shift registers for converting and outputting digital image data inputted in parallel in series are connected in parallel with the first shift register groups 301 to 308 configured in parallel and the first shift register groups 301 to 308 in parallel. The 8-bit shift registers 309 to 316 configured in parallel to the 8-bit shift registers for converting and outputting the digital image data inputted in parallel and outputted in series to store the input digital image data and to store the stored digital image data. In the data rearrangement apparatus of the PDP-TV which performs the output alternately, the hexadecimal counter 501 which hexadecimal counts and outputs the clock signal CLK having a predetermined period, and the hexadecimal counter 501 of the hexadecimal counter 501. Control so that the digital video signal is sequentially stored in the first and second shift register groups 301 to 316 at one output terminal corresponding to each counter value. A load signal generating apparatus constructed by a decoder 502 to generate a load signal. 제1항에 있어서, 상기 16진 카운터(501)는 프레임 동기 신호에 의해 클리어 되는 로드 신호 발생 장치.The load signal generator of claim 1, wherein the hexadecimal counter (501) is cleared by a frame synchronization signal. 제1항 또는 제2항에 있어서, 상기 디코더(502)는 프레임 동기 신호에 의해 디스에이블 되는 로드 신호 발생기.3. The load signal generator of claim 1 or 2, wherein the decoder (502) is disabled by a frame sync signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950018654A 1995-06-30 1995-06-30 Load clock generator for data rearrangement of pdp-tv KR0159373B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950018654A KR0159373B1 (en) 1995-06-30 1995-06-30 Load clock generator for data rearrangement of pdp-tv

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950018654A KR0159373B1 (en) 1995-06-30 1995-06-30 Load clock generator for data rearrangement of pdp-tv

Publications (2)

Publication Number Publication Date
KR970004740A true KR970004740A (en) 1997-01-29
KR0159373B1 KR0159373B1 (en) 1999-01-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100403512B1 (en) * 1998-06-30 2003-12-18 주식회사 대우일렉트로닉스 PDTV's data interface circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100403512B1 (en) * 1998-06-30 2003-12-18 주식회사 대우일렉트로닉스 PDTV's data interface circuit

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Publication number Publication date
KR0159373B1 (en) 1999-01-15

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