KR970076843A

KR970076843A - Synchronous Mirror Delay Circuit

Info

Publication number: KR970076843A
Application number: KR1019960018518A
Authority: KR
Inventors: 이정배; 배용철
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1996-05-29
Filing date: 1996-05-29
Publication date: 1997-12-12
Also published as: KR0183870B1

Abstract

본 발명은 싱크로너스 미러 딜레이 회로에 관해 개시한다. 본 발명은 외부클락을 제1지연시간으로 지연시켜 제1내부클락을 출력하는 출력버퍼와, 상기 제1내부클락을 제2지연시간으로 지연시키는 딜레이 모니터링 회로와, 서로 다른 지연시간을 갖는 제1 내지 제n단위지연기(n2)로 구성되고 상기 딜레이 모니터링 회로의 출력을 제3지연시간으로 지연시키는 저방향 딜레이 어레이와, 상기 제1내부클락에 응답하여 상기 정방향 딜레이 어레이의 출력을 반전시키는 미러 제어회로와, 서로 다른 지연시간을 갖는 제1 내지 제n단위지연기(n2)로 구성되고 상기 미러 제어회로의 출력을 제3지연시간으로 지연시키는 역방향 딜레이 어레이와, 상기 역방향 딜레이 어레이의 출력을 제4지연시간으로 지연시켜 제2내부클락을 출력하는 클락 드라이버를 포함하는 것을 특징으로 한다. 따라서 본 발명은 저주파, 즉 긴 주기를 갖는 외부클락에 락킹되는 내부클락을 발생하는 데 적은 수의 단위지연기가 소용되고, 이에 따라 레이아웃면적이 감소될 수 있다.The present invention discloses a synchronous mirror delay circuit. The present invention provides an output buffer for outputting a first internal clock by delaying an external clock to a first delay time, a delay monitoring circuit for delaying the first internal clock to a second delay time, and a first delay having a different delay time. A delay delay array configured to an nth delay unit n2 and delaying the output of the delay monitoring circuit to a third delay time, and a mirror inverting the output of the forward delay array in response to the first internal clock. A reverse delay array comprising a control circuit, first to nth unit delays n2 having different delay times, for delaying the output of the mirror control circuit to a third delay time, and an output of the reverse delay array. And a clock driver configured to output a second internal clock by delaying the fourth delay time. Accordingly, the present invention utilizes a small number of unit delay units to generate an inner clock that is locked to an external clock having a low frequency, that is, a long period, and thus the layout area can be reduced.

Description

Synchronous Mirror Delay Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 실시예에 따른 싱크로너스 미러 딜레이 회로의 블락도, 제4도는 제2도의 싱크로너스 미러딜레이 회로의 동작 타이밍도.2 is a block diagram of a synchronous mirror delay circuit according to an embodiment of the present invention, and FIG. 4 is an operation timing diagram of the synchronous mirror delay circuit of FIG.

Claims

A synchronous mirror delay circuit for generating an internal clock synchronized with an external clock, the synchronous mirror delay circuit comprising: an output buffer for outputting a first internal clock by delaying an external clock to a first delay time, and a delay time for the first internal clock to a second delay time; A delay monitoring circuit and a first to nth unit delay units (n > 2) having different delay times are sequentially connected in a forward direction to delay the output of the delay monitoring circuit to a third delay time. A low delay delay array, a mirror control circuit for inverting the output of the forward delay array in response to the first internal clock, and first to nth unit delay units n> 2 having different delay times are reversed in a reverse direction. A reverse delay array configured to be sequentially connected in series and delaying an output of the mirror control circuit by a third delay time; And a clock driver for outputting a second internal clock by delaying an output of the reverse delay array to a fourth delay time.

The synchronous delay according to claim 1, wherein each delay time of the first to nth unit delay units of the forward delay array is equal to each delay time of the first to nth unit delay units of the reverse delay array. Mirror delay circuit.

The synchronous delay according to claim 1, wherein the delay time of the (i +1) unit delay unit of the forward delay array is larger than the delay time of the i unit delay unit (i is 1 to (n-1)). Mirror delay circuit.

4. The method of claim 1, wherein the delay times of the even-numbered unit delay units of the forward delay array are the same and the delay times of the odd-numbered unit delay units are the same, and the delay times of the even-numbered unit delay units are the same. A synchronous mirror delay circuit, characterized in that greater than the delay time.

The synchronous delay according to claim 1, wherein the delay time of the (i +1) unit delay unit of the reverse delay array is larger than the delay time of the i unit delay unit (i is 1 to (n-1)). Mirror delay circuit.

2. The method of claim 1, wherein the delay times of the even-numbered unit delay units of the reverse delay array are the same and the delay times of the odd-numbered unit delay units are the same, and the delay times of the even-numbered unit delay units are the same. A synchronous mirror delay circuit, characterized in that greater than the delay time.

The synchronous mirror delay circuit of claim 1, wherein the second delay time is a sum of the first delay time and the fourth delay time.

The synchronous mirror delay circuit of claim 1, wherein the third delay time is a time obtained by subtracting the second delay time from an integer multiple of a period of the first internal clock.

※ Note: The disclosure is based on the initial application.