KR940023021A - Clock signal selector of dual clock system - Google Patents

Abstract

The present invention relates to a clock signal selection device for switching clock signals in a dual clock system, and an object thereof is provided. The present invention provides a control signal supply means for outputting a first control signal required for selecting a clock signal, register means for registering the first control signal to a clock signal to be selected, and a signal related to a clock signal to be selected among the first control signals. In response to outputting a signal capable of effectively selecting a clock signal, and outputting a signal incapable of selecting a clock signal in response to a signal related to a clock signal that is not to be selected, and simultaneously outputting such a signal. And control means for outputting a second control signal for controlling the means, and selection output means for selectively outputting only a clock signal to be selected by appropriately combining the signal output from the control means and the clock signal. Even if the clock signal in use is damaged and the function is lost, the function of the system can be restored immediately by automatically switching to the remaining one clock signal.

Description

Clock signal selector of dual clock system

Since this is an open matter, no full text was included.

1 is a block diagram showing the configuration of a clock signal selection device according to the present invention, FIG. 2 is a block diagram showing an embodiment of each synchronization unit shown in FIG. 1, and FIG. 4 is a timing diagram of each input / output signal of the apparatus shown in FIG. 1. FIG.

Claims (13)

A clock signal selection apparatus of a dual clock system which alternately outputs one clock signal of two clock signals of the same asynchronous frequency supplied from a dual clock system using a clock selection signal, wherein the clock signal is responsive to the clock selection signal. A control signal supply means for outputting a predetermined first control signal required for selection of, a synchronization means for synchronizing and outputting the first control signal to a clock signal to be selected, and among the first control signals applied by the synchronization means. Outputting a signal capable of effectively selecting the clock signal in response to a signal related to a clock signal to be selected, and outputting a signal incapable of effectively selecting the clock signal in response to a signal related to a clock signal not to be selected; Outputting a predetermined second control signal for controlling the synchronization means to enable such signal output at the same time And a selection output means for selectively outputting only a clock signal to be selected by appropriately combining the signal output from the control means and the clock signal. 2. The clock signal of a dual clock system according to claim 1, wherein the control signal supplying means has a buffer and an inverter for inputting the clock selection signal and outputting the same and inverted values as the clock signal, respectively. Selector. The apparatus of claim 1, wherein the synchronizing means comprises a separate synchronizing unit associated with each of the first control signals provided from the control signal supplying means. 4. The synchronizing unit according to claim 3, wherein the synchronization unit uses the inverted signal of the clock signal supplied from the dual clock system as a clock pulse, the second control signal as a clear signal, and the first control signal and its inverted signal as inputs. A logical multiplication device for performing a logical multiplication by combining the first flip-flop and the two outputs of the first flip-flop with the first control signal, and the clock pulse is the same signal as the first flip-flop, and the second control signal is And a second flip-flop for outputting the first control signal synchronized with a clock signal to be selected by using the output of the logical product as an input of a clear signal. 5. The apparatus of claim 4, wherein the first flip flop is a JK flip flop. 5. The apparatus of claim 4, wherein the second flip flop is a JK flip flop. The clock signal selection device of claim 4, wherein the logical multiplication device comprises at least two. 4. The clock signal selection apparatus of claim 3, wherein the control means includes a separate control unit associated with each synchronization unit of the synchronization unit. 9. The control unit according to claim 8, wherein the control unit for outputting a signal capable of effectively selecting the clock signal from among the control units of the clock means sets the inverted output of the associated gibber as a clear signal to supply the clock signal supplied from the double clock system. A shift register for outputting a signal capable of validly selecting the clock signal by delaying a predetermined clock from the time point at which the clear signal is applied, using the inverted signal as a clock pulse and using a constant DC power supply as a serial input; and the shift register The second control unit is further configured to control the second control unit to output a signal from which the other control unit cannot effectively select the clock signal by using a signal related to a clock signal to be selected from one signal and the first control signal. In the dual clock system, characterized in that it comprises a negative logic element provided to the synchronization unit Clock signal selector. The control unit of claim 9, wherein the control unit for outputting a signal in which the clock signal cannot be effectively selected from the control unit of the control unit sets the inverted output of the synchronizing unit to be a clear signal of the clock signal supplied from the double clock system. A shift register for outputting a signal in which the inverted signal is a clock pulse and a constant DC power supply is a serial input and outputs a signal in which the clock signal cannot be effectively selected at the time when the clear signal is applied; and is output from the shift register. A second control signal for controlling the other control unit to output a signal capable of effectively selecting the clock signal using a signal related to a clock signal not to be selected between one signal and the first control signal; Clock signal of dual clock system, characterized in that it has negative logic elements provided at base Selection device. The method of claim 1, wherein the second control signal is a signal whose value is changed as soon as the value of the clock selection signal is changed in response to the change of the value of the clock selection signal and the signal is changed by a predetermined clock delay. Clock signal selector of dual clock system. 10. The apparatus of claim 8, wherein the selection output means outputs a clock signal by performing a logical sum of a logic element which combines the signals provided by the separate control unit and the clock signal, respectively, and the output of the logical AND elements. Clock signal selection device of a dual clock system, characterized in that it comprises a logic element. The clock signal of claim 12, wherein one of the logic multiplying elements of the logic devices outputs the non-selected clock signal that is previously output until the output value of the associated synchronization unit changes. And a signal is outputted from the time when the output insertion of the control unit is changed. ※ Note: The disclosure is based on the initial application.