KR970055549A - Synchronous Counter Circuit - Google Patents
Synchronous Counter Circuit Download PDFInfo
- Publication number
- KR970055549A KR970055549A KR1019950067870A KR19950067870A KR970055549A KR 970055549 A KR970055549 A KR 970055549A KR 1019950067870 A KR1019950067870 A KR 1019950067870A KR 19950067870 A KR19950067870 A KR 19950067870A KR 970055549 A KR970055549 A KR 970055549A
- Authority
- KR
- South Korea
- Prior art keywords
- inputting
- count data
- frequency
- output
- counter circuit
- Prior art date
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- Synchronisation In Digital Transmission Systems (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
카운터 회로Counter circuit
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
카운터 인에이블 클럭 주파수의 변화에 따라 출력 주파수가 자동으로 변환되는 동기식 카운터회로를 제공한다.Counter Enable Provides a synchronous counter circuit that automatically converts an output frequency in response to a change in clock frequency.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
동기식 카운터회로가 출력주파수의 논리 주기를 설정하기 위한 제1카운트데이타 및 제2카운트데이타를 발생하는 수단과, 제1 및 제2카운트데이타들을입력하며 출력주파수의 논리에 의해 카운트데이타를 선택 출력하는 수단과, 중간주파수를 카운트 인에이블 펄스로 입력하며 선택수단의 출력을 데이타로 입력하고 캐리 출력신호를 로드신호로 입력하며 시스템 클럭에 의해 로드한 카운트데이타를 카운트하는 수단과, 출력주파수 및 카운트수단의 캐리출력신호를 배타적 논리합하여 출력하는 수단과, 배타적 논리합신호를 시스템 클럭에 동기시켜 출력주파수를 발생하는 수단으로 구성됨.Means for generating first count data and second count data for setting a logic period of the output frequency, the synchronous counter circuit inputting the first and second count data, and selectively outputting count data by logic of the output frequency Means, inputting an intermediate frequency as a count enable pulse, inputting the output of the selection means as data, inputting a carry output signal as a load signal, counting count data loaded by the system clock, output frequency and counting means Means for outputting an exclusive OR of the carry output signal of a signal, and means for generating an output frequency in synchronization with the system clock.
4. 발명의 중요한 용도.4. Important uses of the invention.
동기식 카운터회로 구현시 분주하고자 하는 중간주파수가 상황에 따라 변화되어도 수정없이 자동으로 출력주파수를 변화시킬 수 있다.When the synchronous counter circuit is implemented, the output frequency can be automatically changed without modification even if the intermediate frequency to be divided varies depending on the situation.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따른 카운터회로의 구성을 도시한 도면.2 is a diagram showing a configuration of a counter circuit according to the present invention.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950067870A KR970055549A (en) | 1995-12-30 | 1995-12-30 | Synchronous Counter Circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950067870A KR970055549A (en) | 1995-12-30 | 1995-12-30 | Synchronous Counter Circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR970055549A true KR970055549A (en) | 1997-07-31 |
Family
ID=66638428
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950067870A KR970055549A (en) | 1995-12-30 | 1995-12-30 | Synchronous Counter Circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970055549A (en) |
-
1995
- 1995-12-30 KR KR1019950067870A patent/KR970055549A/en not_active Application Discontinuation
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |