JPS6379123A - Clock distribution circuit - Google Patents

Abstract

PURPOSE:To reduce the skew regardless of the cycle of a selection clock by supplying clocks independently to the logic units from a system which distributes the clocks of different cycles. CONSTITUTION:The oscillators 11 and 12 supply clock signals of different cycles to clock distribution units 13 and 14. The logic units 15-1-15-n are connected to the units 13 and 14 respectively. The clocks produced by the oscillator 11 or 12 are selected by the clock drivers 16 provided in the units 15-1-15-n. Then the skew control is carried out for each clock distribution system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock distribution circuit, and more particularly to a lock distribution circuit that is preferably applied to a computer system.

[Conventional technology]

Conventionally, this type of clock distribution circuit has been constructed as shown in FIG. In the figure, oscillators 1.2 output clock signals having different periods.

A clock selection signal supplied from a clock selection terminal 4 to the switching circuit 3 selects one of the oscillators 1.2, and the output of the selected oscillator is input to the clock distribution unit 5. This clock distribution unit 5 has a function of adjusting clock skew between the logic units 6-1 to 5-n and various control functions.

The clock output from the clock distribution unit 5 is manually input to the clock driver buffer of each logic unit 6-1 to 5-n. Clock signals are distributed from these clock driver buffers to each flip-flop 8 within the unit. Further, one of the outputs of the clock driver buffer is connected to the waveform observation terminal 9.

Adjustment of the clock skew in such a lock distribution circuit is performed by observing the waveform appearing at the waveform observation terminal 9 of each logic unit with an oscilloscope, and adjusting it by the clock skew adjustment function using the variable delay element in the clock distribution unit 5. be done.

[Problems to be Solved by the Invention] In the conventional clock distribution circuit described above, skinny adjustment is performed by selecting one of the oscillators 1.2.
The drawback is that the clock skew increases when switching to the other oscillator. This is because the delay time of the propagation system consisting of the cable, driver gate, and delay element 0 from point A to point B in FIG. 2 varies depending on the period of the propagating signal.

Therefore, it is an object of the present invention to provide a system that can switch between multiple types of clocks with different periods, so that clock skew is small no matter which clock distribution system is selected from among a plurality of clock distribution systems that distribute clock signals with different clock periods. An object of the present invention is to provide a clock distribution circuit that can provide a system with small clock skew even when applied to a computer system.

[Means for solving problems]

The clock distribution circuit of the present invention includes a plurality of clock distribution systems each outputting a clock signal having a different cycle and each having a variable delay element, each of which is individually connected to each of the plurality of clock distribution systems, In addition, each clock distribution system is capable of selecting one of the clock distribution systems, and is provided with a logic unit that distributes the clock output of the selected clock distribution system.

Therefore, a plurality of clock distribution systems that distribute clock signals each having a different clock cycle are distributed to each logic unit separately, and a clock distribution system that outputs a clock signal with a lock cycle required within the logic unit is selected. Since the configuration is such that the skew can be adjusted individually, the clock skew can be kept small no matter which clock distribution system is selected.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a clock distribution circuit according to the present invention.

Oscillators 11 and 12 that output clock signals with different periods are connected to separate clock distribution units 13.
．． 14. Clock distribution unit 13.
14 has a variable delay element for skew adjustment inside,
It is connected to the clock driver 16 of each logic unit 15-1 to 15-n so as to output a clock signal.

The oscillator 11 and the clock distribution unit 13 constitute a first clock distribution system, and the oscillator 12 and the clock distribution unit 14 constitute a second clock distribution system. The first clock distribution system and the second clock distribution system distribute clock signals having different periods.

The clock drivers 16 in the logic units 15-1 to 15-n are two clock drivers distributed by the clock distribution units 13 and 14 on the oscillators 11 and 12 side (distributed from the first and second distribution systems). The flip-flop 18 in the unit receives two clock signals with different periods through the cable, selects one of the clocks by the clock selection signal supplied to the clock selection terminal 17, and selects one of the clocks.
Furthermore, a clock signal is output to the waveform observation terminal 19.

Next, when adjusting the clock skew, each logical unit 15-
A clock selection signal is supplied to the clock selection terminals 17 of 1 to 15-n to select the clock signal of the oscillator 11, and while observing the waveform appearing at each waveform observation terminal 19 with an oscilloscope, the variable delay element in the clock distribution unit 13 is selected. Adjust the skew by etc. Next, the oscillator 12 is selected by switching the polarity selection signal to the clock selection terminal 17, and the skew is adjusted using the variable delay element of the clock distribution unit 14 while observing the waveform appearing at each waveform viewing terminal 11 with an oscilloscope. I do.

In this way, the skinny up to the input point B of the clock driver 16 in the logic units 15-1 to 15-n can be completely adjusted no matter which oscillator among the oscillators 11.12 is selected. Since the clock distribution units 13.14 are individually distributed to each logic unit) 15-1 to 15-n, each logic unit) 15-1 to 15-n is
rl) Regardless of which oscillator output the clock driver 16 selects by switching between the outputs of the oscillators 11 and 12,
Clock skinny can be made smaller. Therefore, when applied to a computer system that switches between two types of clock signals with different periods, it is possible to select a system with a small clock skew.

In this embodiment, as described above, when all the logic units l-15-1 to l-15-n select the clock signal of the oscillator 11, that is, the first clock distribution system,
In addition to being applicable to the case where the clock signal of the oscillator 12, that is, the second clock distribution system is selected, or the case where the clock signal of the other oscillator is selected by switching the selection, the present invention is also applicable to the following cases. That is, some of the logic units 15-1 to 15-n select the clock signal of the oscillator 11, and the others supply another clock selection signal to the corresponding clock selection terminal 17, thereby selecting the clock signal of the oscillator 12. You can also select a signal. In this case as well, the same effects as described above can be obtained.

Further, in this embodiment, two clock distribution systems are used, but the present invention is not limited to this, and a plurality of clock distribution systems that distribute clock signals each having a different clock period may be used. , Needless to say, in this case as well, the configuration is similar to that described above, such as being individually distributed to each logical unit.

〔Effect of the invention〕

As described above, by using the present invention, a plurality of clock distribution systems that distribute clock signals having different clock periods from each other can be separately distributed to each logic unit, and clock signals having lock periods as required within the logic unit can be distributed. Since the configuration is such that clock skew can be adjusted individually by selecting a clock distribution system, clock skew can be reduced regardless of which clock distribution system, that is, which clock signal with a different period is selected. . Therefore, when applied to a computer system that switches between multiple types of clock signals with different clock cycles, it is possible to provide a system with small clock skew.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a clock distribution circuit according to the present invention, and FIG. 2 is a block diagram showing an embodiment of a conventional clock distribution circuit. 11.12... Oscillator, 13.14... Clock distribution unit, 15-
1 to 15-n...Logic unit, 16...
...Clock driver, 17...Clock selection terminal. Applicant: NEC Corporation Representative

Claims (1)

[Scope of Claims] 1. A plurality of clock distribution systems each outputting a clock signal having a different cycle and each having a variable delay element, each of which is individually connected to each of the plurality of clock distribution systems, Each clock distribution system can be selected, and it is equipped with a logic unit that distributes the clock output of the selected clock distribution system, so that clock skew adjustment can be performed individually for the corresponding clock signal for each clock distribution system. A clock distribution circuit characterized in that it is configured as follows. 2. A plurality of oscillators that output clock signals with different periods from each other, and a plurality of oscillators that are provided corresponding to each of the plurality of oscillators, are supplied with the output of the corresponding oscillator, and each has a variable delay element. a clock distribution unit, each of which is individually connected to each of the plurality of clock distribution units, each of which can select any one of the clock distribution units, and logic that distributes the clock output from the selected clock distribution unit. 2. The clock distribution circuit according to claim 1, wherein the clock distribution circuit is configured such that clock skew adjustment can be performed individually for each clock signal corresponding to each clock distribution unit.