JPH06163827A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To contrive a reduction in a current consumption and the improvement of the reliability of a semiconductor integrated circuit by a method wherein the integrated circuit is provided with a frequency dividing circuit, which divides a block signal inputted from the outside and distributes the divided block signals to each circuit block, and a multiplying circuit, which reproduces the clock signal having a frequency previous to the frequency division in each circuit block. CONSTITUTION:A clock signal CLOCK inputted from the outside is inputted in a 1/2 frequency divider 16, is divided into clock signals having a 1/2 frequency and thereafter, the divided clock signals are distributed to each circuit block via a buffer 12 and a clock wiring 14. Each circuit block 10 is provided with a multiplying circuit 18 for multiplying the 1/2 frequency of the inputted block signal to a frequency, which is two times higher than the 1/2 frequency, and the frequency of the clock signal distributed to each circuit block is multiplied to a frequency, which is two times higher than the 1/2 frequency. Thereby, the inputted clock signal CLOCK is restored and the circuit blocks are respectively operated in synchronization with each other according to this restored block signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of circuit blocks which operate in synchronization with each other by a clock signal input from the outside.

[0002]

2. Description of the Related Art In constructing a semiconductor integrated circuit, a large number of circuit blocks satisfying a certain circuit function are prepared, and those circuit blocks are combined or newly designed with those circuit blocks. A method of combining blocks to form a semiconductor integrated circuit satisfying a desired function is often used. In this way, a plurality of circuit blocks incorporated in one semiconductor integrated circuit are usually input from the outside. It is configured to operate in synchronization with the clock signal.

FIG. 4 is a schematic diagram showing a semiconductor integrated circuit composed of a plurality of circuit blocks as described above. This semiconductor integrated circuit is composed of a large number of circuit blocks 10. A clock signal CLOCK is input from the outside, and this clock signal CLOCK is transmitted to each circuit block 10 via a buffer 12 and a clock wiring 14. To be done. In each circuit block 10, the circuit operates in synchronization with the transmitted clock signal CLOCK.

[0004]

In the semiconductor integrated circuit having the above-mentioned structure, the clock wiring 14 has a long overall length and therefore has a considerably large capacitance. Therefore, a large charging current and a large discharging current flow, which increases the current consumption of the semiconductor integrated circuit. In addition, noise is generated by this charging current and discharging current, the potential of the power supply line and the ground line fluctuates,
This may cause a malfunction or the like, and may impair the reliability of the semiconductor integrated circuit.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor integrated circuit in which an average charging / discharging current per unit time is reduced, thereby reducing power consumption and improving reliability. To do.

[0006]

A semiconductor integrated circuit of the present invention that achieves the above object is a semiconductor integrated circuit having a plurality of circuit blocks that operate in synchronization with each other in response to a clock signal input from the outside. A frequency dividing circuit that receives the divided clock signal, divides the divided clock signal, and divides the divided clock signal into the plurality of circuit blocks; and a dividing circuit that divides the plurality of circuit blocks. And a plurality of multiplier circuits for returning the generated clock signal to a clock signal having a repetition frequency before frequency division.

[0007]

According to the semiconductor integrated circuit of the present invention, the clock signal inputted from the outside is divided and distributed to each circuit block, and the frequency is returned to the original frequency even when multiplied by each circuit block. Therefore, the number of times of charging / discharging per unit time is reduced, and the current consumption is reduced accordingly. In addition, the probability of malfunctions is reduced, and the reliability is also improved.

[0008]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a schematic diagram showing an embodiment of the semiconductor integrated circuit of the present invention. Elements corresponding to those of the conventional semiconductor integrated circuit shown in FIG. 4 are designated by the same reference numerals as those shown in FIG. 4 and only different points will be described.

Clock signal CLOC input from the outside
K is input to the 1/2 frequency divider 16 and divided into a clock signal having a frequency of 1/2, and then distributed to each circuit block via the buffer 12 and the clock wiring 14. Each circuit block 10 is provided with a multiplication circuit 18 that multiplies the input clock signal to double the frequency, and the clock signal distributed to each circuit block is multiplied to double the frequency. As a result, the input clock signal CL
The OCK is restored, and each circuit block operates in synchronization with each other according to the restored clock signal.

FIG. 2 is a diagram showing a configuration example of the frequency divider 16 and a timing chart thereof. This divider 16
Is composed of a D-type flip-flop, the input clock signal a is divided by returning the inverted output to the input,
The clock signal b is output. FIG. 3 is a diagram showing a configuration example of the multiplier 18 and a timing chart thereof.

The inputted clock signal b is branched into two, one of which is directly inputted and the other of which is inputted to the exclusive OR (XOR) gate 182 through the delay buffer 181, whereby the pulse waveform signal c is obtained. Is generated. The pulse waveform signal c is input to the one-shot circuit 183, and the clock signal d having a frequency twice that of the clock signal b input to the multiplier 18 is generated.

As described above, in the present embodiment, the clock signal input from the outside is divided into halves and distributed to each circuit block 10, and each circuit block 10 doubles the frequency. Since the configuration is such that the original clock signal is restored, the number of times of charging / discharging the clock wiring 14 per unit time is reduced to 1/2, and the current consumption is reduced and the reliability is improved accordingly.

The above embodiment is an example in which the frequency is divided into 1/2 and the frequency is multiplied by 2. However, the present invention is not limited to this. For example, the frequency is divided into 1/4 and the frequency is multiplied by 4. Such a configuration may be adopted.

[0014]

As described above, the semiconductor integrated circuit of the present invention divides a clock signal input from the outside and distributes the divided clock signal to each circuit block. Since it is configured to multiply so as to reproduce, the current consumption can be reduced and the reliability can be improved.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is a diagram showing a configuration example of a frequency divider and a timing chart thereof.

FIG. 3 is a diagram showing a configuration example of a multiplier and a timing chart thereof.

FIG. 4 is a schematic diagram showing a semiconductor integrated circuit including a plurality of circuit blocks.

[Explanation of symbols]

 10 circuit blocks 12 buffer 14 clock wiring 16 frequency divider 18 multiplier 181 delay buffer 182 exclusive OR gate 183 one-shot circuit

Claims (1)

[Claims] 1. In a semiconductor integrated circuit having a plurality of circuit blocks that operate in synchronization with each other by a clock signal input from the outside, the clock signal input from the outside is input, the clock signal is divided, and the divided clock signal is divided. A frequency divider circuit that distributes the divided clock signal to the plurality of circuit blocks, and the divided clock signal that is distributed to each of the plurality of circuit blocks is returned to a clock signal having a repetition frequency before the division. A semiconductor integrated circuit comprising a plurality of multiplication circuits.