JP3019049B2 - Clock control circuit and clock control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to clock distribution in a device connected to a bus line and receiving a clock from the bus line.

[0002]

2. Description of the Related Art A clock control circuit is provided in various devices, and is provided in a device by dividing a clock signal supplied from a connected bus line into a clock signal having an operating frequency of the device. This is a circuit for supplying a clock signal to each flip-flop circuit (hereinafter referred to as F / F).

Such a conventional clock control circuit is shown in FIG.
This will be described with reference to FIG.

This conventional clock control circuit includes a frequency divider 2
02, a distributor 203, and F / Fs 204 _{1 to} 204 _n .

The frequency divider 202 divides the frequency of the clock signal supplied from the bus line 201 into a signal of the operating frequency of the device and outputs the signal.

[0006] The distributor 203 distributes the clock signal divided by the frequency divider 202 into n clock signals.

[0007] The F / Fs 204 _{1 to} 204 _n
It operates by inputting each of the n clock signals distributed by. And F / F204 _n
Is connected to an output buffer (not shown), and its output signal is output to the outside via a bus line 201. Next, the operation of this conventional clock control circuit will be described.

The clock signal supplied from the bus line 201 is first supplied to a frequency divider 202 in the device to divide the frequency into the operating frequency of the device. And all F /
F204 is supplied to the ₁ to 204 _n.

At this time, the clock signal supplied from the bus line 201 includes a delay generated when the frequency is divided into an operating frequency in the frequency divider 202 and a delay generated when the frequency is divided by the divider 203. Will be included.

An F / F 20 for distributing a clock signal
4 _1-204 wiring delay and _n number of come increased from the distributor 203 to the total route length is lengthened to the F / F 204 ₁ to 204 _n also increases. Further, F / F204 _{1 to} 20
As the number of 4 _n increases, the delay due to the load on the F / Fs 204 _{1 to} 204 _n itself also increases. Therefore, when the number of F / Fs 204 _{1 to} 204 _n for supplying a clock signal is large, the F / Fs 204 _{1 to} 204 _n are divided into several systems in consideration of the respective functions and layout conditions. It has been practiced to reduce these delays to some extent by performing distribution. At that time, the clock signal supplied from the bus line is first supplied to the distributor to be divided into clock signals for each system. Then, the clock signal divided for each system is supplied to each frequency divider under the clock signal, and is divided into the operating frequency of the device.
The frequency-divided clock signal is further supplied to each F / F connected under the divider through the distributor.

In this conventional clock distribution method, even for an F / F whose logic is closed in the device, an F / F connected to a signal whose logic goes out (ie, connected to an output buffer). Similarly, the clock signal is supplied to the F / F). Therefore, a clock signal with a delay caused by the circuit itself in the frequency divider or the divider, a delay due to the load of each F / F, and a delay due to the wiring to each F / F is equally supplied to all the F / Fs. As a result, with respect to the clock signal supplied from the bus line, not only the F / F whose logic is closed in the device but also the F / F connected to the output buffer are all equally delayed in the data determination timing. Would.

In particular, if the delay between the output data output to the outside via the bus line and the clock signal on the bus line increases, the output data cannot be transmitted normally.

[0013]

In the conventional clock control circuit described above, the delay between the clock signal on the bus line and the output data to be output to the outside increases, and the output data is not transmitted normally. There was a problem.

An object of the present invention is to provide a clock control circuit capable of minimizing a delay between a clock signal on a bus line and output data output to the outside.

[0015]

In order to achieve the above object, the present invention provides a clock control system for supplying a clock signal supplied from a connected bus line to each flip-flop circuit provided in the device. A circuit for distributing a clock signal supplied from the bus line to a plurality of clock signals, and a circuit for distributing one of the clock signals distributed by the first distributor to the device. A frequency divider that divides the frequency of the clock signal into a clock signal having the same operating frequency, a second divider that distributes the clock signal divided by the frequency divider to a plurality of clock signals, and an output buffer connected to the bus line. The clock signal distributed by the first distributor is inputted to a clock input terminal, and the clock signal distributed by the second distributor is inputted to a hold terminal. It has a first the F / F to force a second the F / F for inputting a clock signal distributed by the second distributor to the clock input terminal.

In the clock control circuit according to the present invention, the clock supply system is first controlled by the second F / F in which the logic is closed in the device.
F and 2 of the first F / F connected to the output buffer.
It is divided into strains. Then, the clock signal supplied from the bus line is supplied to the first F / F without dividing the frequency,
For the second F / F, after dividing the frequency of the clock signal supplied from the bus line, the signal is supplied as a clock signal. Then, the clock signal after further frequency division is supplied to the first F / F as a hold signal. Therefore, the first F / F
In this case, even if the clock signal before frequency division is used as a clock, it is held by the clock signal after frequency division, so the same operation as operating with the clock signal after frequency division as the clock is used. It can be carried out.

Therefore, the delay between the clock signal on the bus line and the output data to the first F / F bus line can be minimized.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the clock control circuit of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a clock control circuit according to one embodiment of the present invention. In FIG. 1, the connections of the respective units are only those relating to the present embodiment, and other connections are omitted.

The clock control circuit according to the present embodiment includes a distributor 102, a frequency divider 103, F / Fs 104 _{1 to} 104 _n ,
It has a distributor 105 and F / Fs 106 _{1 to} 106 _n .

The distributor 102 divides the clock signal supplied from the bus line 101 into n + 1 signals and outputs the signal.

The frequency divider 103 divides one of the clock signals distributed by the distributor 102 into a signal having an operating frequency of the apparatus and outputs the signal.

The divider 105 divides the clock signal divided by the divider 103 into 2 × n signals and outputs it.

The F / Fs 106 _{1 to} 106 _n include a distributor 105
Of the clock signals distributed by the above are input.

The F / Fs 104 _{1 to} 104 _n correspond to the distributor 102
The clock signals output from the distributor 105 are input to the clock input terminal, and the n signals among the clock signals output from the distributor 105 are input to the hold input terminal. The F / Fs 104 _{1 to} 104 _n are connected to an output buffer (not shown), and the output signals are output to the outside via the bus line 101.

The F / F 104 used here
_{1 to} 104 _n and 106 _{1 to} 106 _n are all operated at the falling edge of the clock. Further, as for the F / Fs 104 _{1 to} 104 _n connected to the output buffer, the hold input terminals are at a low level (hereinafter referred to as L and L). ) Is held at that time.

Next, the operation of this embodiment will be described with reference to FIGS.

In the present embodiment, the connection to the bus line 101 is made.
Clock signal supplied from the bus line 101.
The signal is first input to the distributor 102 inside the device. Distribution
In the device 102, the clock supplied from the bus line 101 is used.
The frequency divider 103 and the F / F 104₁~ 1
04_nClock input terminals. Soshi
Therefore, the divider 103 receives the clock supplied from the distributor 102.
Divide the lock signal according to the operating frequency of the device,
The clock signal after the frequency division is supplied to the distributor 105.
The divider 105 receives the clock signal received from the frequency divider 103.
No. is distributed, and n are distributed to F / F106₁~ 106_nClock
Supply to the input terminal, and another n lines are ₁~ 104_n
Are supplied to the respective hold input terminals.

FIG. 2 is a timing chart for explaining the operation of the present embodiment.
A case where the clock signal supplied from 01 is frequency-divided by 2 in the frequency divider 103 will be described.

The clock signal A supplied from the bus line 101 passes through the divider 102, thereby delaying the circuit by the circuit of the divider 102 itself and the frequency divider 103 and F
/ F 104 ₁ -104 contains a delay due to the wiring for connecting to the _n becomes as the clock signal B.

The clock signal B is divided by two by the frequency divider 103, and then passes through the divider 105, whereby the delay of the circuit of the frequency divider 103 and the divider 105 itself and the delay of the divider 105 or F / F104 _1-
The clock signal C includes a delay caused by wiring when connecting to 104 _n and 106 _{1 to} 106 _n . In this manner, the clock signal C changes somewhat later than the clock signal B, and the clock signal B changes somewhat later than the clock signal A.

That is, of the F / Fs inputting the clock signals B and C as clocks, the F / Fs 106 ₁ to 10 operating using the clock signal C as a clock signal.
In the case of 6 _n , the decision time of the input data is delayed by the delay of the clock signal C from the clock signal A, like the signal D.

Here, the F / Fs 104 _{1 to} 104 _n operating using the clock signal B as the clock signal are the F / Fs 106 operating using the clock signal C as the clock signal.
_The clock changes at a half cycle compared to _{1 to} 106 _n . However, since the F / Fs 104 _{1 to} 104 _n operating with the clock signal B as the clock signal further input the clock signal C as the hold signal, the F / Fs 104 _{1 to} 104 _n are output once every two falling times of the clock signal B. Because of the hold state, there is a difference in the data determination timing due to the difference in delay between the clock signals B and C as compared with the F / Fs 106 _{1 to} 106 _n operating using the clock signal C as a clock signal. However, they are operating at the same clock cycle. Therefore, as shown by the signal E in FIG. 2, the timing is shifted as compared with the clock signal A to determine the data, but the amount of the timing shift is smaller as compared with the signal D.

[0034]

As described above, according to the present invention, when the clock signal is supplied from the bus line and the frequency is divided and used inside the device, the F / F whose logic is closed inside the device is used.
By dividing the clock distribution method between the F and the F / F connected to the output buffer, the difference between the clock signal on the bus line and the output data to the bus line of the F / F connected to the output buffer is obtained. This has the effect of minimizing the delay.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a clock control circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation of the clock control circuit of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a conventional clock control circuit.

[Explanation of symbols]

Reference Signs List 101 bus line 102 divider 103 divider 104 _{1 to} 104 _n flip-flop circuit (F / F) 105 divider 106 _{1 to} 106 _n flip-flop circuit (F / F) 201 bus line 202 divider 203 divider 204 _{1 to} 204 _n flip-flop circuit (F / F)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 1/10 G06F 1/12 G06F 13/42 H03K 3/02

Claims (6)

(57) [Claims] 1. A clock control circuit for supplying a clock signal supplied from a connected bus line to each flip-flop circuit provided in the device, wherein the clock signal supplied from the bus line is supplied to a plurality of clocks. A first divider for dividing the signal into a signal; a frequency divider for dividing one of the clock signals distributed by the first divider into a clock signal having an operating frequency of the device; A second divider for dividing the clock signal divided by the divider into a plurality of clock signals, and a clock input connected to the bus line via an output buffer for receiving the clock signal distributed by the first divider. A first flip-flop circuit for inputting the clock signal distributed by the second distributor to a terminal and inputting the clock signal to a hold terminal; Clock control circuit and a second flip-flop circuit for inputting a clock signal distributed to a clock input terminal by. 2. The clock control circuit according to claim 1, wherein said first and second flip-flop circuits operate at a falling edge of a clock signal input to a clock input terminal. 3. The clock control circuit according to claim 1, wherein said first and second flip-flop circuits operate at a rising edge of a clock signal input to a clock input terminal. 4. The clock control circuit according to claim 1, wherein the first flip-flop circuit holds an output state when a clock signal input to the hold input terminal is at a low level. 5. The clock control circuit according to claim 1, wherein the first flip-flop circuit holds an output state when a clock signal input to the hold input terminal is at a high level. 6. A clock control method for supplying a clock signal supplied from a connected bus line to each flip-flop circuit provided in the device, wherein the clock signal supplied from the bus line is supplied to a plurality of clocks. And distributing a part of the divided clock signal to a clock input terminal of a flip-flop circuit for outputting data to the bus line, and supplying one of the divided clock signals to the device. Dividing the signal into an operating frequency signal, dividing the divided signal into a plurality of signals, and outputting the divided signal to the hold input terminal of the flip-flop circuit for outputting data to the bus line and data to the bus line. A clock control method for supplying a clock output terminal of a flip-flop circuit that does not output a clock signal.