JPS63215212A - Pulse circuit - Google Patents

Abstract

PURPOSE:To easily obtain an optional delay time or an optional pulse width by providing a delay circuit network comprising plural delay circuits, a multiplexer circuit outputting one of plural delay outputs selectively and a logic circuit receiving the output of the multiplexer circuit and an input signal and outputting the result of logic operation. CONSTITUTION:In giving, e.g., a negative pulse 11 to a pulse input terminal 1, a retarded pulse 12 in response to the delay time of the delay circuit 2 is outputted at the output of the delay circuit 2. A delay pulse 15 being the sum of delay times of delay circuits 2-5 is outputted at the output of the delay circuit 5. Each delay pulse is inputted to the multiplexer 6, where one delay pulse is selected. The delay time and the input pulse to the pulse input terminal 1 are ORed by a logic circuit 7, from which a negative pulse having a wider pulse width than that of the input pulse is outputted. In this case, the output pulse width is the sum of the delay time of the delay pulse to the input pulse width. When the delay pulse 15 is selected similarly, an output pulse 19 is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Prior Art] The present invention relates to a pulse circuit, and particularly to a pulse circuit that obtains a pulse having an arbitrary delay time and pulse width from an input pulse.

[Conventional technology]

Conventionally, this type of pulse circuit is constituted by a logic circuit that performs an AND, OR or exclusive OR of an input signal and a delayed signal of this input signal via a single delay circuit.

FIG. 9 is a block diagram of a conventional circuit. The input pulse input to the pulse input terminal 1 is outputted as a delayed pulse by the delay circuit 92. The input pulse and the delayed pulse are ANDed,
The signal is input to a logical OR or exclusive OR logic circuit 7, and a pulse corresponding to the logic of the logic circuit 7 is outputted to an output terminal 8.

[Problem that the invention seeks to solve]

However, since the conventional pulse circuit described above uses a single delay circuit to perform the delay, there is a drawback that only a pulse having a single delay time or a single pulse width can be obtained. In particular, since the delay time of the delay circuit changes depending on the temperature or the wiring length at the time of mounting, there is a drawback that it is not easy to obtain a pulse with an arbitrary delay time or an arbitrary pulse width.

An object of the present invention is to provide a pulse circuit that can easily obtain an arbitrary delay time and an arbitrary pulse width by using a plurality of delay circuits and multiplexer circuits.

[Means for solving problems]

The pulse circuit of the present invention includes a delay circuit network consisting of a plurality of delay circuits that send out a plurality of delay outputs each having a different delay time from an input signal, and a plurality of delay outputs of this delay circuit network as inputs. The device includes a multiplexer circuit that selects and outputs one of the signals, and a logic circuit that receives the output of the multiplexer circuit and the input signal as input, and outputs the result of a logical operation.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In the figure, delay circuits 2, 3, 4 and 5 are connected in series to the pulse input terminal 1, and the respective outputs of the delay circuits 2, 3, 4 and 5 are connected to the respective data input terminals Do, Di, D2 of the multiplexer 6. and D3, the output terminal Y of the multiplexer is connected to the input terminal B of the logic circuit 7, the pulse input terminal 1 is connected to the input terminal A of the logic circuit 7, and the output terminal C of the logic circuit 7 is connected to the output terminal 8. It is connected to.

Further, the select terminals 9 and 10 are connected to the select terminals SO and SL of the multiplexer 6.

Next, in FIG. 1, the logic circuit 7 is an AND circuit (AND
) is explained below.

FIG. 2 shows a time chart when the input is a negative pulse. In this case, a negative pulse 11 is input to the pulse input terminal 1.
When input, the delay pulse 12 corresponding to the delay time of delay circuit 2 is output to the output of delay circuit 2, and the delay pulse 13 which is the sum of the delay times of delay circuits 2 and 3 is output to the output of delay circuit 3. However, the output of the delay circuit 4 is connected to the delay circuit 2.
．． A delay pulse 14 in which the delay times of delay circuits 2, 3, 4, and 5 are also added is outputted, and a delay pulse 15 in which the delay times of delay circuits 2, 3, 4, and 5 are added is outputted at the output of the delay circuit 5. Each delayed pulse is input to multiplexer 6, and one delayed pulse is selected by select signals at select terminals 9 and 10. The delayed pulse selected by the multiplexer 6 and the input pulse at the pulse input terminal 1 are ANDed by the logic circuit 7, and a negative pulse having a wider pulse width than the input pulse is output. The output pulse width at this time is approximately equal to the input pulse width plus the delay time of the delayed pulse.

That is, when the multiplexer 6 selects the delayed pulse 12,
An output pulse 16 is outputted to the output terminal 8 by logical product with the input pulse 11. Similarly, when delay pulse 13 is selected, output pulse 17 is output, when delay pulse 14 is selected, output pulse 18 is output, and when delay pulse 15 is selected, output pulse 19 is output.

FIG. 3 shows a time chart when the input is a positive pulse. In this case, a positive pulse 21 is input to the pulse input terminal 1.
is input, the delay pulse 22 is output to the output of the delay circuit 2, the delay pulse 23 is output to the output of the delay circuit 3, the delay pulse 24 is output to the output of the delay circuit 4, and the delay pulse 24 is output to the output of the delay circuit 5. A delayed pulse 25 is output at the output. One delayed pulse is selected by the multiplexer 6, and the input pulse and this delayed pulse are ANDed by the logic circuit 7 to output a positive pulse having a narrower pulse width than the input pulse. The output-pulse width at this time is approximately the value obtained by subtracting the delay time of the delayed pulse from the input pulse width. That is, when the delayed pulse 22 is selected by the multiplexer 6, an output pulse 26 is outputted to the output terminal 8 by ANDing it with the input pulse 21. Similarly, when delay pulse 23 is selected, output pulse 27 is output, when delay pulse 24 is selected, output pulse 28 is output, and when delay pulse 25 is selected, output pulse 29 is output.

Next, the operation when the logic circuit 7 in FIG. 1 is a logical sum (OR) circuit will be described.

FIG. 4 shows a time chart when the input is a negative pulse. In this case, the negative pulse 31 is applied to the pulse input terminal 1.
When input, the outputs of delay circuits 2.3.4 and 5 are as follows.
Delayed pulses 32°, 33, 34 and 35 are output, respectively. One delayed pulse is selected in the multiplexer 6, and the input pulse 31 and this delayed pulse are logically summed by the logic circuit 7 to output a pulse narrower than the input pulse width.

The output pulse width at this time is approximately the value obtained by subtracting the delay time of the delayed pulse from the pulse width. That is, when the delayed pulse 32 is selected by the multiplexer 6, an output pulse 36 is outputted to the output terminal 8 by logical sum with the input pulse.

Similarly, when delay pulse 33 is selected, output pulse 3
When delay pulse 34 is selected, output pulse 38 is output, and when delay pulse 35 is selected, output pulse 39 is output.

FIG. 5 shows a time chart when the input is a positive pulse. In this case, a positive pulse 41 is applied to pulse input terminal 1.
When input, delay pulses 42°43, 44 and 45 are outputted from the outputs of delay circuits 2, 3°4 and 5, respectively. One delayed pulse is selected in the multiplexer 6, and the input pulse 41 and this delayed pulse are connected to the logic circuit 7.
A positive pulse wider than the input pulse width is output by the logical sum of . The output pulse width at this time is approximately the sum of the input pulse width and the delay time of the delayed pulse.

That is, when the delayed pulse 42 is selected by the multiplexer 6, an output pulse 46 is outputted to the output terminal 8 due to the logical sum with the input pulse 41. Similarly, when delay pulse 43 is selected, output pulse 47 is output, when delay pulse 44 is selected, output pulse 48 is output, and when delay pulse 45 is selected, output pulse 48 is output, and delay pulse 45 is output.
When is selected, four output pulses are output.

Next, in FIG. 1, the logic circuit 7 performs an exclusive OR (Ex
The operation in the case of the exclusive OR) circuit will be explained.

FIG. 6 shows a time chart when the input is negative and pulse. In this case, the negative pulse 51 is applied to the pulse input terminal 1.
When input, the outputs of delay circuits 2, 3.4 and 5 are as follows.
Delayed pulses 52, 53, 54 and 55 are output, respectively. One delayed pulse is selected in the multiplexer 6, and the input pulse 51 and this delayed pulse are connected to the logic circuit 7.
When the signal levels of the input pulse and the delayed pulse are different, a positive output pulse is output by the exclusive OR of the input pulse and the delayed pulse.

The output pulse width at this time is approximately the delay time of the delayed pulse. That is, when the delayed pulse 52 is selected by the multiplexer 6, an output pulse 56 is outputted to the output terminal 8 by exclusive ORing with the input pulse. Similarly, delay pulse 5
When 3 is selected, output pulse 57 is output, when delay pulse 54 is selected, output pulse 58 is output, and when delay pulse 54 is selected, 5 output pulses are output.

FIG. 7 shows a time chart when the input is a positive pulse. In this case, when a positive pulse 61 is input to the pulse input terminal, delay pulses 62, 63, 64 and 65 are output to delay circuits 2, 3.4 and 5, respectively. One delayed pulse is selected in the multiplexer 6, and the input pulse 61 and this delayed pulse are exclusive ORed in the logic circuit 7, so that when the signal levels of the input pulse and the delayed pulse are different, a positive output pulse is output. do. The output pulse width at this time becomes the delay time of the delay pulse. That is, when the delayed pulse 62 is selected by the multiplexer 6, an output pulse 66 is outputted to the output terminal 8 by exclusive ORing with the input pulse. Similarly, when delay pulse 63 is selected, output pulse 67 is output, when delay pulse 64 is selected, output pulse 68 is output, and when delay pulse 65 is selected, output pulse 69 is output.

FIG. 8 is a block diagram of another embodiment of the invention, in which delay circuits 82, 83, 84 and 85 are connected in parallel between the pulse input terminal 1 and the respective data input terminal of the multiplexer 6. The output terminal Y of the multiplexer 6 and the pulse input terminal 1 are connected to the respective input terminals A and B of the logic circuit 7, and the output terminal C of the logic circuit 7 is connected to the output terminal 8. Select terminals 7 and 8 are connected to select terminals SO and SL of multiplexer 6, respectively, and delay circuits 82, 83, 84 and 8
Select 5 delayed pulses. This embodiment is the same as the case of FIG. 1 except that the delay circuit is connected in parallel between the input terminal and the multiplexer.

In both of the above two embodiments, four delay circuits are connected in series.
Although the case where the delay circuits and the delay circuits are connected in parallel has been described, it is clear that a similar configuration can be achieved by using two or more delay circuits.

〔Effect of the invention〕

As explained above, the present invention connects a plurality of delay circuits that delay an input signal in series or parallel, etc. to create a plurality of delay outputs with different delay times, and a multiplexer circuit that selects the delayed output, and By having a logic circuit that obtains an AND, OR, or exclusive OR of the output of the multiplexer circuit and the output of the multiplexer circuit, there is an effect that a pulse with an arbitrary delay time or an arbitrary pulse width can be easily obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG.
4, 5, 6 and 7 are time charts of FIG. 1, FIG. 8 is a block diagram of another embodiment of the present invention, and FIG. 9 is a block diagram of a conventional pulse circuit. It is a diagram. 1... Input terminal, 2-5.82-85.92... Delay circuit, 6... Multiplexer, 7... Logic circuit,
8...Output terminal, 9.10...Select terminal, 11
, 21. 31, 41, 51, 61... input pulse, 1
6-19.26-29.36-39.46. ~49°5
6-59.66-69...Output pulse. Kaya 1 time $2 1!1 2/ -----1"-L 2S-"-111"-L $3 Figure J5--1--I Recruitment 4 times 4t --------L 45- ---- - L 茅 5 times 55-111-------L f A Figure 61'''-1111''''''''-' ″-one-ts-”--
------ $7WJ

Claims (1)

[Claims] A delay circuit network consisting of a plurality of delay circuits that send out a plurality of delay outputs each having a different delay time from an input signal, and a multiplexer circuit that receives the plurality of delay outputs of this delay circuit network and selects and outputs one of them. and a logic circuit that receives the output of the multiplexer circuit and the input signal and outputs the result of a logical operation.