JPS5911434A - Digital input circuit - Google Patents

Abstract

PURPOSE:To judge accurately a switching element to be turned on, by providing a shift register close to plural switches and an FET for using three wirings connecting an input/output circuit and each circuit. CONSTITUTION:When a load signal (a) is transmitted from an input/output circuit I/O based on the operation of a processor CPU, an ''L'' is set to the 1st stage S0, an ''H'' is set to other stages S1-Sn, the ''L'' of the 1st stage S0 is shifted sequentially to the next stage S1 and succeeding according to a clock pulse (b) transmitted from the circuit I/O succeedingly, and outputs (c)-(g) of the stages S0-Sn go successively to ''L''. For example, if only the switch K2 is turned on, an output signal (h) goes to ''L'' corresponding to the 2nd pulse of the pulse (b) and is given to the CPU via the circuit I/O. As a result, the CPU judges the switch K2 to be turned on from the relation of synchronism between the pulse (b) and the signal (h) and the required number of wirings is taken as three.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a digital input circuit that provides the states of a plurality of switching elements as input to a processor via an input/output circuit.

Figures 1 and 2 are configuration diagrams showing conventional examples.
In the figure, an input/output circuit I 10 connected to a processor CPU is connected to a switch as a switching element.
The transistors Q, which are turned on according to f Kl to Kn and the input IN, are individually connected, but in FIG. 2, the switches 1. ~Kn are connected in a matrix, the input/output circuit I10 sends out scanning signals Ssl to Sml to the vertical bus line at individual timings, and the corresponding output signals of the horizontal bus line are sent. 5olxSon is received by the input/output circuit I10, and the processor CPU determines which of the switches 1 to Kn is turned on based on the synchronization relationship between the scanning signals 5III to Ss' and the output signals Sol to Son. ing.

However, in the configurations of FIGS. 1 and 2, the amount of wiring between the switch and the input/output circuit I10 increases depending on the number of ~Kn, and in particular, the amount of wiring between the switch and the input/output circuit I10 increases depending on the number of ~Kn or the transistor Q. If the distance from circuit I10 is large,
The disadvantage is that the wire material cost and the wiring man-hour cost are high.

Furthermore, in FIG. 2, if three switches are turned on at the same time, this results in a drawback that an error occurs in determining which switch is turned on.

That is, for example, on the switch KI+! If Kl and Kl are turned on at the same time, the scanning signal Ss2 is turned on! - to the switch, to the -switch through 7 to the output signal Son, originally to the switch! Only switch Km should be judged to be on, but switch Km is also judged to be on.

The present invention has the purpose of fundamentally eliminating such drawbacks of the conventional technology, and a signal of a specific state is set to the first stage in response to a load signal from an input/output circuit, and a shift operation is performed in accordance with a clock pulse. An extremely effective digital device that includes a shift register and a plurality of switching elements whose negative poles are individually connected to the output of each stage of the shift register, and whose other poles are commonly connected and connected to the input/output circuit. It provides an input circuit.

The present invention will be described in detail below with reference to FIG. 3 showing an embodiment.

FIG. 3 is a block diagram showing the configuration, and FIG. 4 is a timing chart showing waveforms of each part in FIG. ) 4t shift register S
R is provided, and the negative poles are individually connected to the outputs of the stages 5I-8n in the shift register SR, and the other poles are commonly connected and connected to the input/output circuit I10, ~ Km and field effect transistor (
Hereinafter, FET) Qf is provided, and a shift register SR
As a set input, a common potential is applied to the first stage S0, while a power supply Vc is applied to the other stages 81 to Sn.

Therefore, when a load signal (,) is sent from the input/output circuit i10 based on the operation of the processor CPU, the first stage S
oK is set to 'L' (low level), while other stages S and ~Sn are set to 1H' (high level), and the clock pulse (b) sent from the input/output circuit is
), the % L l of the first stage S1ρ is sequentially shifted to the next stage S and thereafter. ~Output of Sn (01~(g
) occur sequentially as % L I, for example switch K
.

If only the output signal (h) is turned on/off, the output signal (h) will be % in response to the second pulse 2 of the clock pulse (b).
L l is given to the input/output circuit I10 as an input to the processor CPU.

Therefore, in the processor CPU, based on the synchronization relationship between the clock pulse (b) and the output signal (h), which switch is turned on? can be judged.

Note that when other switches KI, Km, etc. and FET-Qf are turned on according to the input IN, they are also turned on according to the synchronization relationship between the clock pulse (a) and the output signal (h). In addition, even if a plurality of switching elements are turned on at the same time, they can be determined individually.

Therefore, if the switch is provided with a shift register SR close to ~Km and FET-Qf, the input/output circuit I
10, while only three wires are required, it is possible to accurately determine which switching elements are turned on.

However, a switch of 1 to Km, a FET-Qf scale, a relay contact, various semiconductor elements, etc. may be used as the switching element, and the first stage S. It is optional to set the specific state signal to %Hl instead of 'L', and when the shift register SR performs a shift operation by the trailing edge of the clock pulse (b), the first stage So can be omitted. , next stage Sl
The present invention can be modified in various ways, such as being able to be used as the first stage.

As is clear from the above explanation, according to the present invention, the number of wires connected to the input/output circuit is reduced due to the simple configuration, and it is possible to reliably determine which switching element is turned on. Furthermore, remarkable effects can be obtained as a digital input circuit for various uses.

[Brief explanation of the drawing]

1 and 2 are configuration diagrams showing a conventional example, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a timing chart showing waveforms of various parts in FIG. CPU...---Processor, Ilo...Input/output circuit, K1~Km...Switch, Qf...FET (
(field effect transistor), SR...shift register, (a)...load signal, (b)...-clock pulse. Patent applicant Yamatake Honeywell Co., Ltd. Agent
Masaki Yamakawa (and 1 other person) Figure 1 Figure 2

Claims (1)

[Claims] In a digital input circuit that provides the states of multiple switching elements to a processor via an input/output circuit,
a shift register in which a signal of a specific state is set to the first stage in response to a load signal from the input/output circuit and performs a shift operation in accordance with a clock pulse; A digital input circuit comprising a plurality of switching elements whose poles are commonly connected and connected to the input/output circuit.