JPH056335A - Inter-device interface system - Google Patents

Abstract

PURPOSE:To compact an electronic device by sharply reducing the number of interface lines by the serial conversion of an interface while suppressing the drop of data transfer performance to its minimum. CONSTITUTION:In the 1st device 105, each of switching circuits SELU, SELL for converting parallel transmitting data with a prescribed data length set up in a transmitting part to serial data SIRIU, SIRIL at the timing of the 2nd clock CLK under control from the 2nd device 106 executes the conversion to serial data by dividing the parallel data in each bits of serial data to be transferred to the 2nd device 06, i.e., in each m bits (m<=xn) in the x-times period of the 1st clock CLK1 which can be optionally set up. The 2nd device 106 serially receives the serial data divided in each m bits and sent from the 1st device 105 at the timing of the 2nd clock CLK2 and converts the received serial data into parallel data with the prescribed data length.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device-to-device interface system, and in particular, an electronic device operates based on clocks with different cycles, and a device operating with a clock with a long cycle operates from a device with a short cycle. The present invention relates to an inter-device interface system for transferring data to a device.

[0002]

2. Description of the Related Art In the conventional device-to-device interface of this type, an electronic device, particularly a computer, is required to have a high-speed processing ability. As a method, there is a method of using a high-frequency clock with a short cycle as the operation clock. On the other hand, memory chip access performance and I / O
The access performance of the device has not been improved as much as the central processing unit of the computer. Therefore, the memory control device and the I / O control device generally operate with a low-frequency clock having a long period in order to cope with this gap. In such a case, between a device operating with a high-frequency clock and a device operating with a low-frequency clock, such as an interface between the central processing unit and the memory control unit or the central processing unit and the I / O control unit. You need to control the interface. The control operation of this inter-device interface method will be described with reference to FIG.

FIG. 4 shows an inter-device interface between a device 205 (UNIT1) operating with a long cycle clock and a device 206 (UNIT2) operating with a short cycle clock. This interface is a device U that operates a long cycle clock with a short cycle clock.
The timing is controlled by making NIT2 recognize it. The clock generation unit 201 supplies the clock CLK1 having a long cycle to the device U.
The clock CLK2 having a short cycle is distributed to the device UNIT2. Further, a timing identification signal DEF for notifying the timing of the clock CLK1 having a long cycle is distributed to the device UNIT1.

FIGS. 5 (a) and 5 (b) are timing charts of the operation of the conventional example, from the device UNIT2 to the device UNI.
Describing the data transfer to T1, the data set to the data transmission register SDR2 of the device UNIT2 is performed at the timing a when the timing recognition signal DEF is "1". Therefore, the value "B" of SDR2 is stored in the SDR2 register until the cycle of the clock CLK1 having a long cycle of the timing b of the next DEF. The device UNIT1 can capture the output of this SDR2 in the data reception register RDR1 at the timing c. Next, the unit UNIT
The data transfer from the device 1 to the device UNIT2 will be described. At the timing of the clock CLK1, the data transmission register SD
The device UNIT2 receives the data stored in R1 from the data reception register R when the timing identification signal DEF is "1".
Take it into DR2.

Next, a method of reducing the number of interface signals will be described. Miniaturization of electronic devices, especially computers,
The demand for higher density is increasing more and more, and this has been considerably improved by adopting a large-scale LSI or the like. Then, as a means for downsizing by improving the logic circuit, a serial interface method for reducing the number of interface signals is put up as a general technique. This serial interface method will be described with reference to FIGS. In FIG. 6, the device 405 (UNIT1) is operated by the clock CLK1 having a long cycle, and the device 406 (UNIT) is
IT2) operates with a clock CLK2 having a short cycle. The device UNIT2 receives the timing recognition signal DEF to recognize the timing of CLK1 and controls the interface operation between the devices. Conversion of parallel data to serial data in the device UNIT1 is performed by the shift register 408SFTR1, and conversion of received data in the device UNIT2 from serial to parallel is performed by the shift register 409SFTR2. The inter-device interface line 411SIRI is a 1-bit serial interface.

The transfer timing is as shown in FIG.
Parallel data register PARA of device (UNIT1)
The data stored in 1 is serially transmitted bit by bit to the device UNIT2 at the timing of CLK1. The device UNIT2 serially receives one bit at a time of DEF and sets the parallel data register PARA2 only after receiving all bits.

[0007]

In the above-mentioned conventional inter-device interface method, the parallel interface requires 16 data lines, and there is a drawback that it is difficult to miniaturize the electronic device by increasing the density.

Further, in the case of the serial interface, the number of data lines can be significantly reduced as compared with the parallel interface method, but the data transfer time of the number of bits to be transmitted is required, and the interface performance is extremely low. It has the drawback of falling into.

[0009]

According to the inter-device interface method of the present invention, there is provided a first device which operates at a timing of a first clock and a second device which has a cycle which is 1 / n times the first clock. In a data transfer interface with a second device that operates by clock timing, the first device transmits parallel data of a predetermined bit length to the second device in units of m (m ≦ xn) bits. First switching means for converting the serial data into serial data and serial data converted by the first switching means for the second switching means.
Serial data interface line for each m-bit unit to be transmitted to the device, and parallel data of the predetermined bit length can be arbitrarily set with respect to the first clock x
Data holding means for holding only for a double period and suppressing data update, and data update notification for notifying the second device of update timing of parallel data of the predetermined bit length held by the data holding means for x times period The second device recognizes the data update timing in the first device by the data update notification, and serializes the serial data transmitted by the serial data interface at the timing of the second clock. Second switching means for receiving and converting to m-bit-unit parallel data, and a data switching instruction for the first switching means and a data switching instruction for the second switching means at the timing of the second clock. Data conversion control means to be executed, and the first switching by the data conversion control means. And a data switching instruction means for transmitting data switching instruction to the first device for changing means.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention.

In the first embodiment, the first clock CLK1 having a long cycle from the clock generation unit 101 operates as the first clock.
Device 105 and a second device 106 that operates with a second clock CLK2, which is a cycle of 1 / n times the first clock CLK1, and the second device 106 has the timing of the first clock CLK1. And receives a timing identification signal DEF for recognizing each other, and controls the inter-device interface with each other. Transmission data from the first device 105 is set in the parallel data register PARA1. Register PA
The data stored in RA1 is the switching circuits SELU, S
It is converted into serial data SIRIU, SIRIL by ELL and transmitted to the second device 106. Second device 10
Reference numeral 6 sequentially receives this by shift registers SFTRU and SFTRL, restores it to parallel data, and stores it in parallel data register PARA2. The flow of one data transfer operation has been described above. Next, the first device 105 and the second device 10
The clock ratio 1 / n of 6 and the data transfer control operation will be described.

1 to 3, the inter-device interface when the ratio of the cycles of the first clock CLK1 and the second clock CLK2 of the first device 105 and the second device 106 is 10: 1 will be described. . The inter-device transfer data is 16-bit data. Therefore, the registers PARA1, P
Each ARA2 is a register having a length of 16 bits. The switching circuit for converting the output of the register PARA1 into serial data includes a SELU for converting the upper 8 bits of the register PARA1 and a SELL for converting the lower 8 bits of the register PARA1. First device 105 to second device 1
The 8-bit unit serial data transfer to 06 is executed during one cycle of the first clock CLK1. The 1-cycle mode is the timing control unit (TMG) 10 of the first device 105.
The data stored in the register PARA1 is updated under the control of the timing control unit 108. In these switching circuits SELU and SELL, the 3-bit values of the switching signals CNTL (0), (1), and (2) are "000" → "001" → "0" as shown in the time chart.
10 ”→“ 011 ”→“ 100 ”→“ 101 ”→“ 11 ”
By switching from 0 ”to“ 111 ”, the switching circuit SELU changes the bit output of the register PARA1 to (0) →
(1) → (2) → (3) → (4) → (5) → (6) →
Select sequentially (7), register SELL is (8) →
(9) → (10) → (11) → (12) → (13) →
Select (14) → (15) in sequence and select serial data SI
Convert to 2 bits of RIU and SIRIL. The switching control signals CNTL (0), (1), (2) are transmitted to the second device 1
It is generated by the data conversion control unit (CNT) 115 of 06. Therefore, the conversion in the switching circuits SELU and SELL is performed at the timing of the second clock CLK2. That is, during one cycle of the first clock CLK1, the transmission data stored in the PARA1 register is converted into serial data SIRU, SIRIL in units of 8 bits of the timing of the second clock CLK2 having a cycle of 1/10. Two
Device 106.

Next, in the second device 106, the serial data SIRU is transferred to the shift register S every time the serial data is switched at the timing of the second clock CLK2.
Received by bit (7) of FTRU, serial data SI
The RIL is received in bit (15) of the shift register SFTRL. The received data is the shift register S
In FTRU, bits (7) → (6) → (5) → (4) →
(3) → (2) → (1) → (0) shift, SFTR
In L, bit (15) → (14) → (13) → (12)
By serially shifting in the order of (11) → (10) → (9) → (8), serial data is taken into each shift register. This value is set in the parallel data register PARA2 at the timing of the set signal SET only after all bits of the serial data have been taken into the shift registers SFTRU and SFTRL. When the data update notification SETD is valid, the data conversion control unit 113 uses the CNTL at the timing of the timing identification signal DEF.
Switching of the (0), (1), and (2) signals is started, and the set signal S is generated at the timing of the next timing identification signal DEF.
Generate ET.

FIG. 3 is a timing chart for explaining the operation of the second embodiment. The first device 105 and the second device 10 are shown.
6 clock cycle ratio, ie, the first clock CLK1
And the inter-device interface in the case where the cycle ratio of the second clock CLK2 is 5: 1 will be described. The switching circuit for converting the output of the PARA1 register into serial data is
It is composed of a SULU for converting the upper 8 bits and a switching circuit for converting the lower 8 bits of SELL in units of 8 bits. Considering the clock ratio, the serial data transfer in units of 8 bits can be executed in a double cycle of the first clock CLK1. Double cycle mode is the first device 105
The data stored in the register PARA1 is held for two cycles under the control of the timing control unit 108. The switching circuits SELU and SULL have a switching signal CNTL.
As shown in the time chart, the three bits (0), (1), and (2) are “000” → “001” → “010” → “0”.
11 ”→“ 100 ”→“ 101 ”→“ 110 ”→“ 11
By switching to 1 ", SELU becomes register PA
Bit output of RA1 is (0) → (1) → (2) → (3)
→ (4) → (5) → (6) → (7), and again SE
LL is (8) → (9) → (10) → (11) → (12)
→ (13) → (14) → (15) are sequentially selected and converted into serial data SIRIU, SIRIL and output. The switching control signals CNTL (0), (1), (2) are the second
It is generated by the data conversion control unit 115 of the device 106.
Therefore, the conversion in the switching circuits SELU and SELL is the second
Is performed at the timing of the clock CLK2. That is, the first
During one cycle of the clock CLK1 of
The transmission data stored in 1 is the second 1/5 cycle.
At the timing of the clock CLK2, the serial data is converted into serial data SIRIU and SIRIL in 8-bit units and sent to the second device 106.

Next, in the second device 106, the serial data SIRU is transferred to the shift register S every time the serial data is switched at the timing of the second clock CLK2.
Received by bit (7) of FTRU, serial data SI
The RIL is received in bit (15) of the shift register SFTRL. Then, the received data is bit (7) → (6) → (5) → (4) → (3) → in the SFTRU.
In (2) → (1) → (0), the bit (1
5) → (14) → (13) → (12) → (11) → (1
Serial data is captured in each shift register by sequentially shifting from 0) to (9) to (8). All bits of serial data are shift register SFT
This value is set in the register PARA2 at the timing of the set signal SET only after being taken into the RU and SFTRL. When the data update notification SET is valid, the data conversion control unit 115 outputs the CNTL (0), (1), (2) signals BSY at the timing of the timing identification signal DEF.
Switching is started, and the SET signal HLD is generated at the timing of DEF in the second cycle.

In this way, in the first embodiment, the first
16-bit data can be transferred from the first device 105 to the second device 106 in one cycle of the first clock CLK1, and the serial data line 2 bits (SIRI
U, SIRIL) and switching control 3 bits (CNTL)
(0), (1), (2)) and data update notification SET can be realized by a total of six hardware interface lines.

Also, in the second embodiment, the first device 105
16-bit data is transferred from the second device 106 to the second device 106 during two cycles of the first clock, and the serial data line 2 bits (SIRIU, SIRIL) and the switching control line 3 bits (CNTL (0), ( 1), (2)),
The data update notification SET can be realized by a total of 6 birdware interface lines.

In the conventional example, the parallel interface requires 16 data lines with the same performance, and the serial interface requires only one hardware line, but the transfer time is 16 times longer. Was needed. In this embodiment, it is possible to significantly reduce the number of hardware interface lines while suppressing the same performance as the parallel interface or the performance degradation to the minimum. Further, even when connected to a plurality of types of electronic devices having different clock cycles, the data transfer cycle can be arbitrarily set to provide a device that can be commonly connected to a plurality of electronic devices.

[0019]

As described above, according to the present invention, in the data transfer from the first device operating with the first clock having a long cycle to the second device operating with the second clock having a short cycle, The parallel transmission data having the predetermined data length set in the transmission unit of the first device is converted into serial data at the timing of the second clock under the control of the second device, and the conversion into the serial data is performed by the first device. The serial data is divided into units of the number of bits of serial data that can be transferred to the second device in an x-times cycle that can be arbitrarily set with respect to the clock, and the serial data divided into units of m bits is divided by the second device into the second
By receiving serially at the timing of the clock and converting it to parallel data of a predetermined data length, the interface performance of the conventional parallel data can be minimized with the same performance or performance degradation, while the interface is serialized. Since the number of lines can be significantly reduced, there is an effect that the electronic device can be downsized.

Further, even when connected to a plurality of types of electronic devices having different clock cycles, the transfer cycle of serial data can be set arbitrarily, so that it is possible to provide a device-to-device interface that can be commonly connected to a plurality of electronic devices. There is an effect.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a time chart for explaining the first embodiment of the present invention.

FIG. 3 is a time chart for explaining the second embodiment of the present invention.

FIG. 4 is a block diagram of a first conventional inter-device interface method.

FIG. 5 is a time chart for explaining the operation of the first conventional example.

FIG. 6 is a block diagram of an inter-device interface system of a second conventional example.

FIG. 7 is a time chart for explaining the operation of the second conventional example.

[Explanation of symbols]

101 Clock generation unit 102 First clock (CLK1) 103 Second clock (CLK2) 104 Timing identification signal (DEF) 105 First device 106 second device 107 Data processing unit (DAT)

Claims (2)

[Claims] 1. Data of a first device that operates at a timing of a first clock and a second device that operates at a timing of a second clock that is a cycle of 1 / n times the first clock. In the transfer interface, the first device converts the parallel data having a predetermined bit length to be transmitted to the second device into serial data in units of m (m ≦ xn) bits, and a first switching means. The serial data converted by the first switching means is converted into the second data.
Serial data interface line for each m-bit unit to be transmitted to the device, and parallel data of the predetermined bit length can be arbitrarily set with respect to the first clock x
Data holding means for holding only for a double period and suppressing data update, and data update notification for notifying the second device of update timing of parallel data of the predetermined bit length held by the data holding means for x times period The second device recognizes the data update timing in the first device by the data update notification, and serializes the serial data transmitted by the serial data interface at the timing of the second clock. Second switching means for receiving and converting to m-bit-unit parallel data, and a data switching instruction for the first switching means and a data switching instruction for the second switching means at the timing of the second clock. Data conversion control means to be executed, and the first switching by the data conversion control means. Inter device interface system and having a data switching instruction means for transmitting data switching instruction to the first device for changing means. 2. Within the x period of the first clock, the parallel data of the predetermined bit length is divided into serial data of m-bit unit, and the first device outputs the first data from the first device at the timing of the second clock. 2. The inter-device interface method according to claim 1, wherein the inter-device interface is transmitted to the second device.