JP2000347992A - Data transmitting and receiving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the data transfer speed when the same data are transferred to the continuous addresses. SOLUTION: 1st and 2nd devices 1 and 2 of a data transmitting/receiving circuit 30 consist of signal generation circuits 7 and 8 which generate the value of an address bus 3, a data bus 4, a data transfer frequency signal 5 and a data size signal 6 respectively and the restoration circuits 9 and 10 which decode the signals 5 and 6 and restore the data and addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission / reception circuit, and more particularly to a data transmission / reception circuit having an improved transfer speed when the same data is transferred to consecutive addresses.

[0002]

2. Description of the Related Art Conventionally, in data transfer, data and a destination address are output each time, but no time is required for switching from read access of a source device to write access to a destination device. ,
Japanese Patent Application Laid-Open No. 09-11477 discloses a technique capable of continuously transferring read data and improving the transfer speed of data transfer.
No. 7 is disclosed in FIG.
It is shown in FIG.

Referring to FIG. 11, a device (A) 10
1 and the device (B) 102 are connected to an address bus 110 and a data bus 111, respectively. The device (A) 101 and the device (B) 102 are controlled by device control signals 121 and 122 from a control circuit 120, respectively. Generation circuit (A) 130, address generation circuit (B) 1
31 is a device (A) 101 and a device (B) 1
The address generation circuit (A) 130 and the output of the address generation circuit (B) 131 are controlled by address control signals 123 and 124 from the control circuit 120 and output from the address selection circuit 1.
As a configuration selected at 40 and output to the address bus 110, an address necessary for reading data from the transfer source device is supplied to the address bus 110 for a certain period, and data read from the transfer source device is output to the data bus 111. While controlling by the control circuit 120 so as to keep the
By supplying the address of the transfer destination device to the address bus 110 and writing the data output from the transfer source device on the data bus 111 to the transfer destination device, the read access from the transfer source device to the write access to the transfer destination device is performed. The data transfer is performed continuously without the need for the switching time when performing the data transfer.

[0004]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Application Laid-Open No.
The technique disclosed in Japanese Patent Application Laid-Open No. 114777, which performs continuous data transfer without requiring a switching time when performing read access from a transfer source device to write access to a transfer destination device, is disclosed in Japanese Patent Application Publication No. The address must be supplied each time, so that there is a problem that a cycle time for the address transfer occurs.

It is an object of the present invention to provide a data transmitting / receiving circuit in which, when the same data is transferred to consecutive addresses, the data transfer cycle time is shortened and the transfer speed is improved by transferring the data collectively. Is to do.

[0006]

A data transmitting and receiving circuit according to the present invention comprises a first device and a second device for transmitting and receiving data, an address bus connecting the first device and the second device, a data bus, and a data transfer. A data transfer number signal indicating the number of times, and a data size signal indicating the data size, wherein the first device and the second device both include an address bus, a data bus, a data transfer number signal,
And a signal generation circuit for generating a value of each signal line of the data size signal, and a restoration circuit for decoding the data transfer number signal and the data size signal to restore data and addresses.

A signal generation circuit decodes an instruction to determine a normal access or a shortened access, and outputs a signal for validating one of the first access and a normal access control circuit used in the normal access. And a short access control circuit used for short access, and an output control circuit for outputting an input from the normal access control circuit or the short access control circuit.

The restoration circuit decodes which bit of the received data is valid according to the received address and the data size signal, and outputs a valid bit signal. A counter for restoring the originally required address by incrementing the address input from the address bus, and copying the value of the data transfer count signal and the data received by the valid bit signal from the second decoding circuit to copy the originally required data A restoring copy circuit.

The first decoding circuit is characterized in that when the same data is transferred to consecutive addresses, the first decoding circuit outputs a signal for enabling access to the shortened access control circuit.

[0010] The first decoding circuit is characterized in that when data to be transferred is different and addresses are not continuous, the first decoding circuit outputs a signal for enabling access to the normal access control circuit.

The shortened access control circuit is characterized in that it outputs only the first value of the address to be transferred.

The normal access control circuit is characterized in that the value of the address to be transferred is output as it is.

[0013] The continuous addresses are characterized in that the addresses have an error series of any one of 1, 2, and 4.

Further, the data transmitting / receiving circuit of the present invention comprises a first device and a second device for transmitting / receiving data, an address bus connecting the first device and the second device,
A data bus, a data transfer number signal indicating a data transfer number, and a data size signal indicating a data size. The first device and the second device both include an address bus, a data bus, a data transfer number signal, A signal generation circuit that generates each value of the data size signal; a restoration circuit that decodes the data transfer count signal and the data size signal to restore data and addresses; and a buffer provided at a stage preceding the restoration circuit. And

[0015]

Next, an embodiment of a data transmitting / receiving circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of the data transmitting / receiving circuit of the present invention, FIG. 2 is a block diagram showing the details of the signal generating circuits 7 and 8 of FIG.
FIG. 3 is a block diagram showing the configuration of the restoration circuits 9 and 10 of FIG. 1 in detail.

Referring to FIG. 1, a data transmitting / receiving circuit 30 of the present invention includes a first device 1 and a second device 2 for transmitting and receiving data, an address bus 3 for connecting the first device 1 and the second device 2, The first device 1 and the second device 2 each include a data bus 4, a data transfer number signal 5 indicating the number of data transfers, and a data size signal 6 indicating the data size. , A signal generation circuit 7 for generating values of the data transfer number signal 5 and the data size signal 6,
8, a data transfer number signal 5 and a data size signal 6
And restoring circuits 9 and 10 for restoring data and addresses.

Referring to FIG. 2, the signal generation circuits 7 and 8
First decodes an instruction to determine whether it is a normal access or a shortened access, and issues a signal for enabling either access.
A decode circuit 11 and a normal access control circuit 1 used when data to be transferred and an address are not continuous.
2, a shortened access control circuit 13 used when data to be transferred and an address are continuous, and an output control circuit 14 for outputting an input from the normal access control circuit 12 or the shortened access control circuit 13. ing.

Referring to FIG. 3, the restoration circuits 9, 10
A second decoding circuit 15 for decoding which bits of the data received by the address received from the address bus 3 and the data size signal 6 are valid and outputting a valid bit signal 18; A counter 16 for incrementing an address input from the address bus 3 by a value to restore an originally necessary address, and a value of the data transfer number signal 5 and data received by a valid bit signal 18 from the second decode circuit 15 Copy circuit 17 for copying and restoring originally required data
It is composed of

Next, the operation of the data transmitting / receiving circuit 30 configured as described above will be described below.

The first device 1 to the second device 2 in FIG.
First, a case where the same data is transferred to consecutive addresses and the data transfer cycle is shortened by performing at least one data transfer will be described.

Assume that the address is 32 bits and the data is 3 bits.
2 bits, data transfer count signal 5 is 2 bits, data size signal 6 is 2 bits, and valid bit signal 18 is 3 bits
Assuming that the value of the number of times of data transfer, the value of the data size, and the value of the effective bit are as shown in FIGS. 7, 8, and 9, respectively, the addresses to be transferred are four consecutive addresses 00000000h, 00000004h, 00000
008h and 0000000ch, and the data transferred to each address is the same data of 1 word,
010011h.

Referring to FIG. 1 to FIG. 3, the signal generation circuit 7
The first decode circuit 11 decodes the instruction and can perform the shortened access, so that the shortened access control circuit 13 is enabled. The shortened access control circuit 13 generates an address, data, a data transfer count signal 5 and a data size signal 6 to be output as a shortened access from the originally transferred address and data, and outputs them to the output control circuit 14.

Next, an address, data, data transfer count signal 5 and data size signal 6 are output from the output control circuit 14 to the second device 2 as shortened access. Each of the data size signals 6 is shown in FIG.

Next, the second decoding circuit 15 of the restoration circuit 10 of the second device 2 decodes which bit of the received data is valid according to the received address and the data size signal 6. The received address is 000000
00h, the value of the data size signal 6 is 1 W from FIGS.
ORD, the received data 01010011h
Decodes that 32 bits are valid.

The counter 16 receives the data transfer number signal 5,
The address input from the address bus 3 is incremented by the data size signal 6 and restored to the originally received address. Since the data size is 1 word, the address is received from the value 000000000h to 1 word.
The increment is performed three times in units, and as shown in FIG. 4B, four addresses originally received on the restoration address bus 27 are restored.

The copy circuit 17 receives the data transfer number signal 5
And the valid bit of the data received by the valid bit signal 18 from the decoding circuit 15 is restored for the data to be received. However, since the data size is 1 WORD and the data transfer count signal 5 is 4 times in FIGS. 32 bits that are 1 word from the value 01010011h
By copying the data three times, four data originally received on the restoration data bus 28 are restored as shown in FIG. 4B.

Next, the case where the number of times of data transfer is 3 and the data size is 1 BYTE during the shortened access will be described with reference to FIGS. 5 (a) and 5 (b).

The addresses to be transferred are consecutive addresses 00000005h, 00000006h, 0
000000007h, and the data transferred to each address is the same data and 10h.

The operation of the signal generation circuit 7 is the same as that in the case where the same 1-word data is transferred to the four consecutive addresses described above, and a description thereof will be omitted.

Referring to FIG. 5A, the output control circuit 1
4 outputs an address, data, data transfer number signal 5 and data size signal 6 as shortened access.

In the second decoding circuit 15, the received address is 00000005h, and the value of the data size signal 6 is 01 from FIG. 8 and is 1 BYTE, so the received data 01101011h is [1
5: 8] is valid (15 bits to 8 bits are valid).

The counter 16 has a data size of 1 BYT.
E, the value of the received address is 00000005
The address is incremented twice in units of 1 BYTE from h, and three addresses originally received are restored.

The copy circuit 17 has a data size of 1 BYE.
Since TE and the number of times of data transfer are three, three values of originally received data are restored by copying twice the value 10h of the valid bit [15: 8] of the received data.

With the above operation, the restoration address bus 2
7. FIG. 5B shows a signal restored on the restoration data bus 28.

Next, in the case of normal access in which different data is transferred to discontinuous addresses, FIG.
This will be described with reference to FIG.

Here, the address to be transferred is 0000
0000h, 00000008h, 00000100
h, 00000012h, and the data transferred to each address is 01011111h, 0100001, respectively.
1h, 01010101h, and 01011111h.

The first decode circuit 11 decodes an instruction, and since the address to be transferred is not continuous but has different data, the normal access control circuit 12 is enabled.

The normal access control circuit 12 outputs the originally transferred address and data to the output control circuit 14 as shown in FIG. 6A.

The restoration circuit 10 determines that the value of the data transfer number signal 5 is 00 and is a normal access according to FIG. 7, and uses the received address and data as they are,
As shown in FIG. 6 (b), the transferred address and data are transferred as they are to the restored address bus 27 and the restored data bus 2.
8 is output.

Next, a second embodiment of the data transmitting / receiving circuit of the present invention will be described with reference to the drawings.

FIG. 10 is a block diagram showing the configuration of a data transmission / reception circuit according to a second embodiment of the present invention. The same components as those in the first embodiment are denoted by the same reference numerals.

Data transmission / reception circuit 40 of the second embodiment
Is different from the first embodiment only in that buffers 20 and 19 are provided in front of the restoration circuits 9 and 10 of the data transmission / reception circuit 30. Others are the same as those of the first embodiment. Since it is the same as the data transmission / reception circuit 30, only the differences will be briefly described below.

The first device 1 is used as a transmitting side, and the second device 2 is used as a receiving side.
Will be described.

Referring to FIG. 10, since buffer 19 is provided before restoration circuit 10, the address from address bus 3 and the data from data bus 4 can be restored by restoration circuit 10. , The next address and data can be simultaneously received by the buffer 19 in the second device 2.

In the first and second embodiments described above,
32 bits for the address bus, 32 bits for the data bus,
The data transfer count signal is 2 bits and the data size signal is 2 bits.
The case where the number of bits and effective bit signals is 3 bits has been described. However, the number of these bits is not limited.
It goes without saying that the number of data transfers, the data size, and the range of valid bits are not limited by the number t.

[0047]

As described above, the data transmitting / receiving circuit of the present invention, when transferring the same data to consecutive addresses, shortens the address and data to be transferred on the transmitting side and shortens the cycle on the receiving side. By restoring the received address and data, a plurality of data transfers can be performed in one transfer cycle, and the data transfer speed can be improved.

Further, by providing a buffer before the restoration circuit, it is possible to simultaneously receive the next address and data by the buffer on the receiving side while the data is restored by the restoration circuit. is there.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram showing a first embodiment of a data transmission / reception circuit of the present invention.

FIG. 2 is a configuration block diagram of a signal generation circuit in FIG. 1;

FIG. 3 is a configuration block diagram of a restoration circuit in FIG. 1;

FIG. 4A is a diagram showing an output signal from an output control circuit in the case of a shortened access. FIG. 4B is a diagram illustrating an output signal from the restoration circuit in the case of the shortened access.

FIG. 5A is a diagram showing an output signal from an output control circuit in the case of a shortened access. FIG. 5B is a diagram showing an output signal from the restoration circuit in the case of the shortened access.

FIG. 6A is a diagram showing an output signal from an output control circuit in a case of a normal access. FIG. 6B is a diagram showing an output signal from the restoration circuit in the case of normal access.

FIG. 7 is a diagram illustrating a relationship between a data transfer count signal and a transfer count.

FIG. 8 is a diagram illustrating a relationship between a data size signal and a data size.

FIG. 9 is a diagram showing a relationship between a valid bit signal and a valid bit.

FIG. 10 is a configuration block diagram showing a second embodiment of the data transmission / reception circuit of the present invention.

FIG. 11 is a block diagram showing a basic configuration of a conventional data transfer control device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st device 2 2nd device 3 Address bus 4 Data bus 5 Data transfer number signal 6 Data size signal 7, 8 Signal generation circuit 9, 10 Restoration circuit 11 First decoding circuit 12 Normal access control circuit 13 Short access control circuit 14 Output control circuit 15 Second decode circuit 16 Counter 17 Copy circuit 18 Valid bit signal 19, 20 Buffer 27 Restore address bus 28 Restore data bus 30, 40 Data transmission / reception circuit 101 Device (A) 102 Device (B) 110 Address bus 111 Data Bus 120 Control circuit 121, 122 Device control signal 123, 124 Address control signal 130 Address generation circuit (A) 131 Address generation circuit (B)

Claims (9)

[Claims] 1. A first device and a second device for transmitting and receiving data, an address bus connecting the first device and the second device, a data bus, a data transfer number signal indicating the number of data transfers, and data. A data size signal indicating a size, wherein the first device and the second device both have a value of each signal line of the address bus, the data bus, the data transfer count signal, and the data size signal. And a restoration circuit for decoding the data transfer number signal and the data size signal to restore data and addresses. 2. A signal decoding circuit comprising: a first decoding circuit for decoding an instruction to determine a normal access or a shortened access and outputting a signal for validating either access; and a normal decoding circuit used for a normal access. An access control circuit, a shortened access control circuit used for shortened access,
2. The data transmission / reception circuit according to claim 1, further comprising: an output control circuit for outputting an input from the normal access control circuit or the shortened access control circuit. A second decoding circuit for decoding which bit of the received data is valid based on the received address and the data size signal and outputting a valid bit signal; A counter for restoring an originally required address by incrementing an address input from the address bus according to a value of a data size signal, and a data received by a value of the data transfer number signal and a valid bit signal from the second decoding circuit 2. A data transmission / reception circuit according to claim 1, further comprising a copy circuit for copying the data and restoring the originally required data. 4. The first decoding circuit according to claim 1, wherein when the same data is transferred to consecutive addresses, the first decoding circuit issues a signal for enabling access to the shortened access control circuit. A data transmission / reception circuit as described. 5. The apparatus according to claim 1, wherein the first decoding circuit outputs a signal for enabling access to the normal access control circuit when data to be transferred is different and addresses are not consecutive. 2. The data transmitting / receiving circuit according to 2. 6. The data transmitting / receiving circuit according to claim 1, wherein the shortened access control circuit outputs only an initial value of an address to be transferred. 7. The data transmitting / receiving circuit according to claim 1, wherein the normal access control circuit outputs the value of the address to be transferred as it is. 8. The continuous addresses have a tolerance of 1,
5. The data transmitting / receiving circuit according to claim 4, wherein the address is an arithmetic series of any one of 2, 4 and 4. 9. A first device and a second device for transmitting and receiving data, an address bus connecting the first device and the second device, a data bus, a data transfer number signal indicating the number of data transfers, and data. And a data size signal indicating a size, wherein both the first device and the second device generate respective values of the address bus, the data bus, the data transfer count signal, and the data size signal. A signal generation circuit, a restoration circuit for decoding the data transfer number signal and the data size signal to restore data and addresses,
A data transmission / reception circuit, comprising: a buffer provided before the restoration circuit.