JPH04333954A - Information processor - Google Patents

Abstract

PURPOSE:To connect the data buses of various bit widths without being conscious of them in the manner of a software by apparently connecting more than two bus lines with the various bit widths as the same bus line. CONSTITUTION:When a command is inputted from a command signal 111 from a 2N bus, a bus control circuit 106 inverts an address signal 109 and outputs it as an address signal 110, and a command signal 112 outputs the command signal 111. Therefore, an N bus performs access to a memory inverting the address 109 and when the access is completed, a latch signal 107 or 108 corresponding to the address 110 is outputted. Next, the address signal 110 is recovered, the command signal 112 is outputted, and data are read from the N bus. At such a time, correspondent data are respectively outputted from bus buffers 101 and 102.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a data bus control circuit for connecting data buses having different bit widths.

0002

2. Description of the Related Art Conventionally, when data buses having different bit widths are connected, the bus with the smaller bit width is connected only to the upper or lower bus of the bus with the larger bit width. Therefore, in order to use an optional device designed with a small bit width in a system with a large bit width, it is necessary to generate data transfer means multiple times in software and connect it, assuming that the bit width is different. I had to.

0003

[Problem to be Solved by the Invention] However, as the bit width of the data bus increases, in order to use an optional device with a smaller bit width of the data bus, data must be transferred multiple times using software. . the result,
Data transfer efficiency deteriorates.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to access data buses with different bit widths by dividing the bus access.
The purpose is to connect data buses with different bit widths without being aware of it using software.

[0005]

[Means for Solving the Problems] The present invention provides an information processing device comprising a central processing unit and a bus line for transmitting signals from the central processing unit, wherein the bus line has two or more lines having different bit widths. The device includes a bus line, a plurality of bus buffer circuits that connect the bus lines, and a bus control circuit that controls the bus buffer circuit, so that two or more bus lines having different bit widths appear to be the same. The information processing device further comprises means for connecting n-bit bus lines, m bus buffer circuits, and latch control signals of the m bus buffer circuits. The present invention is characterized in that it comprises a bus control circuit for controlling, and means for connecting the n-bit bus line and the mn-bit bus line apparently as the same bus line.

[0006]

[Operation] Data buses with different bit widths are connected by latchable bus buffers, and an access control circuit that divides the bus buffer and bus access is used, allowing one access when accessing a bus with a small bit width. The bus is divided into several parts and a divided access is performed to a bus with a small bit width. At this time, by using a data bus buffer that divides and latches data for each access, even if buses with different bit widths are accessed, it is possible to perform the same access in terms of software as when accessing a data bus with the same bit width. Become.

[0007]

【Example】

(Embodiment 1) FIG. 1 shows a block diagram of a system for realizing the present invention. The n-bit bus 103 is connected to the 2n-bit bus 104, 1 by the bus buffers 101, 102.
Connected to 05. At this time, bus buffer latch control signals 107 and 108 are driven by bus control circuit 106. Address signal 109 is also connected to address signal 110 of n-bit bus 103 through bus control circuit 106 . Similarly, the command signal 111 is also sent to the bus control circuit 1.
Command signal 11 on n-bit bus 103 through 06
Connected to 2. In this system, when a command is input from the command signal 111 from the 2N bus, the bus control circuit 106 inverts the address signal 109 and outputs it as an address signal 110, and the command signal 112 outputs the command signal 111. As a result, the N bus accesses the memory whose address 109 has been inverted. When this access is completed, the latch signal 107 or 108 corresponding to address 110 is output. Next, the address signal 110 is returned to its original state and the command signal 112 is output. Output and read data from the N bus. At this time, bus buffer 1
From 01 and 102, corresponding data is output.

(Embodiment 2) Next, a case in which a 32-bit bus and a 16-bit bus are connected will be specifically described. Figure 2 shows a block diagram of this system. A time chart of this specific example is shown in FIG. 16-bit bus 203 is connected to 32-bit buses 204, 205 by bus buffers 201, 202. At this time, the bus buffer latch control signals 207 and 208 are sent from the bus control circuit 206. The control signal 207 becomes active when the address signal 210 is Low, and the control signal 208 becomes active when the address signal 210 is High. Also, address signal 2
As 10, the address SA1 on the 16-bit bus side is connected. In this system, a command from a 32-bit bus is input as a command signal 211, and when a command start signal 213 is input, the bus control circuit 206 outputs a LOW address signal 210. In addition, the command signal 21
A command start signal 214 for the 2 and 16 bit buses is generated and output. As a result, on the 16-bit bus side, the memory whose address signal SA1 is LOW is accessed. When this access is completed, a command end signal 216 is input to the bus control circuit 206 from the 16-bit bus. The bus control circuit 206 outputs a data latch signal as a control signal 208, and outputs a data latch signal as a control signal 208, and
The bit data is latched into the bus buffer 202.

A circuit shown in FIG. 4 is used as the bus control circuit 206. This circuit takes in a status signal 401 as an address inversion signal 403 using a command start signal 402. When the address inversion signal 403 is HIGH, the inversion signal of the address signal 404 is output as the address signal 405, the command end signal 407 is fixed at "High" by the address inversion signal 403, and the command end signal 406 is not output. With the rise of the command end signal 406, the address inversion signal 403 goes low.
”, and the address signal 404 is set to the address signal 405.
is output, and the command end signal 406 is output as the command end signal 407. As a result, the bus control circuit 2
06, the control circuit 206 outputs HIGH to the address signal 210 without outputting the command end signal 215 to the 32-bit bus in response to the command end signal 216,
The command signal 212 and command start signal 214 are output again.

[0010] As a result, the address S on the 16-bit bus
The memory where A1 is "High" is accessed. When this access is completed, a command end signal 216 is input to the bus control circuit 206 from the 16-bit bus. The bus control circuit 206 outputs a data latch signal as a control signal 207, and latches the upper 16 bits of data of the 32-bit bus into the bus buffer 201. As a result, corresponding data can be output to the data buses 204 and 205, respectively. Further, in response to this command end signal 216, the bus control circuit 206 outputs a command end signal 215 to the 32-bit bus to notify the 32-bit bus of the end of access. This makes it possible to read correct data from the 32-bit bus. By using this method of dividing a 32-bit access into two 16-bit accesses, 16 bits can be accessed from a 32-bit wide bus.
It becomes possible to access a bit-wide bus.

As described above, by using means for dividing and accessing data buses with different bit widths, it becomes possible to connect data buses with different bit widths.

0012

According to the present invention, it is possible to connect data buses having different bit widths without being aware of the software.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data control circuit according to the present invention.

FIG. 2 is a block diagram when connecting a 32-bit data bus and a 16-bit data bus according to the present invention.

FIG. 3 is a time chart of the data control circuit according to the present invention.

FIG. 4 is a diagram showing an example of a bus control circuit of the present invention.

Claims (2)

[Claims] 1. An information processing device comprising a central processing unit and a bus line for transmitting signals from the central processing unit, wherein the bus line has two or more bus lines having different bit widths, and a signal between the bus lines. a plurality of bus buffer circuits for connecting the bus buffer circuits; and a bus control circuit for controlling the bus buffer circuits; An information processing device comprising: 2. The information processing device includes an n-bit bus line, m bus buffer circuits, a bus control circuit for controlling latch control signals of the m bus buffer circuits, and the n-bit bus line. 2. The information processing apparatus according to claim 1, further comprising means for connecting the mn bit bus line and the mn bit bus line apparently as the same bus line.