JPH09134325A - Dma controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute DMA transfer at a high speed even when the byte position of a transferring source does not coincide with that of a transferred destination. SOLUTION: When a CPU 1 has 32-bit data bus width, a ROM 2 and a RAM 3 respectively have 32-bit data bus width and DMA transfer is executed by 8-bit data bus width for instance, a control ASIC 4 having a DMA control function drives only bits not to be driven by a source device. Thereby write data can be driven without waiting the turning-off of the source device, and even when the bit position of the source device is different from that of a destination device, high speed DMA transfer can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention performs control so that data can be transferred between an input / output device connected to an external device and a memory without going through an arithmetic and control unit such as a central processing unit. The present invention relates to speeding up of DMA controller, especially DMA transfer in which the amount of data transferred in one cycle is smaller than the data bus width.

[0002]

2. Description of the Related Art DMA between an input / output device connected to an external device and a memory which does not require an address and a memory
When transferring, it is not necessary to give an address to the I / O device, so one type of address
Only the bus is good. For this reason, even in the conventional system, it is possible to realize it in only one bus cycle by simultaneously performing read and write.

On the other hand, when performing DMA transfer between memories,
Different addresses must be given to the two memories, the transfer source and the transfer destination. Since the conventional system has only one type of address bus, it is executed as two separate bus cycles of read and write. Therefore, there is a problem that the processing time is long. Therefore, JP-A-6-
As shown in Japanese Patent No. 332842, by having two types of address buses, one bus can be used for DMA transfer between memories.
I am able to run it in cycles.

[0004]

Due to the demand for high-speed processing, the CPU has been expanding its data bus width, and 32-bit and 64-bit CPUs are also used. However, an input / output device having an 8-bit width is often used as it is. Therefore, when performing a DMA transfer, the byte positions of the transfer source and the transfer destination are limited, or the transfer is executed in two bus cycles of read and write. Therefore D
In some cases, MA transfer cannot be executed in one cycle, which causes an increase in processing time. In particular, many I / O devices have a long turn-off time, which requires a long wait time between reads and writes, and the need to use a buffer with a short turn-off time to separate the buses. there were.

The present invention has been made to solve the above disadvantages, and DMA transfer can be performed at high speed even when the byte positions of the transfer source and the transfer destination are not the same.
The purpose is to obtain a controller.

[0006]

A DMA according to the present invention
The controller has a data transfer rate of 1 cycle.
When controlling a DMA transfer smaller than the bus width, the source device drives only the bits that the source device does not drive.

The above DMA controller copies the read data to the bit positions not driven by the source device regardless of the bit positions of the source device and the destination device. It is characterized by driving with −.

Further, the above-mentioned DMA controller, when the bit positions of the source device and the destination device are different, sets the bit at the position of the destination device to the read data. It is characterized by driving by copy.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, a CPU has a data bus width of, for example, 32 bits, and ROM, RA
Both M have a bus width of 32 bits, and when data is DMA-transferred with an 8-bit data bus width, the DMA controller does not drive the source device (transfer source device) to drive the bits. By driving only the source device, the write data can be driven without waiting for the turn-off time of the source device, and the source device and the destination device (destination device) Even if the bit positions of are different, the DMA transfer is performed at high speed.

In addition, the source device and the destination
Regardless of the bit position of the destination device, the bit position that the source device does not drive is driven by the copy of the read data, and the destination device exists at which byte position. However, high-speed DMA transfer is performed without being aware of it.

Also, the source device and the destination
When the bit positions of the destination devices are different, the bits at the destination device positions are driven by the copy of the read data to reduce the number of simultaneous switching and noise generated in the power line. DMA transfer is performed at high speed while suppressing the above.

[0012]

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, the CPU 1 reads an instruction stored in the ROM 2 and RA
The process proceeds while using M3. Control ASIC (appli
cation specific integrated circuit I
C) 4 receives a read / write request from CPU 1,
The control signals are used to control each device to do so. Further, the control ASIC 4 is an R composed of a DRAM.
It also controls the refresh for AM3. The control ASIC 4 has a DMA control function so that data can be directly transferred between the devices without interposing the CPU 1. DUART (dual univers
al asynchronous receiver / transmitter, dual asynchronous receiver / transmitter 5 is an interface device for performing serial communication with an external device.

The CPU 1 has a 32-bit data bus width, and the ROM 2 and the RAM 3 both have a 32-bit bus width. DUART5 has an 8-bit bus width, and
D of 32-bit data bus of [31: 0]
It is connected to [31:24]. Then, the received data from the external device is D-transferred by the DMA transfer by the control ASIC4.
Data is transferred from the UART5 to the RAM3, and the transmission data to the external device is DM from the RAM3 to the DUART5.
A can be transferred. This control ASIC4 is DMA
Since the bus widths of the DUART 5 and the RAM 3 are different when performing the transfer, if the RAM 3 is to be used effectively without a gap, DMA transfer between different bit positions is required. That is, since DUART 5 is connected to D [31:24], not only D [31:24] but also D [2
3:16], D [15: 8] and D [7: 0] are required to be transferred.

Therefore, the data bus control portion of the control ASIC 4 having the DMA controller function is constructed as shown in the block diagram of FIG. In FIG. 2, D [31:
0] is a data bus connected to the ROM 2, RAM 3 and DUART 5, and is also used inside the control ASIC 4 as DI [31: 0] via the input buffers 203 to 206. This signal is also input to the 4: 1 selector 201, and 1 byte out of 4 bytes is selected and D
The signal S [7: 0] becomes a selector 2 of 2: 1.
2 is input. The 2: 1 selector 201 is DO [3
DC [31:24] or DS [7: 0] as 1:24]
Is selected and DC is also set as DO [23:16].
Select [23:16] or DS [7: 0]. DO
[15: 8] is DC [15: 8] or DS [7:
0] is selected, and as DO [7: 0], DC [7:
0] or DS [7: 0] is selected. DC [31:
0] is a signal from inside the control ASIC 4,
ROM2, RAM3, DUART5
It is used as a write data path when writing to. EN3 *, EN2 *, EN1 * and EN0 * are control signals for the output buffers 207 to 210 of the data bus, respectively, and are active low. Therefore, by setting this signal to the low level, the corresponding output buffers 207 to 210 are driven.

As described above, conventionally, the DMA transfer at different bit positions is divided into two bus cycles of read and write to secure the turn-off time of the read device and then the DMA control. Drive starts writing write data, which causes DMA between different bit positions.
While the control ASIC4 drives only the bits that the source device does not drive, the control ASIC4 controls the source ASIC4 even in the DMA transfer between different bit positions. The drive of write data can be started without waiting for the device to turn off, and the DMA transfer can be executed at high speed.

Next, D from the DUART5 to the RAM3
Bus cycle timing chart showing MA transfer
Is shown in FIG. In FIG. 3, RA [11: 0] is R
Address signals to AM3, and RAS *, CAS * and RWE * are control signals to RAM3. ADDR
[23: 0] is an address signal to ROM3 and DUART5, and CSO * is an active low signal of DUART5.
Is a chip select signal. Write * is DUART5
Is a control signal to CSO * and has a meaning when CSO * is asserted, and is a lead at low level. These signals are signals which the control ASIC 4 drives and supplies to each device. D [31:24] and D [23: 1
6], D [15: 8] and D [7: 0] are data buses, EN3 *, EN2 *, EN1 * and ENO * are signals inside the control ASIC4 as described above, and byte The output buffers 207 to 210 are controlled for each. In FIG. 3, the read address is given with CSO * asserted and Write * negated.
A read from DUART5 is being performed. As a result, after a predetermined time, the read data is transferred by the DUART 5
Driven on the D [31:24] data bus.
At this time, since EN2 *, EN1 * and ENO * are asserted, D [23: 0] is driven. The contents to be driven are the selectors 201 and 201 shown in FIG.
The data copy of D [31:24] is driven by 02. At the same time, since write control is performed on the DRAM, data can be written on the DRAM at any byte position.

Next, unlike the case of FIG. 3, the bus transfer showing the DMA transfer when only ENO * is asserted.
The cycle timing chart is shown in FIG. As shown in FIG. 4, since only ENO * is asserted,
Of the data bus, only D [7: 0] are being driven. As a result, DMA transfer from the DUART 5 to the DRAM connected to D [7: 0] is performed. In this case, since the control ASIC 4 drives only 8 bits out of 32 bits, it is possible to suppress the number of simultaneous switching to be low and suppress the noise generated in the power supply line.

In the embodiment, the bus width of 32 bits is shown for 8-bit transfer to the RAM3.
The same can be applied to transfers other than 8 bits.

[0019]

As described above, according to the present invention, in the DMA transfer in which the data transfer amount is smaller than the data bus width, the source device drives only the bits that are not driven. Since the write data can be driven without waiting for the turn-off time of the source device, DM can be performed at high speed even when the bit positions of the source device and the destination device are different.
A transfer can be performed.

Also, the source device and the destination
The bit position not driven by the source device is driven by the copy of the read data regardless of the bit position of the station device.
High-speed DMA transfer can be performed without being aware of the byte position of the device.

Also, the source device and the destination
If the bit positions of the destination devices are different, the bits of the destination device positions are driven by the copy of the read data, so the number of simultaneous switching is reduced and the noise generated in the power line is reduced. It is possible to perform high-speed DMA transfer while suppressing the above.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a data bus control portion of the control ASIC of the above embodiment.

FIG. 3 is a timing chart of a bus cycle showing a DMA transfer.

FIG. 4 is a timing chart of another bus cycle showing a DMA transfer.

[Explanation of symbols]

 1 CPU 2 ROM 3 RAM 4 Control ASIC 5 DUART

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomoki Ishii 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Riko Co., Ltd.

Claims (3)

[Claims] 1. A DMA controller which controls so that data is directly transferred between a memory and an input / output device, in which a data transfer amount of one cycle is smaller than a data bus width. A DMA controller, characterized in that it controls only the bits that the source device does not drive when controlling the transfer. 2. The DMA controller according to claim 1, wherein the bit position not driven by the source device is read regardless of the bit positions of the source device and the destination device. A DMA controller characterized by being driven by a copy of data. 3. The DMA controller according to claim 1, wherein when the bit positions of the source device and the destination device are different, the bit at the position of the destination device is read. A DMA controller characterized by being driven by a copy of data.