JP3210939B2 - Process control device with PIO simulation memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process control device having a direct PIO input / output device and a simulation memory, and more particularly to a process control device having a PIO input / output device and a PIO simulation memory provided with a circuit for switching a CPU access destination to the simulation memory. It relates to a process control device.

[0002]

2. Description of the Related Art Conventionally, there is a bus coupling device as a device that can perform software debugging of a process control device without changing software when a plant system is incomplete and a PIO is not installed. In this apparatus, a transfer memory is provided between the CPU of the process control device and the PIO,
U reads and writes only to this transfer memory. On the other hand, a data transfer circuit is provided between the transfer memory and the PIO, and the data in the transfer memory and the PIO data are periodically matched. This allows the CPU data to be
To tell.

When this bus coupler is applied to a system without a PIO, the data transfer circuit may be stopped at the time of software debugging, and debugging can be performed without changing software.

There is an interface level converter as a device for directly accessing a specific PIO, which enables high-speed PIO access.

Further, in Japanese Patent Application Laid-Open Nos. 60-93519 and 62-99807, a PIO and a simulation memory are connected to a CPU via an access destination switching unit, and the access destination of the CPU is switched by the switching unit. Has been disclosed.

[0006]

SUMMARY OF THE INVENTION The above-mentioned bus coupling device comprises:
First, since the data transfer circuit periodically matches the data in the transfer memory with the PIO data, when the CPU sends data to the specific PIO, or when the CPU
Since the time of the maximum-transfer cycle is required when fetching IO data, no consideration is given to an increase in the number of PIO points, and the latest data transfer time increases when the CPU performs data transfer of a specific PIO. .

Second, since the interface level converter directly accesses the PIO, no consideration is given to when the PIO is not mounted. When the PIO is not mounted, the interface level converter becomes inoperable, and the software is changed to hinder software debugging. And so on.

Further, according to the techniques described in Japanese Patent Application Laid-Open Nos. 60-93519 and 62-99807, software debugging can be performed by accessing a simulation memory even when a PIO is not provided. And when non-simulation, CP
The access destination can be switched by the access destination switching unit so that the U directly accesses the PIO.
It does not take a long time to take in IO data. However, in this technology, an access destination switching registration memory having an address similar to that of the PIO is provided for an access destination switching instruction, and the CPU simultaneously accesses the access destination switching registration memory when accessing the PIO or the simulation memory. Then, the accessed access destination switching registration memory outputs address destination switching bit data preset for each address to the access destination switching unit, and switches the access destination of the CPU to one of the PIO and the simulation memory. Is configured. For this reason, when software debugging is performed in a state where no PIO is installed, it is necessary to register in advance the part corresponding to the PIO in the access destination switching registration memory in order to access the simulation memory. A similar registration procedure is required when returning to the simulation state. Therefore, if only a specific PIO is not implemented,
It is possible to access the simulation memory instead of accessing only when the PIO is accessed. However, when the number of PIO points is large, registration in the access destination switching registration memory, that is, a great deal of labor is required for changing the software.

SUMMARY OF THE INVENTION An object of the present invention is to provide a process control device having a simulation memory and a direct PIO input / output device having a short transfer time of latest data, which enables software debugging without changing software when PIO is not mounted. It is in.

[0010] Further, there is no software change depending on the case, such as when only the input device among the PIO input / output devices is not mounted, when only the output device is not mounted, or when both the input / output devices are not mounted. To enable soft debugging.

[0011]

The above object is achieved by a CPU.
And a process control device with a PIO simulation memory including a direct PIO input / output device and a simulation memory connected to the CPU.
At least a signal control circuit of the IO input / output device and the simulation memory is connected to the CPU via an access destination switching circuit, and the access destination switching circuit includes a simulation mode setting signal input circuit,
Depending on the state of the simulation mode setting signal, the CPU
Of the access destination is set to either PIO and simulation memory, during PIO access to switches the circuit so as to write the read data from the write data and the PIO to PIO together the simulation memory, CPU directly PIO input Output device and simulation
A memory for the data bus and the address bus,
This is achieved by connecting without going through the access destination switching circuit .

[0012]

The above object is also achieved by a process control device with a PIO simulation memory according to claim 1 , wherein the access destination switching circuit comprises a plurality of simulation mode setting signal input circuits.

The above object is also achieved by a simulation mode setting circuit comprising: a simulation mode setting signal input circuit; and first and second OR gates and AND gates each having one of the input sides connected to the simulation mode setting signal input circuit. A third OR gate whose input side is connected to the mode setting signal input circuit via an inverter,
A second AND gate connected to the output of the third OR gate, wherein the strobe signal output of the CPU is a strobe signal input of the simulation memory and the first
Connected to the other input of the third OR gate via a delay gate and the other input of the third OR gate.
The read / write instruction output of the PU is connected to the read / write instruction input of the PIO and the other input side of the first AND gate, and the output side of the first OR gate is connected to the strobe input of the PIO. An output of the first AND gate is connected to a read / write instruction input of the simulation memory, an acknowledge signal output of the PIO is connected to the other input side of the second OR gate, and an output of the second AND gate is a CPU. 2. The PIO according to claim 1, wherein the PIO is connected to an acknowledge signal input of the PIO.
This is also achieved by a process control device with a simulation memory.

The above-mentioned problem is also caused by the fact that the access destination switching circuit uses the PIO connection for both reading and writing of the CPU and C
PIO connection only for PU reading, PIO connection only for CPU writing, PIO for both CPU reading and writing
The present invention is also achieved by a process control device with a PIO simulation memory according to claim 2 , wherein four modes of non-connection are selected.

[0016]

A simulation mode setting signal is input to the access destination switching circuit to instruct whether the process control device operates in the simulation mode or the non-simulation mode. The access destination switching circuit is C
A control signal such as a read / write signal and a strobe signal input from the PU is controlled, and if the instruction of the simulation mode setting signal is the simulation mode, an access destination of the CPU is set in the simulation memory. Performed only for simulation memory.

If the instruction of the simulation mode setting signal is the non-simulation mode, the access destination switching circuit sets the access destination of the CPU to PIO, and
Both the data read from the PIO and the data written to the PIO are written to the simulation memory.

A read (hereinafter referred to as read) / write (hereinafter referred to as write) signal outputted by the CPU is outputted as it is to the PIO, is outputted as it is to the simulation memory in the simulation mode, and is always a write signal in the non-simulation mode. Is fixed and output.

The strobe signal output by the CPU is not output to the PIO in the simulation mode, is output as it is in the non-simulation mode, and is output to the simulation memory in both the simulation mode and the non-simulation mode.

The CPU, PIO, data bus and address bus of the simulation memory are all connected.

In the non-simulation mode, the acknowledgment signal output from the PIO is output to the CPU. In the simulation mode, the strobe signal output from the CPU is output to the CPU as an acknowledgment signal after being delayed by the simulation memory write time. You.

1) When the simulation mode setting signal indicates the simulation mode to the access destination switching circuit and the CPU outputs a read signal and a strobe signal to the access destination switching circuit and outputs an address to the address bus, Since the first switching circuit does not output a strobe signal to the PIO, the PIO does not operate and does not output a data and acknowledge signal.

On the other hand, since a read signal and a strobe signal are output from the access destination switching circuit to the simulation memory, the simulation memory outputs data at a specified address. In addition, the access destination switching circuit delays the strobe signal by an appropriate time and outputs it to the CPU as an acknowledge signal.
U takes in the data output from the simulation memory and ends the read access normally.

2) The simulation mode setting signal indicates the simulation mode to the access destination switching circuit, and the CPU outputs a write signal and a strobe signal to the access destination switching circuit, and also writes the write data and address to the data bus and the address bus. When output, the access destination switching circuit does not output a strobe signal to the PIO, so that the PIO does not operate and does not output an acknowledge signal.

On the other hand, since the access destination switching circuit outputs a write signal and a strobe signal to the simulation memory, the simulation memory takes in the write data and writes it at the designated address. Further, the access destination switching circuit outputs the acknowledgment signal to the CPU after delaying the strobe signal by an appropriate time, so that the CPU normally ends the write access.

3) Next, when the simulation mode setting signal indicates the non-simulation mode and the CPU outputs a read signal and a strobe signal to the access destination switching circuit and outputs an address to the address bus, the access destination switching circuit In order to output a read signal and a strobe signal to the PIO, the PIO outputs data of a designated address and an acknowledge signal.

On the other hand, since the access destination switching circuit outputs a write signal and a strobe signal to the simulation memory, the simulation memory takes in the data on the data bus, that is, the data specified by the PIO by taking in the data output from the PIO. Write to. Further, the access destination switching circuit outputs the acknowledge signal output by the PIO to the CPU as it is, so that the CPU takes in the data output by the PIO and ends the read access normally.

4) Next, when the simulation mode setting signal indicates the non-simulation mode, the CPU outputs the write signal and the strobe signal to the access destination switching circuit, and outputs the write data and the address to the data bus and the address bus. And the access destination switching circuit is P
To output a write signal and a strobe signal to the IO, the PIO fetches the write data, writes the write data to a specified address, and outputs an acknowledge signal.

On the other hand, since the access destination switching circuit outputs a write signal and a strobe signal to the simulation memory, the simulation memory takes in the data on the data bus, that is, the data output from the CPU and receives the designated address. Write to. Further, the access destination switching circuit outputs the acknowledgment signal output from the PIO to the CPU as it is, so that the CPU normally ends the write access.

As described above, during the simulation, the PIO
Since the normal operation can be performed even if is not connected, software debugging can be performed without changing software.

Further, when the simulation mode setting signal is set to two signals and the PIO is configured to indicate four modes of input / output connection, output only connection, input only connection, and input / output non connection, The output address is P
IO, output to simulation memory.

The data buses of the CPU, PIO, and simulation memory are all connected.

When the simulation mode setting signal instructs PIO connection for both input and output, and the CPU performs read access, the CPU outputs a read signal and a strobe signal to the access destination switching circuit, and outputs an address to the address bus. Is output. The access destination switching circuit is P
A read signal and a strobe signal are output to the IO, and a write signal and a strobe signal are output to the simulation memory. Further, the access destination switching circuit outputs the acknowledge signal output by the PIO as it is as the acknowledge signal to the CPU. Thus, the operation becomes the same as the operation 3).

Next, when the simulation mode setting signal instructs PIO connection for both input and output and the CPU performs write access, the CPU outputs a write signal and a strobe signal to the access destination switching circuit, and outputs a data bus. , And outputs the write data and the address to the address bus. The access destination switching circuit outputs a write signal and a strobe signal to the PIO, and outputs a write signal and a strobe signal to the simulation memory. The access destination switching circuit outputs the acknowledge signal output by the PIO as it is as an acknowledge signal to the CPU. As a result, the operation described in the above 4)
The operation is the same.

Next, when the simulation mode setting signal instructs the PIO connection only for the output and the CPU performs the read access, the access destination switching circuit does not output the strobe signal to the PIO but outputs the strobe signal to the simulation memory. Outputs a read signal and a strobe signal. Further, the access destination switching circuit appropriately delays the strobe signal as an acknowledgment signal for the CPU, and then outputs the acknowledgment signal to the CPU. Thereby, the operation becomes the same as the above 1) operation.

Next, when the simulation mode setting signal instructs the PIO connection only for the output and the CPU performs the write access, the access destination switching circuit outputs the write signal and the strobe signal to the PIO and simultaneously outputs the write signal and the strobe signal to the simulation memory. On the other hand, a write signal and a strobe signal are output. The access destination switching circuit is C
The acknowledgment signal output by the PIO is directly output to the CPU as the acknowledgment signal for the PU. As a result, the operation becomes the same as the above 4).

Next, when the simulation mode setting signal instructs the PIO connection only for the input and the CPU performs the read access, the access destination switching circuit sends the PIO to the PIO.
A read signal and a strobe signal are output, and a write signal and a strobe signal are output to the simulation memory. The access destination switching circuit is CP
The acknowledgment signal output by the PIO is directly output to the CPU as the acknowledgment signal for U. Thereby, the operation becomes the same as the above 3).

Next, when the simulation mode setting signal indicates the input only for the PIO connection and the CPU performs the write access, the access destination switching circuit sends the PIO to the PIO.
A strobe signal is not output, and a write signal and a strobe signal are output to the simulation memory. Further, the access destination switching circuit appropriately delays the strobe signal as an acknowledge signal to the CPU, and then outputs the signal to the CPU as an acknowledge signal. Thus, the operation is the same as in the above 2).

Next, when the simulation mode setting signal indicates that the input and output are not connected to the PIO and the CPU performs read access, the access destination switching circuit does not output a strobe signal to the PIO and also outputs a strobe signal to the simulation memory. And outputs a read signal and a strobe signal. The access destination switching circuit outputs the acknowledgment signal to the CPU after appropriately delaying the strobe signal as an acknowledgment signal to the CPU. Thereby, the operation becomes the same as the above 3).

Next, when the simulation mode setting signal indicates that the input and output are not connected to the PIO and the CPU performs write access, the access destination switching circuit does not output a strobe signal to the PIO and also outputs a strobe signal to the simulation memory. And outputs a read signal and a strobe signal. Further, the access destination switching circuit appropriately delays the strobe signal as an acknowledge signal to the CPU, and then outputs the signal to the CPU as an acknowledge signal. Thereby, the operation becomes similar to the above 4).

[0041] Thus, since during the simulation even when four and the operation mode capable of normal operation without connecting the PIO, software without software changes
Can perform debugging .

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows a main part of a process control device according to the present invention. In this embodiment, a CPU 1 and a process input / output device (hereinafter referred to as PIO) connected to the CPU 1 via an address bus 4 and a data bus 5 are shown. And a simulation memory 3 connected to the address bus 4 and the data bus 5. The CPU address output 104 is provided via an address bus 4 to a PIO address input 204 and
Connected to simulation memory address input 304. The CPU data input / output 105 is connected to the PIO data input / output 205 and the simulation memory data input / output 305 via the data bus 5. A CPUR / W (read / write) output 106 which is one of the control signal circuits is connected to a PIOR / W input 206 and one input side of the first AND gate 11. The output side of the AND gate 11 is connected to a simulation memory R / W input 306. C which is one of the control signal circuits
The PU / STB (strobe) output 107 is connected to the PIO / STB input 207 and the simulation memory / STB input 307 via the first OR gate 10. The CPU / STB (strobe) output 107 further passes through a delay gate 13,
As the delay output 308, the acknowledgment switching circuit 12
It is connected to the. The acknowledgment switching circuit 12 includes OR gates 12A and 12B as second and third OR gates.
And a second AND gate 12C which receives the outputs of the OR gates 12A and 12B as inputs. The output of the AND gate 12C is connected to the CPU / ACK input 108. The PIO / ACK output (acknowledge) 208 is connected to one input of the OR gate 12A of the acknowledge switching circuit 12, and the delay output 308 is connected to one input of the OR gate 12B. The simulation mode setting signal input circuit 14 for transmitting the simulation mode setting signal 100 is connected to the other input side of the OR gate 10, the other input side of the AND gate 11, the other input side of the OR gate 12A of the acknowledge switching circuit 12, and the NOT gate. To the other input side of 12B respectively. The acknowledgment switching circuit 12, the AND gate 11, the OR gate 10, the delay gate 13,
The simulation mode setting signal input circuit 14 and a signal line connecting the CPU 1, the PIO 2, and the simulation memory 3 to each other constitute an access destination switching circuit. In the following description, the PIO / ACK output (acknowledge) 208, the simulation memory R /
Symbols such as the W input 306 are used to mean both input / output points and signals input / output therefrom.

Here, it is assumed that the simulation mode setting signal 100 is "H" during simulation and "L" during non-simulation. R / W106,206,306
Is "H" for reading and "L" for writing. / STB1
07, 207, and 307 are "H" indicating no access and "L" indicating access. / ACKs 108 and 208 are "H" indicating no response and "L" indicating a response.

During the simulation, since the simulation mode setting signal 100 is "H", the PIO / STB input 207 remains "H" by the OR gate 10. Further, the CPUR / W output 106 is input to the simulation memory R / W input 306 by the AND gate 11.
Is output as is. Acknowledge switching circuit 1
2, the delay output 308 is selected and the CPU / A
The delay output 308 of the CPU / STB output 107 is output to the CK input 108 as it is.

Next, during non-simulation, since the simulation mode setting signal 100 is "L", the POR / STB input 207 is
The CPU / STB output 107 is output as it is. Further, the simulation memory R / W input 306 remains “L” due to the AND gate 11. Also, the acknowledgment switching circuit 12 causes the PIO / ACK output 208
Is selected, and the PIO /
The ACK output 208 is output as it is.

The operation of this configuration will be described with reference to FIGS. FIG. 2 shows the operation during non-simulation. The simulation mode setting signal 100 is "L" and the CP
U1 performs PIO read and write.

1) During non-simulation and at the time of reading, the CPU 1 transfers the PIO address to the address bus 4
This address is received by the PIO 2 and the simulation memory 3. Also, the CPU 1 has R / W10
6 is read and “H” is output.
The W input 206 inputs "H" and is a read instruction, and the R / W input 306 of the simulation memory 3 is "L" and is a write instruction. Further, the CPU 1 outputs the / STB output 107 and the / STB input 20 of the PIO 2
7 and / STB input 307 of simulation memory 3
Output to This is a state where the PIO 2 is being read-accessed, and the PIO 2 outputs the PIO data to the data bus 5. This data output is sent to CPU1
And the simulation memory 3. On the other hand, since the simulation memory 3 is in a write-access state, the simulation memory 3
Capture the above PIO output data. Also, PIO2 is /
Although the ACK output 208 is output, the acknowledgment switching circuit 12 selects the PIO / ACK output 208, so that the PIO / AC input 108 is output to the CPU / ACK input 108.
The K output 208 is output. As a result, the CPU 1
O2 is read normally, and the read data is written into the simulation memory 3 and the read access is completed.

2) Next, during non-simulation and at the time of writing, the CPU 1 outputs the PIO address to the address bus 4, and this address is received by the PIO 2 and the simulation memory 3. Also, CPU1 is R / W1
06 is written and “L” is output.
The / W input 206 receives "L" and is a write instruction, and the R / W input 306 of the simulation memory 3 also receives "L" and is a write instruction. Also, CPU1 is / STB
Output 107 is output, and / STB input 2 of PIO2
07 and / STB input 30 of simulation memory 3
7 is output. Further, the CPU 1 outputs the write data to the data bus 5, and this data is received by the PIO 2 and the simulation memory 3. This is a state where the PIO 2 is being accessed for write, and the PIO 2 writes the write data on the data bus 5 to the PIO. On the other hand, since the simulation memory 3 is also in a write access state, the simulation memory 3 takes in the write data on the data bus 5. Also, PIO2 is / A
The CK output 208 is output, but the acknowledgment switching circuit 1
2 selects the PIO / ACK output 208, and outputs the PIO / ACK to the CPU / ACK input 108.
The output 208 is output. As a result, the CPU 1
2 is normally written, and the write data is written into the simulation memory 3 to terminate the write access.

FIG. 3 shows the operation during the simulation. The simulation mode setting signal 100 is “H”
Thus, the CPU 1 performs PIO read and write.

3) During the simulation and at the time of reading,
The CPU 1 outputs the PIO address to the address bus 4, and this address is received by the PIO 2 and the simulation memory 3. Also, the CPU 1 outputs “H” by using the R / W 106 as a read, and the R / W input 2 of the PIO 2
06 is a read instruction by inputting "H", and the R / W input 306 of the simulation memory 3 is a read instruction by inputting "H". Further, although the CPU 1 outputs the / STB output 107, the simulation mode setting signal “H” is input to the / STB input 207 of the PIO2,
“L” of the / STB output 107 is output only to the / STB input 307 of the simulation memory 3. This is a state where PIO2 is not accessed,
O2 does not output data, nor does the / ACK output 208 output "H". On the other hand, since the simulation memory 3 is in a read access state, the data is output to the CPU 1 via the data bus 5. Also,
The acknowledgment switching circuit 12 outputs / STB1 of the CPU1 output.
07 delay output 308 is selected, the CPU
The delay output 308 is output in response to the / ACK input 108. As a result, the CPU 1 reads the simulation memory 3 normally and ends the read access.

4) Next, during the simulation and at the time of writing, the CPU 1 transfers the PIO address to the address bus 4.
This address is received by the PIO 2 and the simulation memory 3. Further, the CPU 1 has the R / W 106
And write “L” and output R / W of PIO2.
The input 206 and the R / W input 306 of the simulation memory 3 input "L" and are write instructions. Also, CPU
1 outputs the / STB output 107 but does not output it to the / STB input 207 of the PIO 2 but outputs only to the / STB input 307 of the simulation memory 3. Further, the CPU 1 outputs the write data to the data bus 5,
This data is received by the PIO 2 and the simulation memory 3. However, since PIO2 is not accessed, no data is fetched, and / ACK output 20
8 is not output as "H". On the other hand, since the simulation memory 3 is in a write access state,
The write data on the data bus 5 is taken in. The acknowledgment switching circuit 12 outputs the / STB 107 of the CPU 1 output.
Of the CPU / A
The delay output 308 is output in response to the CK input 108. As a result, the CPU 1 stores the simulation memory 3
And the write access ends.

As described above, the CPU 1 can normally access the PIO 2 during the non-simulation and write data to the simulation memory 3 at the same time.
During the simulation, the simulation memory 3 can be accessed normally without accessing the PIO 2.

According to the present embodiment, when the control device is operating in the simulation mode, the data read from the PIO and the data written to the PIO are simultaneously written to the simulation memory. It always matches the data in the simulation memory, so even if you switch from operating in non-simulation mode to simulation mode, you can perform system debugging using the actual data without transferring data as it is. is there.

Next, a second embodiment will be described with reference to FIGS. In this embodiment, the simulation mode setting signal input circuit is one in the first embodiment, and another simulation mode setting signal input circuit is added to increase the number of modes to four. . The simulation mode setting signal A101 and the simulation mode setting signal B102 are connected to the access destination switching circuit 20, and the CPUR / W output 106, the CPU / STB
An output 107, a delay output 308 obtained by adjusting the time of the CPU / STB output 107 by the delay gate 13,
IO / ACK output 208 is connected, and CP
A U / ACK input 108, a PIOR / W input 206,
PIO / STB 207 and simulation memory R /
The W input 306 and the simulation memory / STB input 307 are connected.

The logic of these input and output signals is shown in FIG.
Shown in Simulation mode setting signals A101, B
102, the input / output PIO connection mode, the output only PIO connection mode, the input only PIO connection mode,
Both input and output have four modes of PIO non-connection mode. Further, according to the CPUR / W output 106, there are eight states.

The operation in these eight states will be described with reference to FIGS. FIG. 6 shows an operation in the input / output PIO connection mode. Simulation mode setting signal A10
1 and B102 are both "L", and the CPU 1 performs read access and write access. When both input and output are PIO connected and read, the CPU 1 outputs the PIO address to the address bus 4, and this address is received by the PIO 2 and the simulation memory 3. Also, the CPU 1 outputs “H” by using the R / W 106 as a read, and the R / W input 2 of the PIO 2 is output by the access destination switching circuit 20.
06 is a read instruction by inputting "H", and an R / W input 306 of the simulation memory 3 is "L" input and is a write instruction. Further, the CPU 1 outputs the / STB output 107
Is output by the access destination switching circuit 20.
It is output to the / STB input 207 of O2 and the / STB input 307 of the simulation memory 3. This is the PI
O2 is in a state where read access is performed, and PIO
2 outputs the PIO data to the data bus 5. This data output is received by the CPU 1 and the simulation memory 3. On the other hand, since the simulation memory 3 is in a write access state, the simulation memory 3 takes in the PIO output data on the data bus 5. The PIO 2 outputs the / ACK output 208, but the access destination switching circuit 20 selects the PIO / ACK output 208, so that the CPU / ACK input 10 is output.
8, a PIO / ACK output 208 is output. As a result, the CPU 1 normally reads the PIO 2 and the read data is written into the simulation memory 3,
End the read access. This is the same operation as 1) of the first embodiment.

Next, when both the input and output are PIO connected and at the time of writing, as in 2) of the first embodiment, the CPU 1
, And the write data is simultaneously written into the simulation memory 3 to terminate the write access.

FIG. 7 shows the operation in the output only PIO connection mode. The simulation mode setting signal A101 is "L", the B102 is "H", and the CPU 1 performs read access and write access. When only the output is connected to the PIO and at the time of reading, the PIO is connected similarly to 3) of the first embodiment.
2 does not output anything, the CPU 1 reads the simulation memory 3 and ends the read access. Next, when only the output is connected to the PIO and at the time of writing, the CPU 1 writes data to the PIO 2 as in 2) of the first embodiment, the write data is simultaneously written to the simulation memory 3, and the write access ends.

FIG. 8 shows the operation in the input only PIO connection mode. The simulation mode setting signal A101 is "H", B102 is "L", and the CPU 1 performs read access and write access. When only input is a PIO connection and at the time of reading, as in 1) of the first embodiment, the CPU
1 reads PIO2, the read data is written into the simulation memory 3, and the read access ends. Next, when only the input is a PIO connection and at the time of writing, similarly to 4) of the first embodiment, the CPU 1 does not write to the PIO 2 but writes data only to the simulation memory 3 and ends the write access.

FIG. 9 shows the operation in the PIO non-connection mode for both input and output. Simulation mode setting signal A101
And B102 are both "H", and the CPU 1 performs read access and write access. When both the input and output are not connected to the PIO and read, the PIO is
2 does not output anything, the CPU 1 reads the simulation memory 3 and ends the read access.

Next, when both the input and output are not connected to the PIO and at the time of writing, as in 4) of the first embodiment, the CPU 1
, But write data only to the simulation memory 3 and end the write access.

As described above, in the output only PIO connection mode, the input PIO is unnecessary, in the input only PIO connection mode, the output PIO is unnecessary, and in the input / output PIO non-connection mode, all the PIOs are unnecessary. .

According to the present embodiment, the output-only PIO connection mode is set when no input PIO is installed, the input-only PIO connection mode is set when the output PIO is not installed, and the input / output PIO connection mode is set when all the PIOs are not installed. There is an effect that can be applied to an unfinished plant in three states.

[0064]

According to the present invention, the data read from the PIO and the data written to the PIO when the control device is operating in the simulation mode are simultaneously written to the simulation memory. And the data in the simulation memory always match, so even if you switch from operating in non-simulation mode to simulation mode, you can use the actual data to perform system debugging without changing software or transferring data. It is possible to do.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a first embodiment of the present invention.

FIG. 2 is an operation time chart at the time of simulation of the first embodiment of the present invention.

FIG. 3 is an operation time chart of the first embodiment of the present invention at the time of non-simulation.

FIG. 4 is a block diagram showing a main configuration of a second embodiment of the present invention.

5 is a logic diagram showing a combination example of input / output signals of the access destination switching circuit shown in FIG. 4;

FIG. 6 is an operation time chart showing an operation example of the second embodiment of the present invention.

FIG. 7 is an operation time chart showing an operation example of the second embodiment of the present invention.

FIG. 8 is an operation time chart showing an operation example of the second embodiment of the present invention.

FIG. 9 is an operation time chart showing an operation example of the second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 PIO 3 Simulation memory 4 Address bus 5 Data bus 10 First OR gate 11 First AND gate 12 Acknowledge switching circuit 12A Second OR gate 12B Third OR gate 12C Second AND gate 14 Simulation mode setting signal input Circuit 20 Access destination switching circuit 100 Simulation mode setting signal 101 Simulation mode setting signal A 102 Simulation mode setting signal B

Continued on the front page (72) Inventor Ryuichi Watanabe 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture Within Hitachi Process Computer Engineering Co., Ltd. (72) Inventor Shuichi Nakata 5-2-1 Omikamachi, Hitachi City, Ibaraki Prefecture No. Hitachi Process Computer Engineering Co., Ltd. (72) Inventor Takehiro Asakura 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Examiner, Hitachi Process Computer Engineering Co., Ltd. Yasushi Nakamura (56) References JP 56-94139 (JP, A) JP-A-63-234302 (JP, A) JP-A-62-274436 (JP, A) JP-A-62-99807 (JP, A) U) (58) Field surveyed (Int. Cl. ⁷ , DB name) G05B 23/02 G06F 11/22

Claims (4)

(57) [Claims] 1. A CPU and a direct P connected to the CPU
In a process control device with a PIO simulation memory including an IO input / output device and a simulation memory, at least a control signal circuit of the direct PIO input / output device and the simulation memory is connected to the CPU via an access destination switching circuit. And the access destination switching circuit includes a simulation mode setting signal input circuit, and sets the access destination of the CPU to one of the PIO and the simulation memory according to the state of the simulation mode setting signal. and that switches the circuit to the write data and read data from PIO to both written in the simulation memory, C
PU and direct PIO input / output device and simulation memo
The data bus and address bus connected to the
The above three parties are connected without going through the destination switch circuit.
A process control device with a PIO simulation memory. 2. The process control device with a PIO simulation memory according to claim 1 , wherein the access destination switching circuit includes a plurality of simulation mode setting signal input circuits. 3. An access destination switching circuit comprising: a simulation mode setting signal input circuit; first and second OR gates and an AND gate each having one of the input sides connected to the simulation mode setting signal input circuit; A third OR gate having one of its inputs connected to the circuit via an inverter, and a second AND gate connected to the outputs of the second and third OR gates; The output is connected to the strobe signal input of the simulation memory, the other input of the first OR gate, and the other input of the third OR gate via a delay gate.
The write instruction output is connected to the read / write instruction input of the PIO and the other input of the first AND gate. The output of the first OR gate is connected to the strobe input of the PIO, and the first AND gate is connected to the first AND gate. The output of the gate is connected to the read / write instruction input of the simulation memory, the acknowledge signal output of the PIO is connected to the other input side of the second OR gate, and the output of the second AND gate is the acknowledge signal input of the CPU. 2. The process control device with a PIO simulation memory according to claim 1 , wherein the process control device is connected to the PIO simulation memory. 4. The access destination switching circuit, according to the signal state of the simulation mode setting signal, performs both PIO connection for reading and writing of the CPU, and P
IO connection, CPU write only PIO connection, CP
3. The process control device with a PIO simulation memory according to claim 2 , wherein four modes of reading and writing U and not connecting PIO are selected.