JP2000295295A - Buffer memory for block data transfer and serial data transmission reception system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a buffer memory with a small circuit scale and low power consumption where reduction in a throughput of a processing section with a high throughput is suppressed between processing sections with different throughput. SOLUTION: A buffer provided between processing sections A, B comprises shift registers 10, 20, an input selector section 30, an output selector section 40, a write control section 50 and a read control section 60. Write to the processing section A is conducted by selecting the input selector 30 by the write control section 50, writing data to the shift register 10 and writing data to the shift register 20. Reading from the processing section B is conducted by using the read control section 60 to select the output selector 40, reading data in the shift register 10 and reading the shift register 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a buffer memory for transferring block data, and more particularly to a buffer memory between processing units having different processing speeds.

[0002]

2. Description of the Related Art In recent electronic apparatuses, a plurality of CPUs are used, and a plurality of processings are respectively performed by the CPUs. In the system, there are processing units that must perform processing at high speed and processing units that may perform processing at low speed.

In general, the higher the speed of the processing unit, the more power is consumed. Therefore, in order to increase the processing power of the entire system with low power consumption, it is necessary to prevent the low processing unit from lowering the overall processing performance. It is important to improve the efficiency and transmission capacity of the data transmission part. Conventionally, as shown in FIG.
When performing data transmission between the processing units A and B having different data processing speeds, a method of absorbing a difference in processing speed by placing a storage element (memory) 11 called a buffer between the processing units. . The processing unit A having a high data processing capacity writes data into the buffer 11 and always keeps the buffer from being empty, so that the processing unit B having a low data processing capacity can always read data from the buffer and perform processing. . Conversely, processing unit A having a high data processing capability
The side performs reading so that the buffer 11 does not always become full, so that the processing unit B having a low data processing capability
The side can always write data from the buffer 11. The write control unit 51 switches the input selector 31 by a write signal, the read control unit 61 switches the output selector 41 by a read signal,
〜4 is switched. 71 is FIFD (first
(In-first-out) The memory outputs a status signal such as data full.

[0004]

As described above, by placing a buffer between processing units, a processing unit having a high processing capability can perform processing without being pulled down by the processing speed of a processing unit having a low processing capability. You can continue.

[0005] However, a processing unit having a high processing capacity must constantly monitor the state of the buffer, so that the processing capacity decreases.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an optimal buffer memory capable of suppressing a decrease in processing performance of a processing unit having a high processing capability, having a small circuit size, and reducing power consumption between processing units having different processing capabilities. It is in.

[0007]

The above object is achieved by providing two shift registers which are selectively switched.

[0008] The above-mentioned object is to switch and select 2
Two shift registers, write control means for switching and selecting the write side of the shift register according to the state of the read side and the number of write signals, and switching and selecting the read side of the shift register according to the state of the write side and the number of read signals. This is achieved by providing read control means.

According to the above means, when transmitting block data from the processing section A having a high processing capacity to the processing section B having a low processing capacity, if the two shift registers are set to 10 and 20, writing to the buffer is performed as follows. Assuming that the state on the reading side is the state where the reading of the shift register 10 is completed, the write control means selects the shift register 10 and writes data from the processing unit A. When the number of write signals reaches the number set in the shift register 10 and the state on the reading side is the state in which reading of the shift register 20 is completed, the write control means switches and selects the shift register 20 and writes data from the processing unit A. .

The reading of the processing section B is performed by the reading control means selecting the shift register 10 and reading the data. When the shift register 10 becomes empty and the reading is completed,
The read control means determines that the state on the write side is the write end state of the shift register 20 and the shift register 20
Is selected, and data is read from the processing unit B. In this reading, the number of read signals is
The process is continued until zero data becomes empty.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration diagram of a buffer according to an embodiment of the present invention.

The buffer of the present invention is provided between a processing section A having a high processing capacity and a processing section B having a low processing capacity, and includes a shift register 10, a shift register 20, an input selector section 30, an output selector section 40, It comprises a write control unit 50 and a read control unit 60.

Shift register 10 and shift register 20
Is configured by cascade-connecting registers 1 and 2 and stores written data, and the written data is
They are read in the order written. Now, when the write data W is written to the shift register 10, the data W is written to the register 1 of the shift register 10 and the register 2
Moves data previously written to the register 1. Once again, the write data X is written to the shift register 10.
Is written, data X is written into the register 1 and data W is written into the register 2. When the shift register 10 is read in this state, first, the data W of the register 2 is read, and the data X of the register 1 is moved to the register 2. When the data X is read again from the shift register 10, the moved data X is stored in the register. 2 is read.

The input selector 30 includes a write control unit 50
And the shift register 10 and the shift register 20
Is a switch unit for selecting which of the above data is to be inputted. ANDGATE3,4 performs switch selection. The output selector 40 is a switch unit that is controlled by the read control unit 60 and selects which of the shift register 10 and the shift register 20 outputs data. AN
DGATE5 and DGATE6 select a switch, and data is read through ORGATE7.

The read control unit 60 has a read counter 9 for counting the number of times of reading, and controls the output selector 40 according to the states of the read counter 9 and the write control unit 50. The state transition of the read control unit 60 is as follows.
The transition is as follows. FIG. 2 shows a state transition diagram of the read control unit.

(Reading of shift register 20 is completed)
-> (Reading state of shift register 10)-> (Reading state of shift register 10)-> (Reading state of shift register 20)-> Each state transition condition is as follows: (Reading state of shift register 20) If the state is the write end state of the shift register 20 or the write state of the shift register 10, the state of the read control unit 60 remains at the read end state of the shift register 20, and the state of the write control unit 50 is
If the shift register 10 is in the write end state or the shift register 20 is in the write state, the shift register 10 transitions to the read state.

(Reading state of shift register 10) If the value of the reading counter 9 is 1, the state of the reading control section 60 remains in the reading state of the shift register 10, and
If the value of the read counter 9 is 2, the shift register 1
0 transitions to the read end state.

(Reading of shift register 10 is completed)
If the state of the write control unit 50 is the write end state of the shift register 10 or the write state of the shift register 20, the state of the read control unit 60 is such that the shift register 10 remains in the read end state and the write control unit 50
Is the write end state of the shift register 20 or the write state of the shift register 10, the shift register 20 transits to the read state.

(Read state of shift register 20) If the value of the read counter 9 is 3, the state of the read control unit 60 remains in the read state of the shift register 20,
If the value of the read counter 9 is 0, the shift register 2
0 transitions to the read state.

The output selector 40 controls the output selector 40 to select the shift register 10 and output data from the shift register 10 when the read control unit 60 is in the read state of the shift register 10. or,
When the read control unit 60 is in the read state of the shift register 20, the output selector 40 selects the shift register 20 and outputs data from the shift register 20.

The write control unit 50 has a write counter 8 for counting the number of times of writing, and controls the input selector 30 and controls an external control signal for a write request according to the state of the write counter 8 and the read control unit 60. The state transition of the write control unit 50 transits as follows. FIG. 3 shows a state transition diagram of the write control unit 50.

(Write end state of shift register 20-> (write state of shift register 10)-> (write end state of shift register 10)-> (write state of shift register 20)-> Each state transition condition is as follows. If the state of the read control unit 60 is the read end state of the shift register 10, the state of the write control unit 50 remains at the write end state of the shift register 20, and the read control unit 6
0 indicates that the shift register 10 has finished reading,
Alternatively, if the shift register 20 is in the read state or the read end state, the state shifts to the shift register 10 write state.

(Writing state of shift register 10) If the value of the writing counter 8 is 1, the state of the writing control unit 50 remains in the writing state of the shift register 10, and
If the value of the write counter 8 is 2, the shift register 1
The state transits to the 0 write end state.

(Shift register 10 writing completed state)
If the state of the read control unit 60 is the read end state of the shift register 20, the state of the write control unit 50 remains at the write end state of the shift register 10, and the state of the read control unit 60 indicates that the read of the shift register 20 has been completed. Alternatively, if the reading of the shift register 10 is completed, the shift register 20 transitions to the write state.

(Writing state of shift register 20) If the value of the writing counter 8 is 3, the state of the writing control unit 50 remains in the writing state of the shift register 20, and
If the value of the write counter 8 is 0, the shift register 2
0 transitions to the write state.

The input selector 30 controls the input selector 30 to select the shift register 10 and input data from the shift register 10 when the state of the write control unit 50 is the write state of the shift register 10. or,
When the state of the write control unit 50 is the write state of the shift register 20, the input selector 30 selects the shift register 20 and inputs data from the shift register 20.

The external control signal of the write request is controlled when the write control unit 50 is in the write state of the shift register 10 or the write state of the shift register 20.
Outputs a write request signal.

Next, the operation will be described. In the description, the case where data is transmitted from the processing unit A having a high processing capability to the processing unit B having a low processing capability will be described. The number of block data transfers is two. It is assumed that the read counter 8 and the write counter 9 have been cleared to 0 by default.
The state of the read control unit 60 is determined by the shift register 20.
In the read end state, the state of the write control unit 50 is
It is assumed that the shift register 10 has been initialized to the write end state.

The write operation of the buffer will be described. FIG. 5 shows an operation flowchart of the write operation.
FIG. 6 shows a data operation time chart of the shift register.

The write control unit 50 includes the read control unit 6
Since the state of 0 is the read end state of the shift register 10 (500), the state transits to the write state of the shift register 10. At this point, the state of the reading control unit 60 is
The state shifts to the read state of the shift register 20, and the processing unit B
Is ready for reading. The write control unit 50 switches the input selector 30 to the shift register 10 (5
10), the processing unit A writes the write data W (520). The write data W is selected by the shift register 10 by the input selector 30 and written into the register 1 of the shift register 10. The write control unit 50 increments the write counter 8 and sets the count to 1 (530).

When the processing unit A writes the next write data X, the already written data W moves to the register 2 of the shift register 10, and the write data X is written to the register 1 of the shift register 10. The write control unit 50 increments the counter 8, sets the count to 2, and makes a transition to the write end state of the shift register 10 (540). At this point, the reading control unit 6
The state of 0 transits to the reading state of the shift register 10, and the processing unit B becomes a reading operable state.

Since the state of the read control unit 60 is the read end state of the shift register 20 (550), the write control unit 50 transits to the write state of the shift register 20 and sets the input selector 30 to the shift register 20 ( 560). Since the state of the shift register 20 is empty, a write is requested to the processing unit A (570). The processing unit A writes the write data Y. The write data Y is selected by the input selector 30 and written to the register 1 of the shift register 20. Write control unit 50
Increments the write counter 8 and sets the count to 3 (580).

When the processing unit A writes the next write data Z, the already written data Y is stored in the shift register 2.
The data moves to the register 2 of 0, and the write data Z is written to the register 1 of the shift register 20. The write control unit 50 clears the write counter 8 to 0, and the write control unit 50 transitions to a write end state of the shift register 20 (590). If the processing unit B has not started reading data, the state of the reading control unit 60 is the reading state of the shift lens 10.
Starts the reading operation, and the state of the reading control unit is
The writing operation is stopped until the reading of the shift lens 10 is completed.

The operation of reading data into the buffer will be described. FIG. 4 shows a flowchart of the reading operation.

When the processing section B starts the reading operation,
The data W of the register 2 of the shift register 10 is read. When read, the data X in the register 1 of the shift register 10 is moved to the register 2. The read control unit 60 increments the read counter 9 and sets the count to 1 (410).

When the processing section B performs the next reading operation,
Since the data X in the register 1 of the shift register 10 has been moved to the register 2 in the previous read operation, the data X is read. The count of the reading counter 9 is set to 2 (420). Since the shift register 10 is empty (430), the read control unit 60 sets the output selector 40 to select the shift register 20 (440). The write control unit 50 issues a write request to the processing unit A because the shift register 10 has become empty.

When the processing section B performs the next reading operation, the data Y in the register 2 of the shift register 20 is read. Data Z of register 1 of shift register 20
Moves to register 2. The reading control unit 60 sets the reading counter 9 to count 3 (450). When the processing unit B performs the next reading operation, the data Z is read from the register 2 of the shift register 20. The count of the reading counter 9 is set to 0 (460).
The reading of the shift register 20 ends (470).
The output selector 40 is set to select the shift register 10 (400).

As described above, by using the buffer constituted by the two shift registers, data can be transmitted to a processing unit having a low processing capability without dropping data. Further, since a processing unit having a high processing capability can also perform block data transfer, it is possible to prevent a reduction in processing capability.

FIG. 8 shows an example in which the buffer memory of the present invention is applied to a system for transmitting and receiving serial data at a constant speed (10 Mbps). In the embodiment, the MPU 600
Side data bus width is 32 bits and read / write cycle is 2
Cycle (1 cycle = 1/20 MHz), M
The data transfer speed (data processing speed) on the PU side is 32 bits × (１ ／ cycle) × 20 MHz = 320 bps,
The data transfer rate of the serial transmission / reception processing unit 800 is 10
Mbps. The data transfer between the different data processing speed systems is performed via the buffer 100 of the present invention.

The serial transmission / reception processing unit 800 reads / writes data from / to the buffer at a constant speed. The serial transmission / reception processing unit includes a serial transmission control unit 810, a serial reception control unit 840, a transmission parallel / serial conversion unit 820,
It comprises a receiving serial / parallel converter 830.

Serial transmission control section 810 outputs a transmission request to MPU 600, reads data from transmission buffer 110 while monitoring the state of transmission parallel / serial conversion section 820, and transmits transmission parallel / serial conversion section 82.
Write to 0. Transmission parallel / serial converter 820
Converts the written parallel data to serial,
Output serial data.

Serial reception control section 840 outputs a reception request to MPU 600, and writes the data of reception serial / parallel conversion section 830 to reception buffer 120 while monitoring the state of reception serial / parallel conversion section 830. The reception serial / parallel converter 830 converts the written serial data into parallel data.

The DMA unit 700 arbitrates between the MPU 600 and the data bus 1000, and
00 is performed. The DMA unit 700 transmits
It comprises an MA control register section 710, a reception DMA control register section 740, a transmission DMA section 720, and a reception DMA section 730.

The transmission DMA control register 710 includes an MPU
A memory 900 for data to be set and transmitted by 600
Is a register in which information on the storage address and the number of transfers is stored.
Is a register that stores information on the storage address of the received data in the memory 900 and the number of transfers of the received data.

The transmission DMA unit 720 is activated when the transmission DMA control register 710 is set, monitors the state of the transmission buffer control unit 110, and writes the transmission buffer 110 in a writable state (when one of the two transmission shift registers is In the empty state), the MPU 600 requests the data bus to be released, and when the release of the data bus is recognized from the MPU 600, the transmission DM is transmitted from the memory 900 to the transmission buffer unit 110.
The writing operation is performed intermittently until the transfer number of the A control register 710 is written.

The reception DMA unit 730 is activated when the reception DMA control register 740 is set, monitors the state of the reception buffer control unit 120, and reads the reception buffer 120 (when either of the two reception shift registers is in the read state). When the MPU 600 requests the release of the data bus at the time of (full state), and the release of the data bus is recognized from the MPU 600, the reception buffer unit 120 sends the reception D to the memory 900.
The reading operation is performed intermittently until the transfer number of the MA control register 740 is read.

The MPU 600 has a serial transmission / reception controller 80
The setting of the DMA 700 is performed by a control signal from 0.
The memory 900 stores transmission / reception data. Buffer 1
00 is the transmission buffer unit 110, the reception buffer unit 120
The transmission buffer unit 110 includes a memory 600
Is a buffer that transfers data from the serial transmission unit 800 to the serial transmission / reception unit 800. The reception buffer unit 120 is a buffer that transfers data from the serial transmission / reception processing unit 800 to the memory 600.

The operation when transmitting serial data will be described.

At the timing of transmission by the serial transmission / reception processing unit 800, the serial transmission control unit 810 issues a transmission request to the MPU 600. The MPU 600 sets the transmission DMA control register 710 (designates the address of the data to be transmitted and the number of transmission data), and sets the transmission DM of the DMA unit 700.
The A section 720 reads the transmission DMA control register 710, requests the MPU 600 to release the data bus if the state of the transmission buffer 110 is writable, and if the release is recognized, one shift register of the transmission buffer 110 is full. Write data until. Also, the value of the transmission DMA control register 710 is updated simultaneously with the write operation. After the writing is completed, the data bus is released to the MPU 600. After releasing the data bus to MPU 600,
If the transfer for the number of transfers in the MA control register 710 has not been completed, the data bus is released to the MPU 600 again, and the transmission buffer 110 is transferred until the transfer for the transfer is completed.
Write to.

The serial transmission control section 810 of the serial transmission / reception processing section 800 reads data from the transmission buffer 110. The serial transmission control unit 810 performs a read operation from one of the shift registers, and the other shift register performs a read operation. If the read operation is completed, the DMA unit 700 completes the read operation of the transmission buffer 110. Write operation to one of the shift registers. If the reading of both shift registers has not been completed, the DMA unit 700 does not perform the writing operation.

The operation at the time of receiving serial data will be described.

At the timing of reception by the serial transmission / reception processing unit 800, the serial reception control unit 840 issues a reception request to the MPU 600. The MPU 600 sets the reception DMA control register 740 (designates the address of the data to be received and the number of received data). And the reception DM of the DMA unit 700
The A unit 730 reads the reception DMA control register 740, and requests the MPU 600 to release the data bus if the state of the reception buffer 120 is readable. If the release is recognized, one shift register of the reception buffer 120 becomes empty. Read data until. At the same time as the reading operation, the value of the reception DMA control register 740 is updated. After the reading is completed, the data bus is released to the MPU 600. After releasing the data bus to the MPU 600,
If the transfer for the number of transfers in the A control register 740 has not been completed, the data bus is released to the MPU 600 again, and the reception buffer 120 is transferred until the transfer for the transfer is completed.
To read

The serial reception control section 840 of the serial transmission / reception processing section 800 writes data in the reception buffer 120. If the serial reception control unit 840 performs a write operation from one of the shift registers, and if the other shift register has completed writing, the DMA unit 7
00 performs a read operation from one of the shift registers for which writing to the reception buffer 120 has been completed. If both shift registers have not been written, DM
A section 700 does not perform a reading operation.

As described above, by configuring the buffer 100 with two shift registers, when one of the shift registers is used for the read operation, one of the shift registers can be used for the write operation. Also, since the shift register is used, reading and writing can be performed at high speed, and complicated control is not required.

Such a system is generally used for FIFO (first-in first-out).
Although it can be realized by a memory, the present invention is much smaller in comparison with the circuit scale, and lower power consumption is possible. For example, comparing the configuration with four registers, in the present invention, the number of gates of the input selector is two, the number of gates of the output selector is two, and in the FIFO, the number of gates of the input selector is four and the number of gates of the output selector is four. And the number of gates of the selector is 2/4. Further, in this description, the number of registers is compared with four for simplicity of description, but the effect increases as the number of registers increases. When the number of registers is 32, the number of gates of the selector is 2/32.

[0057]

As described above, according to the present invention, by using a buffer composed of two shift registers, data can be transmitted to a processing unit having a low processing capability without missing data. Since a processing unit having a high processing capability can also perform block data transfer, it is possible to prevent a reduction in processing capability.

Further, when one of the two shift registers is used for the read operation, the other shift register can be used for the write operation, so that the read / write operation can be performed at high speed without complicated control. it can.

Further, since a shift register having a simple circuit is used, the circuit scale is small and the power consumption is low.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a buffer according to an embodiment of the present invention.

FIG. 2 is a state transition diagram of a reading control unit according to the present invention.

FIG. 3 is a state transition diagram of a write control unit of the present invention.

FIG. 4 is a flowchart of an internal operation of buffer reading according to the present invention.

FIG. 5 is a flowchart of a buffer write internal operation according to the present invention.

FIG. 6 is a data operation time chart of a shift register.

FIG. 7 is a configuration diagram of a transmission / reception system according to an embodiment using the buffer of the present invention.

FIG. 8 is a configuration diagram of a buffer using a conventional FIFO.

[Explanation of symbols]

1, 2, ... register, 3, 4, 5, 6, ... AND gate, 7
... OR gate, 8 write counter, 9 read counter, 10 and 11 shift register, 30 input selector, 40 output selector, 50 write control unit, 6
0: read control unit, 100: buffer unit, 110: transmission buffer, 120: reception buffer, 600: MPU,
700 ... DMA, 710 ... Transmission DMA control register, 7
20: transmission DMA unit, 730: reception DMA unit, 740:
Receive DMA control register, 800: serial transmission / reception processing unit, 810: serial transmission control unit, 820 transmission parallel / serial conversion unit, 830: reception serial / parallel conversion unit, 840: serial reception control unit, 900: memory,
1000 Data bus.

Claims (3)

[Claims] 1. Blocks between processing units having different processing capacities.
A block memory provided for data transfer, comprising: two shift registers that are selectively switched. 2. Blocks between processing units having different processing capacities.
In a buffer memory provided for data transfer, two shift registers to be switched and selected, write control means for switching and selecting the write side of the shift register according to the state of the read side and the number of write signals, and reading of the shift register A block memory for block data transfer, comprising: read control means for switching and selecting the side according to the state of the write side and the number of read signals. 3. A serial data transmission / reception system, wherein the block data transfer buffer memory according to claim 1 or 2 is provided in a transmission buffer for transmitting / receiving serial data and a reception buffer.