KR101128898B1 - Direct memory access controller, system and method for transferring a data using the same - Google Patents

Abstract

The present invention is to provide a data transmission system and a transmission method using a DMA control device for stably performing a direct memory access (Direct Memory Access, DMA) operation even in the input and output device that the data transmission once every specific period, To this end, the present invention provides a DMA request unit for generating a DMA request signal in response to a DMA request input from a timer inside the MCU, a memory according to the DMA request signal, and data transmission / reception for a predetermined period in response to the value of the timer. Provided is a DMA control apparatus including a DMA control unit for performing DMA transfer between external input / output devices.

DMA, LCD, MCU, Timer, FSM, Run Length Data

Description

DIRECT MEMORY ACCESS CONTROLLER, SYSTEM AND METHOD FOR TRANSFERRING A DATA USING THE SAME}

1 is a block diagram showing a configuration of a data transmission system shown for explaining a direct memory access control apparatus according to a preferred embodiment of the present invention.

2A and 2B illustrate a DMA request signal and a channel selector shown in FIG. 1;

FIG. 3 is a flowchart illustrating a DMA data transfer method of a first channel (channel 0) and a second channel (channel 1) to which a DMA request signal DRQ and a register DMA request signal DMRQR are allocated.

4 is a flowchart illustrating a runlength data processing method using a third channel (channel 2) and a fourth channel (channel 3) to which the DMA request signals Timer0 to Timer7 and the register DMA request signal DMRQR are allocated.

<Explanation of symbols for the main parts of the drawings>

10: MCU

20: timer

30: DMA controller

40: memory

50: input / output device

31: priority generation unit

32: DMA request signal and channel selector

33: DMA control unit

34: register counting unit

35: register

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system and a transmission method using a direct memory access (DMA) control device. In particular, a SOC (System On Chip) reads data stored in an internal memory or an external memory, The present invention relates to a data transmission system and a transmission method using a direct memory access control apparatus which transmits data to a specific block inside, or reads and writes data of a specific block inside a chip into a memory.

In general, a direct memory access (hereinafter, referred to as DMA) controller is configured to transfer data into an internal or external block, for example, a memory set in an internal buffer of a request block in response to a request of an input / output (I / O) device. Transfer data from the memory to the buffer of the request block. The request block is configured with a FIFO (First In First Out) as a buffer to store several data inside. When enough data is stored in the FIFO buffer for transfer to memory, or empty enough to retrieve data from memory and store the data, the request block requests data transfer to the DMA controller.

This DMA operation is continued until all the data of the size set in advance in the DMA controller is transmitted. When all data is transferred through the DMA controller, the DMA controller generates an interrupt to notify the central processing unit (CPU) or the micro controller unit (MCU) that the data transfer of the preset size is completed. The CPU receives this interrupt and branches to determine whether to send further data to the DMA controller or to perform another sequence of operations.

Such a general DMA controller is used for data transmission with a block that periodically transmits and receives data of a specific size once every specific time, such as a liquid crystal display (LCD) device or a block that needs to transmit and receive data at regular intervals, such as an electronic sign. The efficiency is reduced. Accordingly, when the CPU is used to perform data processing with a block such as an LCD device instead of the DMA controller, it receives a counter output and transmits and receives data once every specific time (or period). In the meantime, the central processing unit cannot perform any other operation, which causes a problem of deteriorating the overall operating characteristics.

Therefore, in order to reduce the burden on the central processing unit, if a DMA operation is to be performed by using the DMA controller, a counter (or timer) is configured in the block requiring the DMA operation, and this counter is used periodically. In other words, data stored in the memory should be transferred to the FIFO buffer through the DMA controller, or periodically the data in the block should be stored in the FIFO buffer and then the data stored in the FIFO buffer should be transferred to the memory using the DMA controller. However, even in this case, a counter must be configured inside the request block, and a separate control circuit for controlling the FIFO buffer by using the counter is required.

Also, in the electronic board, most background data except for characters have the same value. Nevertheless, conventionally, the same data has been transmitted every time. This causes a problem of occupying the memory area and occupying the bus. In addition, when using a plurality of electronic plates together, there is a problem that a plurality of external devices and a DMA control device are required. In addition, if the processor is implemented using a processor such as a CPU or an MCU instead of the DMA device, the processor must continuously manage data transmission periodically, which may cause interruption when performing other tasks, which may cause a decrease in processing performance. .

Accordingly, an object of the present invention is to provide a DMA control apparatus that can stably perform a DMA operation even in an input / output device in which data transmission is performed once every specific period. .

In addition, the present invention provides a DMA control apparatus capable of processing run length encoded data in which the same data is repeated, thereby reducing performance degradation and power loss due to repetitive data transmission. There is a purpose.

In addition, the present invention enables data transfer to a destination having up to four destination addresses for one DMA request for one source address, thereby maximizing external devices requiring different data in the same period. Another object is to provide a DMA controller capable of handling data transfer by connecting up to four.

In addition, the present invention is to provide a DMA control device having a high utilization for a wide range of source address and destination address by controlling any device in the MCU having a configurable source address and destination address to enable DMA transfer. have.

Another object of the present invention is to provide a data transmission system and a transmission method using the DMA control apparatus.

According to an aspect of the present invention, a DMA request unit generates a DMA request signal in response to a DMA request input from a timer inside the MCU, a memory according to the DMA request signal, Provided is a DMA control apparatus including a DMA control unit for performing a DMA transfer between the external input and output devices for data transmission and reception for a predetermined period corresponding to the value.

According to another aspect of the present invention, there is provided a memory including: a memory in which data is stored, a first input / output device for performing DMA transfers at predetermined intervals with the memory, and the memory or the first input / output device; In order to set a counter value corresponding to the period through the internal timer and the second input-output device in which the DMA transfer is made according to the first DMA request, and perform the DMA transfer between the memory and the first input-output device every cycle. An MCU for setting a DMA address, the first DMA request, and a second DMA request input from the timer, and assigning channels to the first and second DMA requests, respectively, according to a priority of the channels; A DMA request unit which selects one channel and outputs a DMA request signal of the selected channel, and the channel selected in response to the DMA request signal; Wherein using the DMA address provides a data transfer system including the memory, DMA controller for performing DMA transfers between the first and second input-output device.

According to another aspect of the present invention, there is provided an internal register including a first input / output device in which data is transmitted at regular intervals, a second input / output device in which data is transmitted on request, and a DMA address of a memory. Set to a second DMA request input from a timer inside the MCU corresponding to the first input / output device, a second DMA request input from a second input / output device, and a third DMA request input from an internal register. Receiving an input through a DMA request unit, selecting one of the first to third DMA requests according to priority, and generating a channel selection signal and a DMA request signal, and the DMA request signal and the channel selection signal. And performing a DMA transfer between a memory, a first and a second input / output device using the DMA address through a DMA controller. It provides a data transmission method.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

Example

FIG. 1 is a block diagram illustrating a DMA control apparatus according to a preferred embodiment of the present invention. Here, a data transmission system having four channels is illustrated for convenience of description.

Referring to FIG. 1, a DMA control apparatus according to a preferred embodiment of the present invention includes a priority generator 31, a DMA request signal and channel selector 32, a DMA controller 33, a register counting unit 34, and A register 35.

The priority generator 31 receives the DMA request signals DRQ0 and DRQ1 and Timer0 to Timer7 from the MCU 10 and an external chip (or device) to the DMA request signal and the channel selector 32 through an internal bus. When input at the same time, one of these DMA request signals is accepted to determine whether to perform data processing. To this end, the priority generation unit 31 generates four priority determination signals pr0 to pr3 corresponding to four channels, and outputs them to the DMA request signal and the channel selector 32. Here, 'DRQ0 and DRQ1' are DMA request signals input from a chip or an external device installed outside the MCU 10, and 'Timer0 to Timer7' are preset by the timer 20 inside the MCU 10 and are fixed. It is a DMA request signal that occurs every cycle.

The DMA request signal and the channel selector 32 are the DMA request signals DRQ0 and DRQ1 and Timer0 to Timer7 input through the internal bus according to the priority determination signals pr0 to pr3 input from the priority generation unit 31. One of the DMA request signals is selected to generate and output a selected internal DMA request signal dma_req and a channel select signal (ch-sel) of the DMA request signal.

The internal DMA request signal dma_req can be obtained through the configuration as shown in FIG. 2A.

First, the DMA request signals DRQ0 and DRQ1 and Timer0 to Timer7 are assigned to four channels, respectively. The external DMA request signals DRQ0 and DRQ1 are DMA request signals input to an external device regardless of the MCU 10 and are allocated to the first channel and the second channel of the four channels, respectively. Since the DMA operation by the external DMA request signals DRQ0 and DRQ1 is performed in the same manner as the general DMA operation, it will be briefly described for convenience of description.

The DMA request signals Timer0 to Timer7 are signals allocated to the third and fourth channels except for the first and second channels of the four channels, and are input through the MCU 10 through a timer 20 for a predetermined period. Request signal. For example, as shown in the drawing, eight DMA request signals Timer0 to Timer7 are allocated to two channels, and among the eight DMA request signals Timer0 to Timer7, the register setting signals DMICR1 and DMICR2 are assigned. Each one is selected and assigned to the third and fourth channels. Here, the register setting signals DMICR1 and DMICR2 are signals set in advance by the user and stored in the register 35, and are signals for selecting any one of the DMA request signals Timer0 to Timer7.

Referring to the operation characteristics, when the DMA request signals DRQ0 and DRQ1 and Timer0 to Timer7 are simultaneously input, the DMA request signal of the DMA request signals Timer0 to Timer7 by the timer 20 is first converted into a register setting signal ( DMICR1, DMICR2) are used to select through the mux (multiplexer, MUX1, MUX2). The DMA request signals selected through the muxes MUX1 and MUX2 are input to the muxes MUX3 and MUX4, respectively. The mux (MUX3, MUX4) selects one of the selected DMA request signal and the DMA request signal (DMRQR), which is a request signal of the internal register, by using the internal register setting signals (DMICR1, DMICR2) and assigns them to the third channel and the fourth channel. . In this case, the third channel and the fourth channel support only a single transmission mode.

On the other hand, the external DMA request signals DRQ0 and DRQ1 are input to OR gates OR1 and OR2, respectively. The OR gate OR1 receives the DMA request signal DRQ0 and the DMA request signal DMRQR by internal register setting, and outputs the result of the OR operation. The OR gate OR2 receives the DMA request signal DRQ1 and the DMA request signal DMRQR by an internal register, and outputs the result of the OR operation. At this time, the output signals of the OR gates OR1 and OR2 are allocated to the first channel and the second channel, respectively. The first and second channels respectively receive external DMA request signals DRQ0 and DRQ1 or DMA request signals DMRQR to perform DMA operations between the memory and the input / output device, or bind two channels to perform DMA operations between the memory and the memory. Is provided for.

This is because only one address is allocated to each channel. In general, since only one address of the source address and the destination address is required between the memory and the input / output device, DMA transfer is possible using only one channel. However, the DMA transfer between the memory requires two addresses, such as a source address and a destination address, and therefore, DMA transfer is impossible with only one channel. Therefore, it is possible to perform DMA transfer between the memory by tying two channels together.

In addition, the first channel and the second channel can be used for three functions of single transmission, block transmission, and request transmission. In the single transmission, when only one data is transmitted when a DMA request is generated, the DMA request is terminated and waits for the next DMA request. When the DMA transfer is started, the block transfer consists of an operation of transferring a continuous data block by the size of the DMA data transfer set in a register inside the DMA controller. The request transmission is performed only by the external DMA request signals DRQ0 and DRQ1, and continues to perform the DMA operation until the external DMA request signals DRQ0 and DRQ1 are disabled.

The DMA request signals selected through the OR gates OR1 and OR2 and the mux MUX3 and MUX4 are input to the corresponding AND gates AND1 to AND4, respectively. The AND gates AND1 to AND4 select one of the DMA request signals according to the channel select enable signal DMER. That is, when the channel select enable signal DMER is enabled at the high level '1', all of the DMA request signals are selected, and when the channel selection enable signal DMER is enabled at the low level '0', the DMA All request signals are not selected. However, this is an example, and the circuit may be changed appropriately so that only one of the four channels is selected so that only the DMA request signal assigned to that channel is selected. Here, the channel select enable signal DMER is set by the user.

The DMA request signals selected through the AND gates AND1 to AND4 are input to the four muxes MUX5 to MUX8, respectively, and the muxes MUX5 to MUX8 are the priority determination signals pr0 inputted from the priority generation unit 31. To pr3) to select and output each one.

The OR gate OR3 logically outputs the request signals pr0_req to pr3_req selected from the muxes MUX5 to MUX8, respectively. The OR gate OR3 enables and outputs the internal DMA request signal dma_req when any one of the request signals pr0_req to pr3_req whose priority is determined by the priority determination signals pr0 to pr3 is output at a high level. do.

Meanwhile, the channel selection signal ch_sel is generated through the configuration as shown in FIG. 2B.

As shown in FIG. 2B, the channel selection signal ch_sel is generated using the request signals pr0_req to pr3_req (see FIG. 2A) selected by the priority determination signals pr0 to pr3.

Any one of the muxes MUX9 to MUX12 is selected according to the request signals pr0_req to pr3_req. The mux selected by the request signals pr0_req to pr3_req selects and outputs any one of the priority determination signals pr0 to pr3 and '00' data. Data selected by the mux MUX9 to MUX12 is input to the OR gate OR4. OR gate OR4 outputs the OR of data input from mux MUX9 to MUX12.

For example, when the priority determination signal pr0 is selected and output by the mux MUX9, the OR gate OR4 outputs a channel selection signal ch_sel for selecting a channel corresponding to the priority determination signal pr0. do. Of course, not all channels are selected simultaneously in all muxes MUX9 to MUX12. As shown in the drawing, each of the muxes MUX9 to MUX12 use different request signals pr0_req to pr3_req, that is, the mux 9 uses the 'pr0_req' signal, and the mux MUX10 uses the '! Pro_req & pr1_req' signal. MUX11 uses '! Pr0_req &! Pr1_req & pr2_req' signal, and MUX12 uses '! Pr0_req & pr1_req &! Pr2_req & pr3_req' so that only one is selected.

The DMA controller 33 includes a function of a finite state machine (FSM), and receives the internal DMA request signal dma_req and the channel select signal ch_sel from the DMA request signal and the channel selector 32, and overall the DMA transmission. Control the operation. Of course, although not shown, the DMA controller 33 may exchange a predetermined signal with other elements implemented in the chip through a separate internal bus. The operation may be controlled by this signal.

When the internal DMA request signal dma_req and the channel select signal ch_sel are input to the DMA request signal and the channel selector 32, the DMA controller 33 determines whether the DMA request signal dma_req is a request signal from an external device. Otherwise, after determining whether the request signal is set by the timer 20, the overall operation is controlled to perform DMA data transmission through the selected channel.

In addition, the DMA control unit 33 manages the overall processing including encoding or decoding of run length data. The run-length data is data having the same value for a predetermined time, such as most background data except characters in the electronic display board, and is stored in the run-length register (not shown) of the register 35 in the state encoded by the MCU 10. . The encoded run length data is hereinafter referred to as run length encoded data. When the request signal for the run length encoded data stored in the run length register is received, the DMA controller 33 reads the run length encoded data from the run length register and transmits the received length encoded data to the destination.

For example, in the case of a DMA request signal from an external device, a single transmission, block transmission, and request transmission are performed in a general manner. In the case of the DMA request signal by the timer 20, data is transferred from the memory 40 to the input / output device 50, the input / output device 50 to the memory 40, or the memory for the period set in the timer 20 in a single transmission. Controls overall operation to transfer data from memory to memory. Here, the input / output device 50 is a device with a built-in memory such as a register, a device without a built-in memory, or a memory device. In addition, the input / output device 50 is a device that performs data transmission and reception for a predetermined period.

Meanwhile, when the input / output device 50 is a memory mapped device, the first channel and the second channel are allocated by the DMA request signals DRQ0 and DRQ1 to perform the corresponding memory and DMA operations. The priority of the four channels may be set to be divided into two levels of high priority and low priority for each channel. At this time, before the DMA request signals DRQ0 and DRQ1 are input, the address of the peripheral input / output device 50 is preset in the register 35 by the MCU 10. The DMA data transfer is performed between the memory 40 and the input / output device 50 through the address set as described above. This DMA operation is performed by single transmission, block transmission, and request transmission.

In addition, when the input / output device 50 is a device that transmits and receives data for a predetermined period, the third channel and the fourth channel are allocated by the request signals Timer0 to Timer7 that are set and input for a predetermined period by the timer 20. Each cycle performs the memory and DMA operation. When the corresponding memory and the corresponding input / output device are determined through the source address and the destination address initially set by the MCU 10, data transmission between the corresponding memory and the corresponding input / output device is performed using an internal bus only for the corresponding address. That is, in this case, the DMA operation is performed in a single transmission method.

The register counting unit 34 is an apparatus for controlling the overall operation of the register 35. The register counting unit 34 may control an address value set in the register 35 by a control signal input from the MCU 10 or a control signal by the timer 20. Counting. A DMA control apparatus according to a preferred embodiment of the present invention provides DMA transfer with four I / O devices in one channel. In this case, the destination address set in the register 35 is counted by the register counting section 34 and sequentially selected. Therefore, four destination addresses are selected by one source address, and data transmission to the I / O device having each destination address is possible. At this time, the I / O devices should be devices having the same data transmission timing. In this way, it is possible to reduce the number of separate controllers from a maximum of four to one.

In the register 35, the addresses of the peripheral input / output devices 50 are set and stored by the MCU 10. These addresses are counted by the register counting section 34 and appropriately selected. In addition, when the internal DMA request signal 33 is input from the DMA control unit 33, the DMA data transmission is performed between the memory and the I / O device. For example, when the DMA request signal DRQ0 is input from the I / O device, the register 35 selects the memory 40 having the corresponding source address according to the internal DMA request signal selected from the DMA controller 33, and then selects the selected memory ( The data of 40) is transferred to the I / O device having the destination address.

Hereinafter, a data transmission method using a DMA control apparatus according to a preferred embodiment of the present invention shown in FIGS. 1, 2A and 2B will be described with reference to FIG. 3. 3 is a flowchart illustrating a DMA data transfer method of a first channel (channel 0) and a second channel (channel 1) to which a DMA request signal DRQ and a register DMA request signal DMRQR are allocated.

Referring to FIG. 3, first, a DMA controller receives DMA request signals DRQ and DMRQR input in a DMA request standby state, and whether the input DMA request signal is a DMA request signal between the memory and the I / O device, It is determined whether the DMA request signal between the memories (S31 to S33).

If the DMA request signal is a DMA request signal between the memory and the I / O device in step S33, DMA transfer is performed between the memory and the I / O device through a single channel using the DMA address (S34). Here, the DMA address is stored in the register 35 in advance by the MCU 10. This DMA address becomes an address of an I / O device or an address of a memory.

If the DMA transmission is a single transmission, or there is no request transmission and an external request, when one DMA request signal is generated, only one data corresponding to one address is transmitted and then the transmission is terminated (S35 and S42). On the other hand, in the case of block transmission, after the DMA transmission is performed until there is no remaining data, the transmission is terminated when the data is transmitted in mode (S35, S36, S42).

On the other hand, when the DMA request signal is a DMA request signal between the memory and the memory in step S33, the DMA transfer is performed between the memory and the memory through two channels (channels 0 and 1) using the DMA source address and the destination address. (S38, S39). Since the DMA transfer between the memory requires two addresses, such as a source address and a destination address, two channels are used for this purpose, that is, the first channel (channel 0) and the second channel (channel 1).

First, when data is to be transferred between the source memory and the destination memory, the source memory is selected by using the source address set in the register 35 by the MCU 10 in advance through the first channel (channel 0), and stored in the memory. Enter the data. Thereafter, the destination memory is selected using the destination address set in the register 35 by the MCU 10 through the second channel (channel 1) to perform single transmission, request transmission or block transmission (S38 to S40). .

If there is no single transmission or request transmission and external request in step S40, the DMA data is transmitted to the destination memory through the second channel (channel 1). This DMA data transfer is carried out until no residual transfer exists (S40 to S42). On the other hand, in the case of block transmission, data is transferred to the destination memory through the second channel (channel 1) and then the source memory is selected using the source address inputted through the first channel (channel 0) to perform DMA data transfer. . This DMA data transfer is repeatedly performed until all data in the block is transferred (S40, S43, S44).

When the DMA data transfer is completed between the memory and the I / O device or the memory and the memory, the DMA controller 33 generates an interrupt signal and transmits the signal to the MCU 10 to inform that the DMA transfer is completed (S37).

Hereinafter, a run length data processing method using a DMA control apparatus according to a preferred embodiment of the present invention shown in FIGS. 1, 2A, and 2B will be described with reference to FIG. 4. 4 illustrates a run length data processing method using a third channel (channel 2) and a fourth channel (channel 3) to which the DMA request signals Timer0 to Timer7 and the register DMA request signal DMRQR are allocated. It is a flow chart. This operation is also performed by the DMA controller 33.

Referring to FIG. 4, first, the DMA controller 33 determines whether the DMA request signals DMRQR (Timer0 to Timer7) are generated in the DMA request wait state. Then, it is determined whether the corresponding channel is allocated as a channel for run length data processing by user setting (S51 to S53).

If the corresponding channel is activated as a channel for processing the run length data in step S53, it is determined whether the encoding portion exists by analyzing the run length encoding data stored in the run length register (S54). For example, when the run length data 'aaaaaabbbcdeffffghiii' is encoded and converted into the run length encoded data, it becomes '-6a-3b3cde-4f2gh-3i'. Here, '-' represents the number of repetitions of data that is continuously repeated as a portion encoded as data that is continuously repeated. '+' Is general data that is not repeated continuously and indicates the length of the general data. In this way, one bit of run-length data is used to represent the number of consecutive data repetitions or the general data length. In this case, the least significant bit is used so that the normal data length is equal to '0' and the same is equal to '1'. The repeat count of the data is shown. The remaining value minus this least significant bit actually represents the number of occurrences of the normal data or the same repeated data, and is stored in an internal register. While this value is not '0', the DMA controller 33 decreases the register value after performing a memory-to-memory transfer in case of normal data according to a DMA request, or runs data without data transfer in case of repeated data. Decreases the register value. As described above, a total of 21 bytes are required for DMA transmission without encoding run length data, but a total of 15 bytes is required for transmission with run length encoding. That can reduce the number of bytes transmitted.

In operation S54, the run length data register DMRLR is checked to determine whether the data stored in the register DMRLR is run length encoded data.

In the case of general data that is not repetitive in step S54, the data is read and the read value is stored in a register to perform a single DMA data transfer. Herein, as described above, the general data reading method determines whether the least significant bit of the run length data is '0' or '1'. For example, when the least significant bit is '0', it is determined as normal data, and when it is '1', it is determined as data that is continuously repeated.

On the other hand, in the case of run length data that is continuously repeated in step S54, it is determined whether the run length data is encoded data (S57). In the case of the encoded data, the run length data is not transmitted and the value of the run length data register DMRLR is increased by one (S58).

On the other hand, when run length encoding is activated in step S53 or not encoding data in step S57, DMA transfer is performed in the same manner as general data (S61 to S65). Since the DMA transfer is performed in the same manner as described in FIG. 3 using the third channel (channel 2) and the fourth channel (channel 3), a description thereof will be omitted.

In the above, when the DMA transfer is completed, an interrupt signal is generated to inform that the DMA transfer is completed (S60).

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, by using the MCU internal timer output as a DMA request, the DMA controller can be used without the processor's interference not only for data transmission but also for periodic data transmission such as LED / LCD control. There is an advantage.

In addition, according to the present invention, by analyzing the DMA transfer data through the DMA control unit to process the run-length encoded data enables processing of the run-length encoded data in which the same data is repeatedly performed, thereby reducing performance due to repeated data transfer and Power loss can be reduced.

In addition, according to the present invention, by enabling the use of multiple destination addresses for a single source address in the DMA transfer between the memory and the memory, it is possible to transfer different or identical data to multiple data requesting apparatuses through various combinations.

Claims (42)

A DMA request unit that responds to a plurality of DMA requests input from a timer inside the MCU, and determines a priority of the plurality of DMA requests to generate a DMA request signal according to the priorities; And A DMA controller for performing DMA transfer between a memory and an external input / output device that transmits and receives data for a predetermined period in response to a value of the timer according to the DMA request signal; DMA controller comprising a. The method of claim 1, And the DMA request unit selects one of the plurality of DMA requests and allocates one channel. The method of claim 2, And the DMA request unit selects one of the plurality of DMA requests by the timer according to a register setting signal set by a user and stored in a first register. The method of claim 3, wherein And the DMA request unit selects one of the selected DMA request and a DMA request of a second register configured in the MCU using the register setting signal. The method of claim 1, The DMA request unit receives a DMA request directly from another external input / output device in addition to the plurality of DMA requests by the timer, and selects one of the provided DMA request and a DMA request from a register to allocate one channel. DMA controller. The method according to any one of claims 3 to 5, And the DMA requesting unit selects any one of the channels according to a priority set by a user. The method of claim 1, And the DMA control unit performs DMA transfer between the memory and the external input / output device using the DMA address set by the MCU. The method of claim 5, The DMA control unit performs a DMA transfer in a block transfer method for transmitting a continuous data block by the DMA transfer size set in the register when the DMA transfer is started by the corresponding DMA request. The method of claim 5, And the DMA control unit performs DMA transfer in a request transfer manner in which the DMA transfer is completed when the DMA request is disabled after the DMA request is enabled and the DMA transfer is started. The method of claim 1, And a register storing a source address and a destination address used as a DMA address during the DMA transfer between the memory and the external input / output device. 11. The method of claim 10, And a register counting unit for counting the source address and the destination address stored in the register. 11. The method of claim 10, And the registers store run length data including continuously repeated data and run length encoded data encoded with the run length data. 13. The method of claim 12, In the run-length encoded data, negative (-) indicates the number of repetitions of data that is continuously repeated, and positive (+) indicates the number of normal data that is not continuously repeated. The method of claim 13, And the run length encoded data is configured to determine whether the data is continuously repeated using the least significant bit or is general data not continuously repeated. The method of claim 14, And if the least significant bit of the run-length encoded data is '0', this indicates the number of general data, and if it is '1', the DMA control device indicates the number of repetitions of data that is continuously repeated. The method according to any one of claims 13 to 15, If the run-length encoded data is data that is continuously repeated, the DMA controller does not perform DMA transfers as many times as it is repeated, but increases only the DMA address stored in a register to control not to perform DMA transfers for the same data. Control unit. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete

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