JP3910165B2 - High speed processor - Google Patents

Description

  The present invention is used in, for example, a video game device, a communication network information device, a portable information device, a communication karaoke device, a car navigation device, an educational toy, a learning material device, a word processor, a practical information providing device, a factory production line, and the like. The present invention relates to a high-speed processor used in inspection equipment, various measuring equipment, and the like.

  Conventionally, there are many multiprocessor systems in which a plurality of processors (bus masters) share and cooperate to perform processing. In such a system, there are many configurations in which a plurality of processors (bus masters) share a single bus and resources connected to the bus. Here, the resources connected to the bus refer to devices on the side of receiving addresses such as memory devices, input / output control devices, and other functional blocks. In this specification, these are called bus slaves for the bus master that issues the address. In this way, a system in which a plurality of processors (bus masters) share resources has the great advantages of simplifying the system by sharing resources and reducing the need for data transfer between resources. .

  However, in recent years, the performance of the processor (bus master) has been remarkably improved, and the speed difference between the memory device and the like has widened, and data transfer between the processor (bus master) and the memory device has become a major bottleneck in the processing of the processor (bus master). . Many systems strive to alleviate this bottleneck by using high-speed cache memory or the like.

  In a multiprocessor system having a shared bus, the period during which each processor (bus master) can use the shared bus is reduced compared to a system having only a single processor (bus master). It becomes. In many systems, the cache memory inside the processor (bus master) and local memory dedicated to each processor (bus master) are actively introduced to try to reduce the need for data transfer using the shared bus as much as possible. ing.

  As another method for solving this bottleneck, a processor (bus master) may include a plurality of external buses. A known example is a Harvard architecture processor in which an instruction acquisition bus and a data access bus are separated. Alternatively, there is an example of a processor in which a memory access bus and an input / output control bus are separated.

  By the way, in a single bus system, all bus slaves are connected to this bus. However, when there are bus slaves with different response speeds (access speeds) and data bus widths, the bus utilization efficiency Will fall.

  Therefore, as shown in FIG. 16, there is a system in which a plurality of buses having different data transfer capacities are provided and bus slaves corresponding to the respective transfer capacities are connected to increase the bus utilization efficiency. In this specification, the data transfer capability of the bus refers to that compared by the product of the bus cycle frequency and the bit width of the data bus. As an example of a system in which a plurality of buses are provided for each data transfer capability as described above, a hierarchical bus system often found in personal computers and workstations can be cited.

  Taking a recent PC / AT compatible machine equipped with an Intel Pentium processor as a CPU (Central Processing Unit) as an example, a processor external bus with a bus cycle frequency of 60 MHz or 66 MHz and a data bus width of 64 bits, a bus cycle Generally, a bus having three different data transfer capacities, a PCI bus having a frequency of 33 MHz and a data bus width of 32 bits, and an AT bus having a bus cycle frequency of about 10 MHz and a data bus width of 8 bits, are provided.

  Semiconductor memory such as DRAM is connected to the processor external bus, peripheral devices such as graphic processing devices that require high-speed data transfer are connected to the PCI bus, and peripheral devices such as magnetic memory that perform relatively low-speed data transfer are AT Connected to the bus.

  In this system, the CPU directly controls as the bus master only for the processor external bus (high-speed first bus), and the PCI bus (low-speed second bus) and AT bus (low-speed). For the third bus), the inter-bus interface device mediates data transfer. Generally, an inter-bus interface device that interfaces between a processor external bus (high-speed first bus) and a PCI bus (low-speed second bus), a PCI bus (low-speed second bus), and an AT Two bus interface devices for interfacing between buses (a low-speed third bus) are provided. In this system, access to the lower bus is performed via the upper bus.

  By the way, in a system where a plurality of processors (bus masters) share a bus and a bus slave, a system for bus arbitration is indispensable. This is because the bus is shared in a time-sharing manner, and only one processor (bus master) can use the bus when paying attention to a certain temporary point.

  Generally, the processor (bus master) issues a bus use request to the bus arbitration circuit, the bus arbitration circuit performs arbitration based on this bus use request, and the processor (bus master) permits the bus use from the bus arbitration circuit. A method of using a bus after accepting the card is often used.

  However, in the above-described system, the other bus and bus slave are occupied by the one bus master for a period until one bus master releases the bus by itself or for a predetermined fixed period.

  In particular, in a multiprocessor system having a plurality of bus masters, if the use efficiency of the shared bus is deteriorated, the processing capacity of the entire system is lowered.

  In a system using a cache memory, a local memory, or the like often found in the prior art, it is difficult to configure the system at a low cost.

  The cache memory not only needs to be composed of a high-speed memory element, but also the memory element for storing address information in addition to the memory element for storing data, and the contents of the memory device on the shared bus and the cache memory are the same. As a result, a control circuit and the like for maintaining were required, and the entire system was expensive and complicated.

  In addition, cache memory and local memory often hold data with the same contents as memory devices on a shared bus, and the same data is held redundantly among multiple memory devices, making effective use of memory resources. This is undesirable.

  Thus, an object of the present invention is to solve a bottleneck in data transfer between a bus master and a bus slave by increasing the use efficiency of the shared bus as much as possible without using a technique such as a cache memory. To do.

  When there is a single shared bus, all bus slaves with different data transfer capabilities are connected to this bus. This means that the total amount of data transfer on the bus is reduced, which is one of the factors that hinder the efficient use of the bus. In view of this point, separating the shared bus into a plurality of buses having different data transfer capacities and connecting bus slaves corresponding to the respective data transfer capacities is an effective means for achieving efficient use of the buses. It is. However, the known hierarchical bus system has a problem that the upper data transfer width has to be consumed in order to access the lower bus. The inter-bus interface device also has a function for controlling the lower-level bus as a bus master, a FIFO (first-in-first-out) memory for absorbing differences in bus data transfer capability, and the like. It is often used and is not suitable for a system intended to be configured at low cost.

  Therefore, an object of the present invention is to construct a new system that can be configured at low cost and can use the bus efficiently without relying on a conventionally known hierarchical bus system. .

  Another object of the present invention is to provide a high-speed processor that is as inexpensive as possible but has the highest possible performance.

  Here, paying attention to the arbitration method, there are many existing arbitration methods in which a processor (bus master) occupies and uses a bus during a period having a certain time width. In such an arbitration method, the processor (bus master) does not actually use the bus during the period when the processor (bus master) is performing internal operations or accessing the internal cache memory or the like. Regardless, other processors (bus masters) cannot use the bus. Also, the bus cycle speed depends on the bus cycle speed of the processor (bus master) that is given the right to use the bus. When a low-speed processor (bus master) occupies the bus, the bus use efficiency decreases. Therefore, an object of the present invention is to realize efficient use of the bus even by adopting a unique bus arbitration method.

  According to the first aspect of the present invention, a shared bus, a plurality of bus masters each directly connected to the shared bus, a plurality of bus slaves each connected to the shared bus, and a right to use the bus every bus cycle of the shared bus And a bus arbitration circuit that gives a shared bus use permission signal to one of the bus masters at the start of one bus cycle unit, and the shared bus is divided into a first area and a second area, It is determined for each bus cycle of the shared bus whether the address issued by the bus master that has received the shared bus use permission signal corresponds to the first area or the second area. If it is determined that it corresponds to the second bus cycle period length, and if it is determined that it corresponds to the second area, the second bus cycle period length is set to the length of the bus cycle. And a bus cycle length control means for issuing a bus cycle end signal at the end of each bus cycle according to the determined bus cycle length, wherein the bus master uses the shared bus use permission signal to transmit data in the shared bus Is a high-speed processor that starts data transmission / reception and terminates data transmission / reception by the bus cycle end signal.

  In the first aspect of the present invention, for example, the bus master of the embodiment is directly connected to the shared bus which is the second bus (11) of the embodiment, and the bus slave is connected to the shared bus. The bus arbitration circuit determines the right to use the bus for each bus cycle of the shared bus, and gives the use permission to the bus master in one bus cycle unit.

  The shared bus is divided into a first area and a second area like the second bus area A and the second bus area B in the embodiment. Then, for example, the bus cycle length control means such as the external memory interface circuit (FIG. 15: 1314) of the embodiment decodes the address from the bus master having the right to use and the address is in the first area or the second area. A bus cycle end signal is generated by determining which of the areas it belongs to, for example, by referring to the bus cycle length control register corresponding to the determined area. Therefore, the bus master starts data transmission / reception in response to the bus use permission signal, and ends data transmission / reception in response to the bus cycle end signal.

  According to a second aspect of the present invention, the bus arbitration circuit does not depend on the bus cycle speed of the bus master, and is the fastest time during which the shared bus can operate and the fastest time during which the bus slave connected to the shared bus can operate. 2. The high-speed processor according to claim 1, wherein the later one of the two times is defined as a bus cycle period of the shared bus, and the right to use the bus is always determined for each bus cycle.

  According to a third aspect of the present invention, there is provided a first memory map mode in which the first area and the second area are arranged in a first form, and the first area and the second area in a second form. A memory map mode switching control register for switching between the second memory map mode and the second memory map mode, wherein the first mail map mode and the second memory map mode are respectively shared by all the bus masters. A high speed processor according to claim 1 or 2.

  The bus master has a function of outputting a bus use request signal to the bus arbitration circuit, a function of waiting for access to the bus until a bus use permission signal is obtained, and a function of sending an address to the bus. It is preferable to use one that is independently provided for each connected bus and that has an interface that is independent for each bus with respect to the connected bus.

  As the interface, a plurality of independent 3-state buffers for controlling the output / non-output of addresses to the bus, and the input / output and connection / non-connection of data to the bus are controlled for each bus. A plurality of independent bidirectional three-state buffers and a means for controlling the three-state buffer based on the bus use permission from the bus arbitration circuit may be used.

  As the processor, at least one of them issues a logical address inside the processor, a decoder that decodes the issued logical address, and selects one of a plurality of buses based on the decoded address information A means for outputting a bus use request signal, a means for selecting only necessary address information in the logical address and generating a physical address, or a means for converting the logical address to generate a physical address, and A plurality of sets of three-state buffers for outputting physical addresses to the bus, whereby a plurality of independent physical address spaces can be allocated to a part of a single logical address space for each bus; It is desirable to have been made.

  The bus arbitration circuit stores priority order information storing means for storing a plurality of sets of bus master priority order information including a set of bus master priority order information that determines the priority order of the bus masters. Priority information selection means for sequentially selecting the bus master priority information for each bus cycle, with the bus master priority information as a repeating unit, and a set of the priority information selected by the selection means. A bus use permission signal generating circuit for outputting a bus use permission signal to permit use of the bus for one bus cycle to a bus master having the highest priority in the set among the bus masters requesting bus use, It is desirable to comprise.

  Further, all the above-described components may be integrated in a single semiconductor element.

  The bus includes, as the processor, one or more central processing processors, a processor having means for performing graphic processing and generating a video signal, and a processor having means for performing sound processing and generating an audio signal, the bus A first bus that manages data transfer and exchange with a functional block inside a semiconductor element and a high-speed semiconductor memory, and a second bus that manages data transfer and exchange with a peripheral device outside the semiconductor element and a low-speed semiconductor memory Including a semiconductor memory connected to the first bus as the bus slave, a first bus arbitration circuit that controls arbitration of the first bus as the bus arbitration circuit, and the second It is desirable to use a circuit including a second bus arbitration circuit that controls bus arbitration.

  According to the present invention, use permission is always determined for each bus cycle, a use permission signal is given for each bus cycle, and the address from the bus master is set for each area according to which area. Since the end signal is given by the bus cycle length, a high-speed processor capable of efficiently using the bus can be obtained.

  The basic concept of the high speed processor according to the present invention will be described below with reference to FIG.

  As shown in FIG. 1, this system includes one or a plurality of bus masters (1) (2), a plurality of buses (10) (11) having different data transfer capabilities or operation speeds, And a plurality of bus slaves (20) and (21) capable of responding at a speed corresponding to the operation speed.

  Each of the bus slaves (20) and (21) is connected to one of the buses (10) and (11) having an operation speed corresponding to a transfer capability corresponding to the bus slave or a response speed thereof. Here, each of the buses (10) and (11) has an independent address bus and data bus. Thus, the bus masters (1) and (2) are directly connected to the address bus and data bus of each of the buses (10) and (11). Here, in this specification, the direct connection means that each bus master (1) (without the inter-bus interface interposed between the buses as in the conventionally known hierarchical bus system shown in FIG. 2) is connected to each bus (10) (11). Needless to say, the bus masters (1), (2) and the buses (10), (11) are connected via a conventionally known interface, but this interface is extremely configured compared to the inter-bus interface. Is simple.

  Further, each bus (10) (11) is provided with a bus arbitration circuit (not shown) that arbitrates access to the bus from the plurality of bus masters (1) (2). However, when there is a single bus master, a bus arbitration circuit is basically unnecessary.

  The bus masters (1) and (2) output a bus use request signal to the bus arbitration circuit, wait for access to the bus until a bus use permission signal is obtained, Having a function of transmitting addresses and a function of completing transmission and reception of data within a bus cycle period determined by the bus arbitration circuit, and is independent for each bus with respect to the connected buses (10) and (11). An interface (not shown) is provided.

  The interface includes a plurality of sets of three-state buffers independent for each bus for controlling output / non-output of addresses to the buses (10) and (11), and data input / output to the buses (10) and (11). And a plurality of sets of bidirectional three-state buffers independent for each bus for controlling connection / disconnection, and means for controlling the three-state buffers based on a bus use permission from the bus arbitration circuit.

  At least one of the bus masters (1) and (2) includes means for issuing a logical address within the bus master, a decoder for decoding the issued logical address, and a plurality of buses based on the decoded address information. Means for selecting one and outputting a bus use request signal; means for selecting only necessary address information in a logical address to generate a physical address; or means for converting a logical address to generate a physical address; A plurality of sets of three-state buffers for outputting the generated physical addresses to the bus, whereby a plurality of physical address spaces independent for each bus are made part of a single logical address space. Will be assigned.

  The bus arbitration circuit determines the slower of the fastest time accessible to the bus slaves (20) and (21) and the fastest time during which the bus can operate as the bus cycle time. The bus use right is always determined, and the bus master (1) (2) is provided with a function of granting the bus master (1) (2) permission to use the bus (10) (11) only in one bus cycle unit. A function of transmitting and receiving data within the bus cycle period is provided.

  The bus arbitration circuit stores priority order information storing means for storing a plurality of sets of bus master priority order information including a set of bus master priority order information that determines the priority order of the bus masters. Priority information selection means for sequentially selecting the bus master priority information for each bus cycle, with the bus master priority information as a repeating unit, and a set of the priority information selected by the selection means. A bus use permission signal generating circuit for outputting a bus use permission signal to permit use of the bus for one bus cycle to a bus master having the highest priority in the set among the bus masters requesting bus use, It has.

  By the way, all the above-mentioned components, that is, all the components including the bus master (1) (2), the bus (10) (11) and the bus slave (20) (21) are integrated in a single semiconductor device. Has been.

  In order to solve the bottleneck in data transfer between the bus master (1) (2) and the bus slave (20) (21), the high-speed processor according to the present invention provides a plurality of buses having different data transfer capabilities as described above. (10) and (11) are provided, and the bus masters (1) and (2) directly access the buses (10) and (11). As a result, it is possible to prevent a decrease in bus use efficiency due to a mixture of bus slaves (20) and (21) having different data transfer capabilities, and to realize efficient bus use.

  Further, the problem that the data transfer width of the bus (10) having a high transfer capability, which is found in the hierarchical bus system, is consumed by the bus (11) having a low transfer capability is also solved. Furthermore, since a special circuit is not required as a device for interfacing between the buses (10) and (11), a system can be configured at low cost.

  Further, when a plurality of bus masters (1) and (2) request to use the same bus at the same time, the bus master (1) and (2) are determined by determining the right to use the bus independently for each bus. Uses only authorized buses and does not occupy other buses. Therefore, the opportunity to occupy the buses and bus slaves that are not used by the bus master is reduced, and the use efficiency of the bus can be further improved.

  As a bus arbitration circuit, the bus use permission is determined for each bus cycle, and the bus use permission is given to the bus master only in units of one bus cycle. Therefore, the bus master does not occupy the bus during a period when the bus is not used for internal operation or the like.

  If the bus cycle speed is determined by the bus arbitration circuit, it can be made independent of the bus cycle speed of the bus master. Therefore, even when there is a speed difference in the bus cycle between the bus masters, the bus can always operate at the maximum speed. When the bus cycle speed of the bus master is low, the difference in bus cycle speed may be buffered by, for example, providing a read buffer or a write buffer on the data bus or delaying the output of the bus use request signal.

  In addition, by arranging the physical address space of multiple buses within a single logical address space, not only can the physical address space of all buses be handled uniformly, but also as a single processing unit. This data block can be arranged across the physical address spaces of a plurality of buses, and programming is easy and flexible.

  Here, first, an example of a central processing processor according to the present invention will be described.

  The central processing processor is one of a plurality of bus masters constituting the high speed processor according to the present invention. The central processing processor has a function of accessing two sets of shared buses, the first bus and the second bus.

  The first bus is a shared bus including a 16-bit address bus, a read / write signal, and an 8-bit data bus. Access from a plurality of bus masters is arbitrated by the first bus arbitration circuit. This is a high-speed bus in which one cycle of a clock signal is one bus cycle, and is mainly used for access to a high-speed semiconductor memory and data transfer between functional blocks in a high-speed multiprocessor.

  The second bus is a shared bus including a 24-bit address bus, a read / write signal, and an 8-bit data bus. Access from a plurality of bus masters is arbitrated by the second bus arbitration circuit. This is a relatively low-speed bus in which 2 to 8 cycles (however, an integer) of the clock signal is one bus cycle, and is mainly used for access to a low-speed semiconductor memory and data transfer with devices outside the high-speed multiprocessor. . The setting of the number of clock cycles in one bus cycle is controlled by a second bus cycle length control register included in the external memory interface circuit.

  FIG. 2 shows an outline of the main part of the central processing processor. The central processing processor includes a processor core (50), an address decoder (51), first bus interface control means (52), second bus interface control means (53), clock control means (54), and two sets of three. It consists of a state buffer (55) (60), two sets of bidirectional three-state buffers (56) (61), a peripheral function block (57), an internal address bus and read / write signal (58), and an internal data bus (59). .

  The processor core (50) governs various calculations and control of the entire system according to programs stored in the memory. It operates according to a clock signal input from the clock control means (54), and has a 24-bit address bus, a read / write signal, and an 8-bit data bus as bus interface signals. It also has a function of outputting an access valid signal synchronized with its own bus cycle and notifying the outside of the processor core (50) that the bus interface signal is invalid during an internal operation cycle.

  Here, the address bus and read / write signal connected to the processor core (50) are connected to the internal address bus and read / write signal (58), and the data bus is connected to the internal data bus (59). It is not directly connected to the bus and the second bus. Hereinafter, it is assumed that the space of the internal address bus is handled as a logical address space viewed from the program separately from the physical address space of the first bus and the second bus.

  The peripheral function block (57) includes a multiplication circuit, a barrel shifter, an internal vector register, and an interrupt request signal status register. Further, it has a function of outputting a signal obtained by logically summing six interrupt request signals as an interrupt request signal to the processor core (50).

  The address decoder (51) decodes the logical address signal, and the access is made from the decoded first address information, the access valid signal, and the memory map mode control signal sent from the external memory interface circuit (not shown). It is determined which area corresponds to the second bus or the peripheral function block (57). When the access corresponds to the first bus area, a first bus area selection signal is sent to the first bus interface control means (52), and when the access corresponds to the second bus area, the second bus interface control means ( 53), a second bus area selection signal is transmitted. When the access corresponds to the internal peripheral function block area or when the access is not valid, the first bus and second bus area selection signals are not sent, and the central processing processor does not access the external function block.

  The first bus interface control means (52) generates a first bus use request signal from the first bus area selection signal received from the address decoder (51), and sends it to the first bus arbitration circuit. The first bus use request signal is transmitted during a period until the first bus use permission signal is received from the first bus arbitration circuit. The first bus use permission signal is output only during one bus cycle period of the first bus, that is, one clock cycle period, and the first bus interface control means (52) permits output to the 3-state buffer (60) only during this period. And input / output permission to the bidirectional three-state buffer (61).

  The second bus interface control means (53) generates a second bus use request signal from the second bus area selection signal received from the address decoder, and sends it to the second bus arbitration circuit. The second bus use request signal is transmitted during a period until the second bus use permission signal is received from the second bus arbitration circuit. Since the use of the second bus is permitted for a period from when the second bus use permission signal is received to when the second bus cycle end signal is received, the second bus interface control means (53) is used only during this period. Output permission for the 3-state buffer (55) and input / output permission for the bidirectional 3-state buffer (56) are performed.

  The clock control means (54) stops the clock supplied to the processor core (50) according to the processor wait control signal sent from the first bus interface control means (52) and the second bus interface control means (53), The processor core (50) is put into a wait state.

  The 3-state buffer (60) controls the lower 16 bits of the internal address and the output of the read / write signal to the first bus according to the control signal transmitted from the first bus interface control means (52). That is, the three-state buffer (60) controls 17 signal lines.

  The 3-state buffer (55) controls the output of the internal address 24 bits and the read / write signal to the second bus according to the control signal transmitted from the second bus interface control means (53). That is, the three-state buffer (55) controls 25 signal lines.

  The bidirectional three-state buffer (61) outputs from the internal data bus (59) to the first data bus and from the first data bus to the internal data bus (in accordance with a control signal transmitted from the first bus interface control means (52). 59) is controlled. That is, this bidirectional three-state buffer (61) controls eight signal lines.

  The bidirectional three-state buffer (56) outputs from the internal data bus (59) to the second data bus and from the second data bus to the internal data bus (in accordance with a control signal transmitted from the second bus interface control means (53). 59) is controlled. That is, the bidirectional three-state buffer (56) controls eight signal lines.

  The address space of this central processing processor will be described below. Hereinafter, in order to distinguish this from a decimal number, “h” is added to the end of the number.

  The processor core (50) of the central processor has a 24-bit address signal, that is, a 16 megabyte address space. This is a logical address space viewed from a program executed by the processor core (50).

  The first bus has a 16-bit address signal, that is, a physical address space of 64 kilobytes.

  The second bus has a 24-bit address or 16 megabytes physical address space. The address space of the second bus is roughly divided into two areas, and different bus cycle lengths can be set for each. Here, these two areas are referred to as a second bus area A and a second bus area B.

  In this central processing processor, a plurality of physical address spaces are arranged in the logical address space of the processor core (50), and one of these physical address spaces is selected each time the processor core (50) accesses. And used. For the unselected buses, the processor core (50) does not occupy them and is in an open state available to other bus masters.

  As shown in FIGS. 3 and 4, the central processor has two different memory map modes. Here, these are called memory map mode 1 and memory map mode 2. These modes are switched by a memory map mode switching control register included in an external memory interface circuit (not shown).

  The memory map mode switching control register is connected to the first bus and can be read and written from the bus master of the first bus including the central processing processor. By doing in this way, not only this central processing processor but other bus masters can control this memory map mode, and can share this memory map mode.

  The 24-bit address issued by the processor core (50) is roughly divided into upper 8 bits and lower 16 bits, and the upper 8-bit address functions as a bank address. That is, the logical address space of 16 megabytes is divided into 256 unit spaces called 64 kilobyte banks. For example, the FFFFh address of 00h bank and the 0000h address of 01h bank are not continuous. Therefore, the memory maps shown in FIG. 3 and FIG. 4 are written in parallel for each bank in order to express this clearly.

  The memory map mode 1 will be described.

  The peripheral function block (57) is arranged in a space in which the lower 16 bits of the logical address indicate 00FEh, 00FFh, 7FF0h to 7FFFh.

  The space where the physical address of the first bus indicates 0000h to 7FEFh (excluding 00FEh and 00FFh) is arranged in the space where the lower 16 bits of the logical address indicate 0000h to 7FEFh (excluding 00FEh and 00FFh). The space in which the physical address of the first bus indicates 00FEh, 00FFh, 7FF0 to FFFFh cannot be accessed from the central processor.

  In the memory map mode 1, the same image is arranged in all banks 00h to FFh in the peripheral function block area and the first bus area. For example, access to 000000h in the logical address space and access to 010000h are both accesses to 0000h in the physical address space of the first bus.

  The space where the physical address of the second bus is from 00800h to 00FFFFh to FF8000h to FFFFFFh is arranged in the space where the logical address is from 00800h to 00FFFFh to FF8000h to FFFFFFh. Here, the space indicating logical addresses from 00800h to 00FFFFh to 7F8000h to 7FFFFFh is the second bus region A, and the space indicating logical address spaces from 808000h to 80FFFFh to FF8000h to FFFFFFh is the second bus region B. In the memory map mode 1, the space where the physical address of the second bus indicates 000000h to 007FFFh to FF0000h to FF7FFFh cannot be accessed from the central processing processor.

  The memory map mode 2 will be described.

  The peripheral function block is arranged in a space where the bank address in the logical address space indicates 00h to 7Fh and the lower 16-bit address indicates 00FEh, 00FFh, 7FF0h to 7FFFh.

  The space where the physical address of the first bus indicates 0000h-7FEFh (excluding 00FEh, 00FFh) indicates the bank address 00h-7Fh of the logical address space, and the lower 16-bit address is 0000h-7FEFh (except 00FEh, 00FFh) Arranged in the space shown. As in the memory map mode 1, the space where the physical address of the first bus indicates 00FEh, 00FFh, 7FF0 to FFFFh cannot be accessed from this central processing processor.

  The space where the physical address of the second bus is from 00800h to 00FFFFh to 7F8000h to 7FFFFFh is the space where the logical address is from 00800h to 00FFFFh to 7F8000h to 7FFFFFh, and the physical address of the second bus is from 800000h to 80FFFFh to FF0000h to FFFFFFh The space is arranged in a space where logical addresses indicate from 800,000h to 80FFFFh to FF0000h to FFFFFFh. Here, the space indicating logical addresses from 00800h to 00FFFFh to 3F8000h to 3FFFFFh and the space indicating from 800000h to 80FFFFh to BF0000h to BFFFFFh are the second bus area A, and the space from 408000h to 40FFFFh to 7F8000h to 7FFFFFh and C00000h. The space from ˜C0FFFFh to FF0000h to FFFFFFh is the second bus area B. In the memory map mode 2, the space in which the physical addresses of the second bus indicate 000000h to 007FFFh to 3F0000h to 3F7FFFh cannot be accessed from the central processing processor.

  As described above, the physical address space of approximately 32 kilobytes of the first bus and the physical address space of 8 megabytes (mode 1) or 12 megabytes (mode 2) of the second bus are arranged in the 16 megabyte logical address space of the processor core. , It can be handled uniformly and continuously in the program.

  Further, since the peripheral function block, the first bus, and the second bus are selectively used for each access depending on the value of the logical address, the central processing processor cannot occupy the first bus and the second bus at the same time. In addition, even in a period in which the central processing processor is using one bus, the other bus master can use the other bus.

  An example of access to the first bus and the second bus from the central processing processor will be shown below.

  FIG. 5 shows an example of a timing chart of access to the first bus of the central processing processor.

  One bus cycle period of the first bus corresponds to one cycle period of the clock signal, and access from a plurality of bus masters including the central processing processor is arbitrated for each bus cycle by the first bus arbitration circuit.

  On the other hand, one bus cycle period of the processor core (50) of the central processing processor corresponds to three clock signal cycles even when operating without a wait state, and is longer than the bus cycle period of the first bus. The use permission period of the first bus given to the bus master is one bus cycle, that is, one clock cycle. In order for the low-speed central processing processor to access, the above-described functions shown in FIG. Timing control is required.

  The processor core of this central processing processor operates on the basis of the falling edge of the clock signal supplied thereto. That is, one operation cycle of the processor core is from one falling time point to the next falling time point, and one bus cycle of the processor core is the same.

  Based on the falling edge of the clock signal to the processor core, a logical address is transmitted from the processor core, and the address decoder determines whether the access corresponds to the first bus area based on the logical address, the access valid signal, and the memory map mode information. Determine. When the access corresponds to the first bus area, the address decoder sends a first bus area selection signal to the first bus interface control means, and the first bus interface control means sends a first bus use request signal based on this signal. It is generated and sent to the first bus arbitration circuit.

  The first bus arbitration circuit receives the first bus use request signal from each bus master, determines the bus master to which the bus use is permitted every bus cycle of the first bus, and sends the first bus use permission signal to the bus master. To do. At this time, use of the first bus is not permitted to two or more bus masters at the same time.

  The first bus use permission signal is issued only in units of one bus cycle, and each bus master is permitted to use the first bus only in the bus cycle that has received the first bus use permission signal.

  The clock control means stops the clock supplied to the processor core at a high level for a period until the central processing processor receives the first bus use permission signal, and enters a wait state. When the central processing processor receives the first bus use permission signal, the clock is lowered to the low level, the processor core ends the bus cycle, and the wait state is released.

  The central processing processor sends a part of the internal address bus and the read / write signal to the first address bus and the read / write signal while the use of the first bus is permitted. Here, the low level of the read / write signal indicates data write, and the high level indicates data read.

  When the central processing processor reads data from the first bus, it outputs an internal data bus signal to the first data bus in a bus cycle in which use of the first bus is permitted. However, in order to prevent data collision on the first data bus, no output is made during a period when the clock signal is at a low level.

  When the central processing processor writes data to the first bus, the first data bus signal is input to the internal data bus in a bus cycle in which use of the first bus is permitted. The processor core (50) acquires data on the basis of the falling edge of the clock signal to the processor core.

  FIG. 6 shows an example of a timing chart of access to the second bus of the central processing processor.

  One bus cycle period of the second bus corresponds to 2 to 8 cycle periods of the clock signal, and access from a plurality of bus masters including the central processing processor is arbitrated by the second bus arbitration circuit every bus cycle.

  The length of one bus cycle period of the second bus is determined by a second bus cycle length control register included in an external memory interface circuit (not shown). The second bus cycle length control register is connected to the first bus and can be read and written from a bus master such as a central processing processor. The area of the second bus is divided into two areas, the second bus area A and the second bus area B, and each is provided with a different bus cycle length control register, so that different bus cycle lengths can be set. is there. However, in the example shown in FIG. 6, in order to simplify the explanation, the access is limited to an area in which one bus cycle period is set to four cycles of the clock signal.

  Based on the falling edge of the clock signal to the processor core, a logical address is transmitted from the processor core, and the address decoder determines whether the access corresponds to the second bus area based on the logical address, the access valid signal, and the memory map mode information. Determine. When the access corresponds to the second bus area, the address decoder sends a second bus area selection signal to the second bus interface control means, and the second bus interface control means sends a second bus use request signal based on this signal. It is generated and sent to the second bus arbitration circuit.

  The second bus arbitration circuit receives a second bus use request signal from each bus master, determines a bus master to which the bus use is permitted for each bus cycle of the second bus, and sends a second bus use permission signal to the bus master. To do. As in the case of the first bus, two or more bus masters are not permitted to use the second bus at the same time.

  The second bus use permission signal is issued only in units of one bus cycle, and the bus master is permitted to use the second bus after receiving the second bus use permission signal and before receiving the second bus cycle end signal. . This period is equal to the bus cycle length set by the second bus cycle length control register. In this example, one bus cycle corresponds to four cycles of the clock signal.

  The central processing processor sends the internal address bus and the read / write signal to the second address bus and the read / write signal during the period when the use of the second bus is permitted. Here, the low level of the read / write signal indicates data write, and the high level indicates data read.

  The external memory interface circuit decodes the address signal of the second address bus issued by the bus master, and access is made to either the second bus area A or the second bus area B from the decoded address information and memory map mode information. The second bus cycle end signal is generated based on the value of the second bus cycle length control register corresponding to each area, and the second bus cycle end signal is generated for each bus master and the second bus arbitration circuit. And send it out.

  The clock control means stops the clock supplied to the processor core at a high level and waits until the central processing processor receives the second bus use permission signal and receives the second bus cycle end signal. When the central processing processor receives the second bus cycle end signal, the clock is lowered to a low level, the processor core ends the bus cycle, and the wait state is released.

  When the central processing processor writes data to the second bus, it outputs an internal data bus signal to the second data bus in a bus cycle in which use of the second bus is permitted. However, in order to prevent data collision on the second data bus, no data is output during a period when the clock signal is at a low level in the clock cycle corresponding to the head of the bus cycle.

  When the central processing processor reads data from the second bus, the second data bus signal is input to the internal data bus in a bus cycle in which use of the second bus is permitted. The processor core acquires data on the basis of the falling edge of the clock signal to the processor core.

  Hereinafter, an example of the first bus arbitration circuit and the second bus arbitration circuit will be described, and the bus arbitration system will be described. The configuration of the first bus arbitration circuit is shown in FIG. 7, while the configuration of the second bus arbitration circuit is shown in FIG.

  The first bus arbitration circuit shown in FIG. 7 includes first normal bus masters A, B, C, D (not shown) and one privileged bus master S (hereinafter referred to as privileged bus master S). It is responsible for mediating access to the bus. The first bus arbitration circuit always grants the use permission of the first bus in the next one bus cycle in response to the use request of the first bus from one privileged bus master S. On the other hand, for the first bus use requests from the other four normal bus masters A, B, C, D, use is permitted in the next one bus cycle only for the bus master with the highest priority according to the priority information. Mediation to give Here, a DRAM refresh control circuit or the like is assumed as the privileged bus master S, while the central processing processor or the like is assumed as a normal bus master.

  In this first bus arbitration circuit, the first bus consisting of the first address bus, the read / write signal, and the first data bus is arbitrated, and the built-in registers are accessed from the first bus. Yes. The bus cycle corresponds to one cycle of the clock signal, and arbitration is performed every bus cycle.

  As shown in FIG. 7, the first bus arbitration circuit includes 16 fixed priority information storage means (101 to 116), 16 programmable priority information storage means (registers) (101 ′ to 116 ′), Address decoder (117), fixed / programmable switching control register (118), bus cycle counter (119), priority order information selection means (selector) (120), use permission signal generation means (121), data selector (122), A 3-state buffer (123, 124) and an alternative address generating means (125) are provided.

  The address decoder (117) decodes the first address bus and the read / write signal, selects signals from the programmable priority information registers (101 ′ to 116 ′), control signals from the data selector (122), three states A control signal for the buffer (123) is generated.

  The fixed / programmable switching control register (118) switches between the fixed priority information storage means (101 to 116) and the programmable priority information register (101 ′ to 116 ′), so that the fixed priority information or the programmable priority information Either one is selected.

  Each of the programmable priority information registers (101 ′ to 116 ′) stores a set of programmable priority information, and a bus master such as a processor accessing the first bus can rewrite the information. It is made like that.

  Each of the fixed priority order information storage means (101 to 116) is a means for storing a set of fixed priority order information, and is composed of wired logic. This information is not rewritable. In this example, the magnitude of the value of the priority information is 2 bits and represents a combination of four priorities. However, the magnitude of this value need not be 2 bits. The optimum value should be used in consideration of the number of bus masters to be arbitrated, the number of priority combinations, and the circuit scale.

  In this example, the fixed priority information storage means (101 to 116) and the programmable priority information registers (101 'to 116') are both 16, and arbitration is performed using 16 bus cycles as a repeating unit. Done. However, this number need not be 16. The optimum value should be used in consideration of the number of bus masters to be arbitrated, the distribution ratio of bus cycles to each bus master, and the circuit scale.

  The bus cycle counter (119) counts the number of bus cycles of the first bus and indicates a current value with 16 bus cycles as a repeating unit. The maximum value of the count should be set equal to the number of sets of priority information.

  The selector (120) selects one set of 16 sets of priority order information from the current value information of the bus cycle indicated by the bus cycle counter (119).

  The use permission signal generating means (121) receives the first bus use request signals from the four normal bus masters of the bus master A, the bus master B, the bus master C, and the bus master D and the one privileged bus master S, and the selector ( The first bus use permission signal is generated for the bus master with the highest priority from the priority information selected in step 120) and issued to the bus master.

  Here, when the first bus use request signal from the privileged bus master S is received, the first bus use request signal from the other bus masters A, B, C, D and the priority information of these bus masters A, B, C, D Regardless, the use permission of the next one bus cycle is unconditionally given to the privileged bus master S. However, in the present invention, the number of bus masters to be accessed and the presence or absence of a privileged bus master are not limited to this embodiment.

  The data selector (122) is a control signal generated by the address decoder (117) when the value of each register (118, 101 ′ to 116 ′) is read from a bus master such as a processor via the first bus. The data to be read is selected according to the above.

  The 3-state buffer (123) controls whether or not to output the register value sent from the data selector (122) to the first data bus according to the control signal generated by the address decoder (117). It is.

  The other three-state buffer (124) outputs an alternative address issued from the alternative address generation means (125) to the first address bus and read / write signal when there is no bus use request signal from the bus master. Acts like

  Next, an arbitration example of the first bus arbitration circuit described above will be described. In the arbitration example shown below, for the purpose of simplifying the explanation, it is assumed that the bus use request signal is issued only from the bus master A and the bus master B, and the bus use request signal is not issued from the bus master C and the bus master D. That is, arbitration is limited to two bus masters A and B.

  One bus cycle of the first bus corresponds to one cycle of the clock signal. The bus cycle counter (119) increments the value every bus cycle and periodically counts values from 0 to 15. For each bus cycle, one of the priority information storage means (101, 101 'to 116, 116') corresponding to the value of the bus cycle counter (119) on a one-to-one basis is selected and stored in the selected storage means. The priority information is retrieved. In this example, the priority information has a size of 2 bits, and indicates any one of four values of 0, 1, 2, and 3.

  FIG. 8 shows a setting example of the priority information value corresponding to the bus cycle counter value. This setting of priority information can be applied to both fixed priority information and programmable priority information. FIG. 8 shows an example of setting the priority order values 0, 1, 2, and 3 and the priority order of the bus masters A, B, C, and D corresponding thereto.

  FIG. 10 shows a first arbitration example, and FIG. 11 shows a second arbitration example. The arbitration example 1 shown in FIG. 10 and the arbitration example 2 shown in FIG. 11 are based on partially different design methods. The difference between the two is that, when the bus master obtains the use permission of the bus, it can be immediately reflected in the bus use request signal issued by itself.

  In the design method for realizing the arbitration example 1 shown in FIG. 10, the bus master can immediately reflect it in the bus use request signal within the cycle in which the bus use permission is obtained. The bus master is allowed to continuously issue a bus use request signal.

  On the other hand, in the design method for realizing the arbitration example 2 shown in FIG. 11, the bus master circuit cannot reflect the bus use request signal within the cycle in which the bus use permission is obtained. In the cycle in which the use permission of the bus is given, the use request from the bus master giving the use permission is ignored. Therefore, in the arbitration example 2 design method, the same bus master cannot obtain the right to use the bus continuously. However, it is easier to design than the design method of the arbitration example 1 and is an effective design method especially when arbitration at high speed is required.

  In the following, the points common to the first bus arbitration examples 1 and 2 will be described first.

  When no bus master issues a bus use request signal, the bus arbitration circuit does not issue a bus use permission signal to any bus master. For example, since neither bus master A nor bus master B issues a bus use request signal in the first bus cycle (701, 801), the bus arbitration circuit does not issue a bus in the next bus cycle (702, 802) to any bus master. Is not allowed.

  When only one of the bus masters has issued a bus use request signal, the bus arbitration circuit issues a bus use request signal to that bus master. For example, since only the bus master A issues a bus use request signal in the second bus cycle (702, 802), the use is permitted to the bus master A in the next bus cycle (703, 803).

  When two or more bus masters issue a bus use request signal at the same time, the bus arbitration circuit selects a bus master having a higher priority according to the priority order represented by the priority information, and the bus master selects the bus master. Issue a usage permission signal. For example, in the sixth bus cycle (706, 806), the bus master A and the bus master B issue a bus use request signal at the same time, and the bus master B has a higher priority than the bus master A. In (707, 807), use of the bus master B is permitted.

  Next, differences between the two examples of arbitration will be described.

  In the first arbitration example, when a bus master has finished issuing a use request signal in a cycle in which use of the bus has been granted, and another bus master has issued a use request signal in the cycle. Only the other bus master requests use. Therefore, the other bus master A obtains a bus use permission in the next one bus cycle. For example, as shown in FIG. 10, the bus master A has finished issuing the use request signal in the third bus cycle (703) where the bus use permission has been obtained, and the bus master B uses it in the bus cycle (703). Since the request signal is issued, only the bus master B requests use, and the bus master B is permitted to use in the next one bus cycle (704).

  On the other hand, in the second arbitration example, when a certain bus master has not finished issuing a use request signal in a bus cycle in which permission to use the bus is obtained, another bus master issues a use request signal in the bus cycle. In such a case, the use request from the bus master having the use permission is ignored, and only the use request from the other bus master is accepted. Therefore, the other bus master obtains the bus use permission in the next one bus cycle. For example, although the bus master A has not finished issuing the use request signal in the third bus cycle (803) in which the bus use permission has been obtained, the bus master B issues the use request signal in the bus cycle (803). In this case, in this bus cycle (803), the use request of the bus master A is ignored, and only the use request from the bus master B is accepted. Accordingly, the bus master B is permitted to use in the next one bus cycle (804).

  Further, in the arbitration example 1, when the same bus master makes a bus use request continuously (707, 708), it is possible to continuously grant use permission for two or more bus cycles to the same bus master. For example, the bus master A requests use of the bus continuously in the seventh and eighth bus cycles (707, 708), and is continuously permitted in the next two bus cycles (708, 709).

  On the other hand, in the arbitration example 2, the use request signal from the bus master is ignored in the bus cycle (808) for which the use permission is given to the bus master. No license can be granted. For example, since the bus master A is permitted in the eighth bus cycle (808), the use request signal in the bus cycle (808) is ignored and is not permitted in the next bus cycle (809).

  Next, a second bus arbitration circuit that arbitrates access from a plurality of bus masters to the second bus will be described. This arbitration circuit controls the arbitration of the four bus masters, controls the second bus consisting of the second address bus, the read / write signal, and the second data bus, and the built-in register has the first bus. It is accessed from. The bus cycle corresponds to 2 to 8 cycles (only an integer) of the clock signal, and arbitration is performed every bus cycle.

  FIG. 12 shows an outline of a main part of the second bus arbitration circuit.

  The second bus arbitration circuit includes an address decoder (217), a fixed / programmable switching control register (218), eight fixed priority information storage means (201 to 208), and eight programmable priority information registers (201 ′ 208 '), a bus cycle counter (219), a selector (220), a use permission signal generating means (221), a data selector (222), a three-state buffer (223, 224), and an alternative address generating means (225).

  Hereinafter, differences from the first bus arbitration circuit will be described.

  Since the second bus arbitration circuit is intended to arbitrate access of each bus master to the second bus, the use permission signal generating means (221) receives the second bus use request signal from each bus master and Issue a bus 2 permission signal. There are four bus masters, bus master A, bus master B, bus master C, and bus master D, to be arbitrated. As these bus masters, the aforementioned central processing processor or the like is assumed.

  The number of the fixed priority information storage means (201 to 208) and the programmable priority information register (201 ′ to 208 ′) is eight. As a result, the circuit scale of the address decoder (217), bus cycle counter (219), selector (220), and data selector (222) is also smaller than that of the first bus arbitration circuit.

  However, the number of fixed priority information storage means (201 to 208) and programmable priority information registers (201 ′ to 208 ′) need not be eight. The optimum value should be used in consideration of the number of bus masters to be arbitrated, the distribution ratio of bus cycles to each bus master, and the circuit scale.

  When there is no request signal from the bus masters A, B, C, and D, the 3-state buffer (224) outputs the alternative address issued from the alternative address generation means (225) to the second address bus and the read / write signal. To do.

  FIG. 13 shows a second bus arbitration example. Also in this arbitration example, in order to simplify the explanation, it is assumed that the bus use request signal is not issued from the bus master C and the bus master D, and the target of arbitration is limited to the bus master A and the bus master B.

  As described above, the second bus has two areas, and different bus cycles can be set for each of them. In this example, one bus cycle in the area accessed by the bus master A corresponds to four clock signal cycles, and one bus cycle in the area accessed by the bus master B corresponds to two clock signal cycles.

  However, during the period when no bus master uses the bus, one bus cycle corresponds to one cycle of the clock signal.

  The bus use permission signal indicates a high level only for one cycle period of the first clock signal of one bus cycle for the bus master permitting use of the bus. The bus master that has received the bus use permission signal is permitted to use the bus during the period until this bus cycle is completed.

  The bus cycle end signal indicates a high level only during one cycle period of the last clock signal of one bus cycle, and indicates a low level during other periods. A high level is output during a period when no bus master uses the bus. This signal is common to all bus masters.

  The bus cycle counter (219) increments the value every bus cycle and periodically counts values from 0 to 7.

  For each bus cycle, the value of the priority information corresponding to the value of the bus cycle counter (219) on a one-to-one basis is selected. In this example, the priority information has a size of 2 bits and indicates one of four values 0 to 3.

  The contents of the priority order information in this example are shown in FIG. Here, it is not particularly specified whether this is fixed priority information or programmable priority information, but it is applicable to either case.

  The value of the priority order information represents an order of the priority order of the bus master corresponding thereto. Here, the setting example shown in FIG. 8 similar to the arbitration example of the first bus is used.

  When no bus master issues a second bus use request signal, the second bus arbitration circuit does not issue a bus use permission signal to any bus master. For example, in the first bus cycle (901), neither the bus master A nor the bus master B issues a bus use request signal, so the bus arbitration circuit does not issue any bus master to the bus cycle (902) in the next bus cycle (902). Is not allowed.

  When only one of the bus masters has issued a bus use request signal, the bus arbitration circuit issues a bus use permission signal to the bus master in the next cycle after receiving the bus use request signal, and the bus cycle The use permission of the bus cycle is given until the end signal is issued. For example, in the second bus cycle (902), only the bus master A issues a bus use request signal, and a bus use end signal is issued in the middle of the next bus cycle (903). The bus master A is permitted to use in all periods of (903).

  When two or more bus masters issue a bus use request signal at the same time, the bus arbitration circuit selects a bus master having a higher priority according to the priority order represented by the priority information, and the bus master selects the bus master. Issue a usage permission signal. For example, in the sixth bus cycle (906), the bus master A and the bus master B issue a bus use request signal at the same time, and the bus master B has a higher priority than the bus master A. In (907), the bus master B is permitted to use.

  In this example, the bus master detects the bus use permission signal at the falling edge of the clock signal, and reflects the result in the bus use request signal issued by itself. In this example, since the shortest bus cycle given to the bus master corresponds to two cycles of the clock signal, the bus master can complete the operation by the end of the bus cycle. Therefore, the same bus master is permitted to make bus use requests continuously.

  If the same bus master issues a bus use request signal at the end of a bus cycle (908) that is permitted to be used by a bus master, the bus arbitration circuit uses the next bus cycle (909) for the same bus master. Give permission again.

  The high-speed multiprocessor according to the present invention will be described below.

  FIG. 15 shows an outline of the main part of the high-speed multiprocessor. This high-speed multiprocessor according to this embodiment includes one central processing processor (bus master) (1301), one graphic processing processor (bus master) (1302), one sound processing processor (bus master) (1303), one Direct memory transfer (DMA) control processor (bus master) (1304), internal memory (bus slave) (1305), first bus arbitration circuit (1306), second bus arbitration circuit (1307), input / output control circuit (bus slave) ) (1308), timer circuit (bus slave) (1309), analog / digital (A / D) converter (bus slave) (1310), PLL circuit ((1311), clock driver (1312), low voltage detection circuit ( 1313), having an external memory interface circuit (1314) and, if necessary, a DRAM refresh control circuit (bus master) (1315) Have.

  The first address bus and read / write signal (1316) and the first data bus (1317) constitute a high-speed first bus, and the second address bus and second read / write signal (1318) and the first data bus (1318). Two data buses (1319) constitute a low-speed second bus.

  The second address bus and read / write signal (1318) are connected to the external address bus and read / write signal (1320), the second data bus (1319) is connected to the external data bus (1321), and the external memory interface circuit (1314). Connected through.

  External to the multiprocessor is one or more external read only memory (ROM) (bus slave) (1322), one or more external random access memory (RAM) (bus slave) (1323) if necessary, An oscillation circuit constituted by a crystal resonator (1324) and a battery (1325) for holding data in a static memory (SRAM) are required as necessary.

  The central processing processor (1301) provided in the present multiprocessor is the same as the central processing processor.

  As the first bus arbitration circuit (1306) and the second bus arbitration circuit (1307) provided in the multiprocessor, the first and second arbitration circuits are used as they are.

  The first bus arbitration signal shown in FIG. 15 includes a first bus use request signal and a first bus use permission signal, and the second bus arbitration signal includes a second bus use request signal and a second bus use permission signal. The bus cycle end signal of the second bus.

  Here, the bus master A, the bus master B, the bus master C, and the bus master D correspond to a sound processing processor (1303), a graphic processing processor (1302), a DMA control processor (1304), and a central processing processor (1301), respectively. The privileged bus master corresponds to the DRAM refresh control circuit (1315).

  The function of each part constituting this multiprocessor will be described.

  The central processing processor (1301) performs various operations and controls the entire system according to a program stored in the memory.

  The graphic processor (1302) synthesizes graphic data and generates a video signal suitable for the color television receiver. The graphic data consists of a graphic element composed of a two-dimensional array of rectangular pixel sets having a size that covers the entire screen of the television receiver, and one rectangular pixel set that can be placed at any position on the screen. Synthesized from graphic elements. Here, the former is called a text screen, the latter is called a sprite, and each rectangular pixel set is called a character. The one used in this embodiment can display a maximum of two text screens and a maximum of 256 sprites. A video signal that can be displayed on a receiver conforming to the NTSC standard and the PAL standard is generated from the synthesized graphic data.

  The sound processor (1303) synthesizes sound data and generates an audio signal. Sound data is synthesized by performing pitch conversion and amplitude modulation on PCM (pulse code modulation) data, which is a basic timbre. In amplitude modulation, in addition to volume control instructed by the central processing processor (1301), an envelope control function for reproducing the waveform of an instrument such as a piano or drum is prepared.

  The DMA control processor (1304) manages data transfer from the external ROM or external RAM to the internal memory.

  The internal memory (1305) includes a necessary one of mask ROM, static memory (SRAM), and dynamic memory (DRAM). When data retention by the SRAM battery is required, a battery (1325) is required outside the multiprocessor. When a DRAM is installed, an operation for holding stored contents called refresh is required periodically.

  The first bus arbitration circuit (1306) receives a first bus use request signal from each bus master connected to the first bus, performs arbitration according to the priority information of the first bus, and uses the bus to each bus master. Issue permission signal. Since the bus cycle of the first bus in this embodiment corresponds to one cycle of the clock signal, the bus arbitration circuit performs the above operation every cycle of the clock signal.

  The second bus arbitration circuit (1307) receives a second bus use request signal from each processor connected to the second bus, performs arbitration of the second bus according to the priority information of the second bus, and sends it to the processor. The bus use permission signal is issued. Since the bus cycle of the second bus in this embodiment corresponds to 2 to 8 cycles of the clock signal, the bus arbitration circuit performs the above operation every bus cycle and issues a bus cycle end signal to the processor. Signals the end of the bus cycle.

  The input / output control circuit (1308) is mainly used for communication with an external input device that accepts an input from a human or an external semiconductor element.

  The timer circuit (1309) has a function of generating an interrupt request signal to the central processing processor (1301) based on the time interval set by the program.

  The A / D converter (1310) converts an analog level input voltage signal into a digital numerical value.

  The PLL circuit (1311) is configured by a phase-locked loop (PLL), and a high-frequency clock signal obtained by M / N times (M and N are integers) a sine wave signal obtained from a crystal resonator (1324) outside the processor. Generate.

  The clock driver (1312) amplifies the high frequency signal received from the PLL circuit to a signal strength sufficient to supply a clock signal to each functional block.

  The low voltage detection circuit (1313) monitors the power supply voltage, and issues a signal for controlling reset of the PLL circuit and other system reset when the power supply voltage is equal to or lower than a predetermined voltage. In addition, when an SRAM is provided inside or outside the processor and data retention by the battery of the SRAM is required, it has a function of issuing a battery backup control signal when the power supply voltage is lower than a predetermined voltage. .

  The external memory interface circuit (1314) has a function for connecting the second bus to the external bus, a second bus cycle length control register, and a memory map mode control register.

  This high-speed multiprocessor has two types of memory map modes and can be switched by a control register. In any memory map mode, the space of the external bus is roughly divided into two areas, a ROM area and a ROM / RAM area, and a different number of clocks for one bus cycle can be designated for each. The ROM area corresponds to the second bus area A, and the ROM / RAM space corresponds to the second bus area B.

  The DRAM refresh control circuit (1315) unconditionally acquires the right to use the first bus at regular intervals and controls the refresh operation of the DRAM.

  The sound processing processor (1303), graphic processing processor (1302), DMA control processor (1304), timer circuit (1309), input / output control circuit (1308), A / D converter (1310), central processing processor (1301) ) For generating an interrupt request signal. These correspond to the interrupt request signals A to F shown in FIG.

  The first effect when the high-speed multiprocessor is used is that the bus is divided into the first bus and the second bus according to the response speed and data transfer capability of the bus slave. This increases the processing efficiency of the high-speed multiprocessor as a whole.

  The second effect is that each bus master has an interface to the first bus and the second bus independently, and when one bus is used, the other bus is not occupied unnecessarily. As with the effect of, the use efficiency of the shared bus is increased.

  The third effect is that the bus cycle is not determined by the bus cycle speed of the bus master, but the bus cycle is determined at the highest speed at which the bus slave and the bus itself can operate. Even when a bus master having a low-speed bus cycle accesses, the bus use efficiency does not decrease.

  The fourth effect is that a plurality of physical address spaces are arranged on a single logical address space as in the central processing processor shown in the embodiment, so that the plurality of physical address spaces can be programmed. It is possible to handle it uniformly and continuously.

  The fifth effect is that the bus arbitration circuit is configured as described above to give weight to the distribution of the bus use right of each bus master and to acquire the bus use right for all the bus masters within a certain period. In addition, it is possible to increase the overall processing capacity of the entire system by dynamically changing the weighting of the bus usage right allocation of the bus master in response to changes in processing contents. It is.

  The sixth effect is that the high-speed multiprocessor shown in this embodiment is realized on a single semiconductor element, thereby providing a plurality of buses, and each bus master independently having an interface to a plurality of buses. Therefore, it becomes possible to realize a high-performance system with a very simple external circuit.

It is explanatory drawing which shows the outline | summary of the high-speed processor concerning this invention. It is explanatory drawing which shows the structural example of the central processing processor used for the said high speed processor. It is explanatory drawing which shows the memory map mode 1 of the logical address space of the said central processing processor. It is explanatory drawing which shows the memory map mode 2 of the logical address space of the said central processing processor. It is a timing chart which shows the 1st bus usage example of the said central processing processor. It is a timing chart which shows the 2nd bus usage example of the said central processing processor. It is a circuit diagram which shows the outline | summary of a 1st bus arbitration circuit. It is a table | surface which shows the example of a setting of the priority order information in a 1st bus arbitration circuit. It is a table | surface which shows the example of the priority order | rank order which priority order information represents. It is a timing chart which shows the example 1 of arbitration of the 1st bus. It is a timing chart which shows the example 2 of arbitration of the 1st bus. It is a circuit diagram which shows the outline | summary of a 2nd bus arbitration circuit. It is a timing chart which shows the example of mediation of the 2nd bus. It is a table | surface which shows the example of a setting of the priority order information in a 2nd bus arbitration circuit. It is a circuit diagram which shows the Example using the high-speed processor concerning this invention. It is explanatory drawing of the conventional bus system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Bus master 2 ... Bus master 10 ... Bus 11 ... Bus 20 ... Bus slave 21 ... Bus slave

Claims (3)

Shared bus,
A plurality of bus masters each connected directly to the shared bus;
A plurality of bus slaves each connected to the shared bus;
A bus arbitration circuit that always determines the right to use the bus for each bus cycle of the shared bus, and gives a shared bus use permission signal to one of the bus masters at the start of one bus cycle;
The shared bus is divided into a first area and a second area, and an address issued by the bus master that has received the shared bus use permission signal corresponds to either the first area or the second area. Is determined for each bus cycle of the shared bus, the first bus cycle period length is determined if it corresponds to the first area, and the second length is determined if it corresponds to the second area. Bus cycle length control means for determining the bus cycle period length of the bus cycle as a length of the bus cycle and issuing a bus cycle end signal at the end of each bus cycle according to the determined bus cycle length,
The high-speed processor, wherein the bus master starts transmission / reception of data on the shared bus by the shared bus use permission signal and ends transmission / reception of data by the bus cycle end signal.   The bus arbitration circuit does not depend on the bus cycle speed of the bus master, and is one of the fastest time for accessing the bus slave connected to the shared bus and the fastest time for which the shared bus is operable. 2. The high speed processor according to claim 1, wherein the later one is defined as a bus cycle period of the shared bus, and the right to use the bus is always determined every bus cycle. A first memory map mode in which the first area and the second area are arranged in a first form; and a second memory in which the first area and the second area are arranged in a second form. A memory map mode switching control register that switches between map modes is further provided.
The high speed processor according to claim 1 or 2, wherein the first mail map mode and the second memory map mode are respectively shared by all the bus masters.

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