JP2004127245A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize memory distribution according to an application. <P>SOLUTION: This semiconductor integrated circuit device is provided with a plurality of internal memories 20-23, a main processor 24 serving as a first processing unit having a codec function, and a video interface 25 and a graphic processor 26 serving as a second processing unit controlling processing of a video display system. A semiconductor integrated circuit device 10 connected to a CPU 11 serving as an external processing unit and to an external memory 14 to be operated is provided with a memory configuration control part 31 controlling memory distribution according to the application to the first and second processing units and the external processing unit. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device having a plurality of internal memories and a plurality of processing units for data processing, respectively, and operating while being connected to an external processing unit.
[0002]
[Prior art]
According to a first conventional technique, in a shared memory device that performs contention control in response to a DMA transfer request from a plurality of communication controllers, even when a certain memory bank is in use, other memory banks can be accessed, thereby enabling each communication bank to communicate. A technique for reducing the frequency of waiting for a controller to access a shared memory has been disclosed (see Patent Document 1).
[0003]
A second conventional technique discloses a technique for flexibly connecting each processor and each memory bank in a multi-bank memory mixed multiprocessor system LSI (see Patent Document 2).
[0004]
A third prior art discloses a printer device in which access to each memory bank constituting a memory is arbitrated for each memory bank so that each memory bank can be accessed simultaneously. (See Patent Document 3).
[0005]
A fourth prior art discloses a microprocessor in which a plurality of resources share a single memory and can perform no-wait access in parallel (see Patent Document 4).
[0006]
[Patent Document 1]
JP-A-10-27131
[Patent Document 2]
JP-A-10-260952
[Patent Document 3]
JP-A-2000-99391
[Patent Document 4]
JP 2001-43180 A
[0007]
[Problems to be solved by the invention]
Now, in a semiconductor integrated circuit device having a plurality of internal memories and a plurality of processing units each for data processing and operating while being connected to an external processing unit, it is important to allocate memory to each processing unit. .
[0008]
SUMMARY OF THE INVENTION An object of the present invention is to enable a suitable memory allocation according to an application.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention relates to a semiconductor integrated circuit device which operates while being connected to an external processing unit, comprising: a plurality of internal memories; first and second processing units each for data processing; A configuration including a processing unit, a memory configuration control unit for controlling allocation of the plurality of internal memories according to an application to the second processing unit and the external processing unit is adopted. .
[0010]
ADVANTAGE OF THE INVENTION According to this invention, the suitable memory distribution according to an application can be implement | achieved. For example, a plurality of internal memories may be allocated to each of the first processing unit, the second processing unit, and the external processing unit, or all of the plurality of internal memories may be occupied by the first or second processing unit. it can. Further, it is also possible to occupy all of the plurality of internal memories in the external processing unit. In the last example, the semiconductor integrated circuit device operates as a mere memory device for an external processing unit.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0012]
FIG. 1 shows an example of the internal configuration of a semiconductor integrated circuit device according to the present invention and an example of its external connection. The semiconductor integrated circuit device 10 shown in FIG. 1 is for image processing, and comprises a CPU 11 as an external processing unit, a camera 12 for image input, a liquid crystal display (LCD) 13 for image display, and an SDRAM. It operates by being connected to the external memory 14. The maximum storage capacity of the external memory 14 is, for example, 256 Mbit (megabit).
[0013]
The semiconductor integrated circuit device 10 in FIG. 1 is a first processing unit for processing image data having a plurality of internal memories 20 to 23 including SRAMs 0 to 3 and a codec (encode / decode) function based on MPEG-4. A certain main processor (MP) 24, a video interface (VIF) 25 and a graphics processor (GFX) 26, which are second processing units for image data processing for processing a video (Video) display system, and a host interface ( HIF) 27 and an asynchronous serial interface (UART) 28. The storage capacity of each of the internal memories 20 to 23 is, for example, 2 Mbit or 4 Mbit. The video interface 25 is connected to the camera 12 and the liquid crystal display 13, and the host interface 27 and the asynchronous serial interface 28 are connected to the CPU 11, respectively.
[0014]
The semiconductor integrated circuit device 10 of FIG. 1 further includes a memory control unit 30 having a memory configuration control unit 31. The memory configuration control unit 31 controls memory allocation to each of the main processor 24, the video interface 25, the graphics processor 26, and the CPU 11 according to an application. The main processor 24 uses a memory assigned to the main processor 24 among the internal memories 20 to 23 and the external memory 14 as a work area. The video interface 25 and the graphics processor 26 use the memory allocated to the video interface 25 and the graphics processor 26 among the internal memories 20 to 23 and the external memory 14 as a frame area generally called a frame memory. . The CPU 11 uses a memory assigned to the CPU 11 among the internal memories 20 to 23 and the external memory 14 as a CPU area.
[0015]
The memory control unit 30 includes a work area memory interface (WMIF) 32 as a first memory interface, a frame area memory interface (FMIF) 33 as a second memory interface, and a CPU area memory interface (CPUIF) as a third memory interface. ) 34. Correspondingly, the semiconductor integrated circuit device 10 of FIG. 1 includes a WM bus (first data bus) 40, an FM bus (second data bus) 41, and a CPU bus (third data bus) 42 dedicated to the CPU 11. Are provided. The WMIF 32 arbitrates / controls a DMA data transfer request by interposing between the work area allocated to the main processor 24 and the WM bus 40. The FMIF 33 arbitrates and controls a DMA data transfer request by interposing between the frame area allocated to the video interface 25 and the graphics processor 26 and the FM bus 41. The CPUIF 34 is an interface that intervenes between the CPU area and the CPU bus 42 and controls data transfer. As described above, the memory allocated to the work area is accessed via the WMIF 32, the memory allocated to the frame area is accessed via the FMIF 33, and the memory allocated to the CPU area is accessed via the CPUIF. I have. Note that a host bus 43 is provided between the graphics processor 26 and the host interface 27. The main processor 24 has a local bus 44 connected to the host interface 27.
[0016]
The main processor 24 is connectable to either the WM bus 40 or the FM bus 41 via the MP bus selector 50, and includes a plurality of local memories (DM1, DM2 and DM3) 51 to 53 and a plurality of hardware An engine (ENG) 54 is provided on the local bus 44. Each hardware engine 54 is a partial processing core for encoding / decoding MPEG image data. The video interface 25 can be connected to either the WM bus 40 or the FM bus 41 via a VIF bus selector 55. The graphics processor 26 can be connected to only the FM bus 41 of the WM bus 40 and the FM bus 41. The host interface 27 can be connected to either the WM bus 40 or the FM bus 41 via the HIF bus selector 60. Further, the host interface 27 can be connected to either the CPUIF 34 or the FM bus 41 via the CPU bus 42 and the CPU IF bus selector 61. The asynchronous serial interface 28 can be connected to either the WM bus 40 or the FM bus 41 via a UART bus selector 62.
[0017]
The main processor 24 transfers the DMA data between the local memories 51 to 53 and the work area through the bus selector 50, the WM bus 40 and the WMIF 32, and the MP between the local memories 51 to 53 and the frame area. DMA data transfer via the bus selector 50, the FM bus 41, and the FMIF 33 can be commanded. Further, the main processor 24 transfers DMA data between the host memory incorporated in the host interface 27 and the work area via the HIF bus selector 60, the WM bus 40 and the WMIF 32, and executes the host interface incorporated in the host interface 27. It is possible to instruct DMA data transfer between the memory and the frame area via the HIF bus selector 60, the FM bus 41, and the FMIF 33. Further, the main processor 24 includes a UART bus selector 62, a WM bus 40, and a DMA data transfer between the work area and the FIFO memory built in the asynchronous serial interface 28, and a DMA data transfer, and the main processor 24 is built in the asynchronous serial interface 28. A DMA data transfer via the UART bus selector 62, the FM bus 41, and the FMIF 33 between the FIFO memory and the frame area can be commanded. The DMA data transfer between the local memories 51 to 53 and the work area, and the DMA data transfer between the host memory built in the host interface 27 or the FIFO memory built in the asynchronous serial interface 28 and the frame area, Can be executed in parallel. Also, DMA data transfer between the local memories 51 to 53 and the frame area, and DMA data transfer between the host memory built in the host interface 27 or the FIFO memory built in the asynchronous serial interface 28 and the work area. Can be executed in parallel.
[0018]
Further, the main processor 24 transfers DMA data between the built-in memory of the video interface 25 and the work area via the VIF bus selector 55, the WM bus 40 and the WMIF 32, and transfers the DMA data between the built-in memory of the video interface 25 and the frame area. DMA data transfer via the VIF bus selector 55, the FM bus 41 and the FMIF 33 can be instructed. The main processor 24 can also instruct DMA data transfer between the built-in memory of the graphics processor 26 and the frame area via the FM bus 41 and the FMIF 33. The DMA data transfer between the local memories 51 to 53 of the main processor 24 and the work area and the DMA data transfer between the built-in memory of the video interface 25 or the graphics processor 26 and the frame area can be executed in parallel. . The DMA data transfer between the local memory 51 to 53 of the main processor 24 and the frame area and the DMA data transfer between the video interface 25 or the built-in memory of the graphics processor 26 and the work area can be executed in parallel. It is. The main processor 24 can also perform data processing using the local memories 51 to 53, for example, while DMA data transfer for the video interface 25 is being performed.
[0019]
The CPU 11 is provided with three memory access paths for parallel data. The first is access via the host interface 27. For example, writing from the CPU 11 is performed on a host memory built in the host interface 27. In response, the main processor 24 commands DMA data transfer between the host memory and the work area or frame area. Thereby, the CPU 11 can achieve writing of the graphics data into a part of the frame area, for example. The second is a path when the CPU 11 accesses the CPU area without passing through the host memory, and is a path from the CPU 11 to the CPU area via the host interface 27, the CPU bus 42, the CPU IF bus selector 61 and the CPU IF 34. . The third is a path in a case where the CPU 11 accesses the frame area without passing through the host memory. The CPU 11 transmits the frame area via the host interface 27, the CPU bus 42, the CPU IF bus selector 61, the FM bus 41, and the FMIF 33. It is a route to reach. When the second route is selected, the CPU 11 specifies the relative address of the memory. When the DMA data transfer by the first or third route is selected, the CPU 11 specifies the absolute address of the memory and requests other DMA data transfer (such as the video interface 25 and the graphics processor 26). Reconciliation is conducted. Note that the DMA priority of the CPU 11 is preferably set to be lower than that of the graphics processor 26.
[0020]
FIG. 2 shows a detailed configuration example of the memory configuration control unit 31 in FIG. The memory configuration control unit 31 includes a setting unit 70. The setting unit 70 includes a first register 71 for specifying a use of each memory, a second register 72 for specifying a storage capacity of each memory, and The read / write control unit 73 distributes access signals from the WMIF 32, the FMIF 33, and the CPU IF 34 to the respective memories according to the registers 71 and 72. The first and second registers 71 and 72 can be arbitrarily set by the main processor 24 and the CPU 11, respectively.
[0021]
FIG. 3 shows an example of memory allocation for each operation mode according to the application of the semiconductor integrated circuit device 10 of FIG. Here, it is assumed that each of the four internal memories 20 to 23 has a storage capacity of 2 Mbit. That is, the total capacity of the internal memories 20 to 23 is 8 Mbit. The memory configuration control unit 31 plays an important role for effectively utilizing these limited memory resources. For example, in the operation mode A, the main processor 24 occupies all of the internal memories 20 to 23. In the operation mode B, 6 Mbit of the total capacity of the internal memories 20 to 23 is allocated to the main processor 24, and 2 Mbit is allocated to the video interface 25 and the graphics processor 26. In the operation mode C, 4 Mbit of the total capacity of the internal memories 20 to 23 is allocated to the main processor 24 and 4 Mbit is allocated to the video interface 25 and the graphics processor 26, respectively. In the operation mode D, 4 Mbit of the total capacity of the internal memories 20 to 23 is allocated to the main processor 24, 2 Mbit is allocated to the video interface 25 and the graphics processor 26, and 2 Mbit is allocated to the CPU 11. In the operation mode E, 4 Mbit of the total capacity of the internal memories 20 to 23 is allocated to the video interface 25 and the graphics processor 26, and 4 Mbit is allocated to the CPU 11. In the operation mode F, all of the internal memories 20 to 23 are occupied by the video interface 25 and the graphics processor 26. In the operation mode G, the CPU 11 occupies all of the internal memories 20 to 23. In the last operation mode G, the main functions of the main processor 24, the video interface 25, and the graphics processor 26 are stopped, and the semiconductor integrated circuit device 10 operates as a mere memory device for the CPU 11. As described above, the memory configuration control unit 31 can achieve the purposeful memory distribution according to the application. The MPEG-4 processing by the main processor 24, the video display processing by the video interface 25 and the graphics processor 26, and the processing by the CPU 11 can operate in parallel with each other.
[0022]
FIG. 4A shows an example of the first register 71 having a 10-bit configuration, and FIG. 4B shows the meaning of the least significant two bits of the register. If the bits 1 and 0 of the first register 71 assigned to the SRAM0, which is one of the internal memories 20 to 23, are "00", the SRAM0 is a work area if the bits 01 and 01 are "01". If so, SRAM0 is used as the CPU area. If the SRAM0 is not used because it is defective, for example, “11” may be set in the bits 1 and 0 of the first register 71. In this case, the power supply to the SRAM0 is stopped, and the address is not allocated to the SRAM0. Similarly, bits 3 and 2 of the first register 71 specify the use of the SRAM 1, bits 5 and 4 specify the use of the SRAM 2, bits 7 and 6 specify the use of the SRAM 3, and bits 9 and 8 specify the use of the external memory 14 including the SDRAM. . Note that data transfer between the WM bus 40, the FM bus 41, and the CPU bus 42 can be achieved by appropriately rewriting the contents of the first register 71. For example, if the bits 3 and 2 of the first register 71 are changed from “00 (work area)” to “01 (frame area)”, the SRAM 1 is one of the internal memories 20 to 23 via the WM bus 40. The written data can be read out to the FM bus 41.
[0023]
The first register 71 can be changed during the operation of a memory for which a DMA reservation has not been made, but the contents of the first register 71 for a memory which has made a DMA reservation and is being accessed or may be accessed. Should not be changed. The change of the first register 71 is basically performed under the responsibility of software of the main processor 24.
[0024]
FIG. 5A shows an example of a 6-bit second register 72 for designating the storage capacity of each memory, FIG. 5B shows the meaning of the least significant bit of the register 72, and FIG. Indicates the meaning of the two most significant bits of the register 72. If the bit 0 of the second register 72 assigned to the SRAM0, which is one of the internal memories 20 to 23, is "0", the SRAM0 has a storage capacity of 2 Mbits, and if the bit is "1", the SRAM0 has a storage capacity of 4 Mbits. . Similarly, bit 1 of the second register 72 specifies the storage capacity of the SRAM 1, bit 2 specifies the storage capacity of the SRAM 2, and bit 3 specifies the storage capacity of the SRAM 3. If the bits 5 and 4 of the second register 72 assigned to the external memory 14 made of SDRAM are "01", the SDRAM has a storage capacity of 64 Mbit, and if "10", the SDRAM has a storage capacity of 128 Mbit. If "11", the SDRAM has a storage capacity of 256 Mbits. If the external memory 14 is not used for some reason, “00” may be set in the bits 5 and 4 of the second register 72. The contents of the second register 72 are determined when the semiconductor integrated circuit device 10 is started.
[0025]
FIG. 6A shows an example in which an absolute address is specified in the memory assigned to the CPU 11 in the semiconductor integrated circuit device 10 in FIG. 1, and FIG. 6B shows an example in which a relative address is specified in the memory assigned to the CPU 11. Each is shown. Here, the storage capacity of each of the internal memories 20 to 23 is 2 Mbit, the storage capacity of the external memory 14 is 128 Mbit, and the SRAM0 and the SRAM1 of the internal memories 20 to 23 are both in the work area, It is assumed that the SRAM 2 and the SRAM 3 among 20 to 23 are designated as the CPU area, and the external memory 14 is designated as the frame area. According to both figures, for example, from the viewpoint of the main processor 24, addresses are allocated to each memory as one continuous address space regardless of the work area, the frame area, and the CPU area. On the other hand, as the address map of the CPU area seen from the external CPU 11, either the absolute address in FIG. 6A or the relative address in FIG. 6B can be selected. According to the relative address designation in FIG. 6B, the CPU area is always mapped from the address 0, so that the load on the CPU 11 is reduced.
[0026]
FIG. 7 shows a configuration example of a mobile communication terminal (for example, a mobile phone) using the semiconductor integrated circuit device 10 of FIG. 1 as an image processor. The mobile communication terminal in FIG. 7 includes a baseband unit 81, an audio processor 83, and a memory 88 in addition to the image processor 10, the CPU 11, the camera 12, the liquid crystal display 13, and the SDRAM 14 described above. The image processor 10, the CPU 11, the baseband unit 81, the audio processor 83, and the memory 88 are connected to each other via a main bus 80. Further, as described above, the asynchronous serial interface 28 in the image processor 10 enables serial communication between the image processor 10 and the CPU 11 (see FIG. 1).
[0027]
The baseband unit 81 transmits and receives the multiplexed stream via the antenna 82. A speaker 85 is connected to the audio processor 83 via a digital-analog converter (DAC) 84, and a microphone 86 is connected via an analog-digital converter (ADC) 87. For example, when the baseband unit 81 receives the multiplexed stream, the CPU 11 separates the multiplexed stream into an audio stream and an image stream, and the audio stream is transmitted to the audio processor 83 via the main bus 80. Are supplied to the image processor 10 by serial communication. Then, the audio processor 83 performs a decoding process on the audio stream, and an audio output is obtained from the speaker 85. On the other hand, the image processor 10 decodes the image stream, and outputs the image data obtained by the decoding to the liquid crystal display 13 while storing the image data in the work area.
[0028]
The mobile communication terminal in FIG. 7 further includes an IO bus 90, and a plurality of interfaces 91 are connected to the IO bus 90. A keypad 92 is connected to one of the plurality of interfaces 91. When receiving an input from the keypad 92, the CPU 11 directly writes graphics data corresponding to the input to the CPU area via the CPU IF 34 in the image processor 10. The image processor 10 changes the memory configuration from the CPU area to the frame area and from the frame area to the CPU area according to an instruction from the CPU 11 or the main processor 24, and changes the graphics data in the frame area and the image data in the work area. And outputs the result to the liquid crystal display 13.
[0029]
The image processor 10 can perform MPEG encoding on an image input from the camera 12 and output the result of the processing to the CPU 11 via the asynchronous serial interface 28. Alternatively, when the CPU 11 performs the JPEG encoding process on the image captured by the camera 12 and stored in the work area, the memory configuration is changed from the work area to the CPU area in accordance with an instruction from the CPU 11 or the main processor 24, and the CPU 11 Still image data is directly read from the area by the CPU 11.
[0030]
As described above, the semiconductor integrated circuit device 10 of FIG. 1 is suitably used for a mobile communication terminal for image processing.
[0031]
【The invention's effect】
As described above, according to the present invention, in a semiconductor integrated circuit device operating by being connected to an external processing unit, a plurality of internal memories, first and second processing units for data processing respectively, One processing unit, the second processing unit, and a memory configuration control unit for controlling the allocation of the plurality of internal memories according to the application to the external processing unit, and a configuration including a memory configuration control unit, A purposeful memory allocation can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of an internal configuration of a semiconductor integrated circuit device according to the present invention and an example of its external connection.
FIG. 2 is a block diagram illustrating a detailed configuration example of a memory configuration control unit in FIG. 1;
FIG. 3 is a diagram showing an example of memory allocation for each operation mode according to an application of the semiconductor integrated circuit device of FIG. 1;
4A is a diagram showing an example of a first register for designating the use of each memory in the semiconductor integrated circuit device of FIG. 1, and FIG. 4B is a diagram showing the meaning of the least significant 2 bits of the register; is there.
5A shows an example of a second register for specifying the storage capacity of each memory in the semiconductor integrated circuit device of FIG. 1, FIG. 5B shows the meaning of the least significant bit of the register, and FIG. FIG. 3 is a diagram showing the meaning of the two most significant bits of the register.
6A shows an example in which an absolute address is specified in a memory allocated to an external CPU in the semiconductor integrated circuit device of FIG. 1, and FIG. 6B shows a case in which a relative address is specified in a memory allocated to the external CPU; It is a figure which shows the example performed each.
FIG. 7 is a block diagram illustrating a configuration example of a portable communication terminal using the semiconductor integrated circuit device of FIG. 1 as an image processor.
[Explanation of symbols]
10 Semiconductor integrated circuit device (image processor)
11 CPU (external processing unit)
12 Camera
13. Liquid Crystal Display (LCD)
14. External memory (SDRAM)
20-23 Internal memory (SRAM0-3)
24 Main Processor (MP: First Processing Unit)
25 Video interface (VIF: 2nd processing unit)
26 Graphics Processor (GFX: Second Processing Unit)
27 Host Interface (HIF)
28 Asynchronous serial interface (UART)
30 Memory control unit
31 Memory configuration controller
32 WMIF (first memory interface)
33 FMIF (second memory interface)
34 CPUIF (third memory interface)
40 WM bus (first data bus)
41 FM bus (second data bus)
42 CPU bus (third data bus)
43 Host Bus
44 Local bus for MP
50 MP bus selector (first bus selector)
51-53 MP local memory
54 MP Hardware Engine
55 VIF bus selector (second bus selector)
60 HIF bus selector (third bus selector)
61 CPU IF bus selector (4th bus selector)
62 UART Bus Selector
70 Setting section
71 1st register
72 Second register
73 Read / write control unit
80 Main Bus
81 Baseband section
83 audio processor

Claims (12)

A semiconductor integrated circuit device that operates by being connected to an external processing unit,
Multiple internal memories,
First and second processing units each for data processing;
A semiconductor configuration comprising: a memory configuration control unit configured to control allocation of the plurality of internal memories to the first processing unit, the second processing unit, and the external processing unit according to an application. Circuit device. The semiconductor integrated circuit device according to claim 1,
A first data bus connected to the first processing unit;
A second data bus connected to the second processing unit;
A third data bus dedicated to the external processing unit;
A first memory interface interposed between the memory allocated to the first processing unit and the first data bus to control DMA data transfer;
A second memory interface interposed between the memory allocated to the second processing unit and the second data bus to manage DMA data transfer;
A semiconductor integrated circuit device, further comprising a third memory interface interposed between the memory assigned to the external processing unit and the third data bus to control data transfer. The semiconductor integrated circuit device according to claim 1,
A semiconductor integrated circuit device, wherein the memory configuration control unit further has a function of controlling allocation of an external memory to the first processing unit, the second processing unit, and the external processing unit according to an application. . The semiconductor integrated circuit device according to claim 3,
The memory configuration control unit has a first register for specifying the allocation of the plurality of internal memories and the external memory,
A semiconductor integrated circuit device configured to achieve data transfer between the first to third data buses by rewriting the contents of the first register. The semiconductor integrated circuit device according to claim 4,
The semiconductor integrated circuit device according to claim 1, wherein the first register is configured to specify that any one of the plurality of internal memories and the external memory is not used. The semiconductor integrated circuit device according to claim 3,
The semiconductor integrated circuit device, wherein the memory configuration control unit has a second register for specifying a storage capacity of each of the plurality of internal memories and the external memory. 3. The semiconductor integrated circuit device according to claim 2,
A first bus selector for controlling a selective connection between the first processing unit and the first or second data bus;
A semiconductor integrated circuit device further comprising a second bus selector for controlling selective connection between the second processing unit and the first or second data bus. 3. The semiconductor integrated circuit device according to claim 2,
The first processing unit has a local memory;
A semiconductor integrated circuit device configured to perform DMA data transfer between a memory allocated to the first processing unit and the local memory. 3. The semiconductor integrated circuit device according to claim 2,
A host interface interposed between the external processing unit and the third data bus;
A semiconductor integrated circuit device further comprising a third bus selector for controlling selective connection between the host interface and the first or second data bus. 3. The semiconductor integrated circuit device according to claim 2,
A semiconductor integrated circuit device further comprising a fourth bus selector for controlling a selective connection between the third data bus and the third memory interface or the second data bus. The semiconductor integrated circuit device according to claim 10,
When the fourth bus selector selects the connection between the third data bus and the third memory interface, the fourth bus selector selects the connection between the third data bus and the second data bus. A semiconductor integrated circuit device configured to receive an absolute address from each of the external processing units. A mobile communication terminal comprising the semiconductor integrated circuit device according to any one of claims 1 to 11 for image processing.

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