WO2006004166A1

WO2006004166A1 - Data processing unit and compatible processor

Info

Publication number: WO2006004166A1
Application number: PCT/JP2005/012516
Authority: WO
Inventors: Shuhei Kato; Koichi Sano; Koichi Usami
Original assignee: Ssd Company Limited
Priority date: 2004-07-02
Filing date: 2005-06-30
Publication date: 2006-01-12
Also published as: WO2006004166A8; JP2008505386A

Abstract

A processor maintaining backward compatibility with a previous generation processor is provided. When an operation is performed in a current generation processor 100 for writing a value to an address, which is the same address as assigned to a zeroth area access cycle number register of a previous generation processor 500, the same value is written to a zeroth area random access cycle number register 170, and a zeroth area page size register 190 is set to '0' (page size = 0 byte) such that the page mode is disabled. On the other hand, when an operation is executed by the current generation processor 100 for writing a value to an address, which is the same address as assigned to a first and a second area access cycle number register of the previous generation processor 500, the same value is written to both a first area random access cycle number register 171 and a second area random access cycle number register 172, and a first area page size register 191 and a second area page size register 192 are set to '0' such that the page mode is disabled.

Description

DESCRIPTION

DATA PROCESSING UNIT AND COMPATIBLE PROCESSOR

Technical Field

The present invention relates to a data processing unit retaining backward compatibility with a previous generation processing unit and a compatible processor.

Background Art

A variety of techniques for maintaining backward compatibility with a previous generation processor have been known as disclosed in Japanese Patent Published Applications Nos. Hei 11-232098, 11-232099 and 03-248240. Although not described in the above publications, when implementing backward compatibility, there are the following points to be considered.

The first point is the backward compatibility with regard to bus arbitration. The second point is the backward compatibility with regard to the access speed for accessing each of a plurality of address areas into which the address space of the processor is divided.

The third point is the backward compatibility with regard to the access modes for accessing the address space. The fourth point is the backward compatibility with regard to the structure of the address space to be accessed.

Disclosure of Invention

Accordingly, it is an object of the present invention to provide a data processing unit and a compatible processor in which backward compatibility with a previous generation processor is implemented with regard to bus arbitration.

It is another object of the present invention to provide a data processing unit and a compatible processor in which backward compatibility with a previous generation processor is implemented with regard to the access speeds for accessing the address areas.

It is a further object of the present invention to provide a data processing unit and a compatible processor in which backward compatibility with a previous generation processor is implemented with regard to the access modes for accessing the address space. It is a still further object of the present invention to provide a data processing unit and a compatible processor in which backward compatibility with a previous generation processor is implemented with regard to the structure of the address space to be accessed. In accordance with a first aspect of the present invention, a data processing unit is capable of running both the software that can be run on a predetermined another data processing unit comprising a first bus master group consisting of a predetermined plural number of bus masters and a first bus arbitor operable to perform bus arbitration in accordance with first priority ranking information about the order of priority among the plurality of bus masters belonging to the first bus master group, and the software that cannot be run on the predetermined another data processing unit, said data processing unit comprising: a second bus master group including bus masters which are provided corresponding respectively to the bus masters belonging to the first bus master group and further including one or more additional bus masters; and a second bus arbiter operable to perform bus arbitration in accordance with second priority ranking information about the order of priority among the bus masters belonging to said second bus master group, wherein the order of

• priority among the bus masters corresponding to the bus masters belonging to the first bus master group in accordance with the second priority ranking information is identical with the order of priority in accordance with the first priority ranking information. In accordance with this configuration, since the order of priority among the respective bus masters corresponding to the first bus master group for use in accordance with the second priority ranking information of the current generation data processing unit is identical with the order of priority in accordance with the first priority ranking information of the previous generation data processing unit, even if a new bus master is introduced into the current generation data processing unit in addition to the bus masters as implemented in the previous generation data processing unit, it is possible to properly run the software that can be run on the previous generation data processing unit (i.e., compatible software) also on the current generation data processing unit, and maintain the backward compatibility with regard to bus arbitration.

In accordance with a second aspect of the present invention, a data processing unit is capable of running both the software that can be run on a predetermined another data processing unit comprising a first bus master group consisting of a predetermined plural number of bus masters and a first bus arbitor operable to perform bus arbitration in accordance with first priority ranking information about the order of priority among the plurality of bus masters belonging to the first bus master group, and the software that cannot be run on the predetermined another data processing unit, said data processing unit comprising: a second bus master group including bus masters which are provided corresponding respectively to the bus masters belonging to the first bus master group, each bus- master belonging to said second bus master group being capable of issuing a bus use request for one or more bus use request purpose; and a second bus arbitor operable to perform bus arbitration on the basis of a second priority ranking information which determines the order of priority among all the bus use request purposes of the bus masters belonging to said second bus master group, wherein at least one of the bus masters belonging to said second bus master group is capable of issuing bus use requests for a plurality of the included bus use request purposes, and consecutive priority rankings are assigned to the plurality of the bus use request purposes, and wherein the order of priority among the bus masters in accordance with the second priority ranking information is identical with the order of priority among the corresponding bus masters in accordance with the first priority ranking information.

By this configuration, if one bus master has a plurality of bus use request purposes in accordance with the second priority ranking information, consecutive priority levels are assigned respectively to such bus use request purposes. Because of this, as seen from the software that can be run on the previous generation data processing unit (i.e., compatible software) in which bus use requests are not distinctively issued for the respective bus use request purposes, the second priority ranking information serves to provide the order of priority among the bus masters. In addition to this, the order of priority among the bus masters corresponding to the first bus master group in accordance with the second priority ranking information of the current generation data processing unit is identical with the order of priority among the corresponding bus masters of the previous generation data processing unit in accordance with the first priority ranking information.

As a result, in the case where the bus masters of the current generation data processing unit issue bus use requests on the basis of the bus use request purposes, it is possible to properly run the software that can be run on the previous generation data processing unit (i.e., compatible software) also in the current generation data processing unit, and maintain the backward compatibility with regard to bus arbitration.

In accordance with a third aspect of the present invention, a data processing unit is capable of running both the software that can be run on a predetermined another data processing unit comprising a first bus cycle length information storing unit operable to store a bus cycle length for accessing a predetermined address area, and the software that cannot be run on the predetermined another data processing unit, wherein the address area of said data processing unit corresponding to the predetermined address area is divided into a plurality of areas, wherein said data processing unit is provided with a plurality of second bus cycle length information storing units which are provided respectively for the plurality of areas and operable to store bus cycle lengths respectively for accessing the plurality of areas, wherein if an operation for rewriting the content stored in the first bus cycle length information storing unit is executed by said data processing unit while running, in said data processing unit, the software that can be run on the predetermined another data processing unit, the contents stored in all the second bus cycle length information storing units are rewritten by a value equivalent to the content stored in the first bus cycle length information storing unit. In accordance with this configuration, if an operation for rewriting the content stored in the first bus cycle length information storing unit is executed by the current generation data processing unit while running the compatible software on the current generation data processing unit, that is, if a write operation is executed by the current generation . data processing unit during running compatible software to the address assigned to the first bus cycle length information storing unit, the contents stored in all the second bus cycle length information 'storing units are rewritten by a value equivalent to the content stored in the first bus cycle length information storing unit.

As a result, even if the address space is not divided into a plurality of areas in the case of the previous generation data processing unit but is divided into a plurality of areas in the case of the current generation data processing unit which can set bus cycle lengths individually for the respective areas, it is possible for the current generation data processing unit to properly run the software that can be run on the previous generation data processing unit (i.e., compatible software) and maintain the backward compatibility with regards to the access speed to the address space. In accordance with a fourth aspect of the present invention, a data processing unit is capable of running both the software that can be run on a predetermined another data processing unit comprising a first bus cycle length information storing unit operable to store a bus cycle length for accessing a predetermined address area, and the software that cannot be run on the predetermined another data processing unit, said data processing unit comprising: a second bus cycle length information storing unit operable to store a bus cycle length for accessing the predetermined address area in a first access mode; and a third bus cycle length information storing unit operable to store a bus cycle length for accessing the predetermined address area in a second access mode, wherein if an operation for rewriting the content stored in the first bus cycle length information storing unit is executed by said data processing unit while runningthe software that can be run on the predetermined another data processing unit, the content stored in said second bus cycle length information storing unit and the content stored in said third bus cycle length information storing unit are rewritten by a value equivalent to the content to be stored in the first bus cycle length information storing unit. In accordance with this configuration, if an operation for rewriting the content stored in the first bus cycle length information storing unit is executed by the current generation data processing unit while running the compatible software on the current generation data processing unit, that is, if a write operation is executed by the current generation data processing unit during running compatible software to the address assigned to the first bus cycle length information storing unit, the content stored in said second bus cycle length information storing unit corresponding to the first access mode and the content stored in said third bus cycle length information storing unit corresponding to the second access mode are rewritten by a value equivalent to the content stored in said first bus cycle length information storing unit of the previous generation processor.

As a result, since the first access mode and the second access mode become substantially equivalent to each other, even if the previous generation data processing unit supports only one of the first access mode or the second access mode, it is possible to properly run the software that can be run on the previous generation data processing unit (i.e., compatible software) also in the current generation data processing unit, and maintain the backward compatibility with regards to the access mode for accessing the address space.

In accordance with a fifth aspect of the present invention, a data processing unit is capable of running both the software that can be run on a predetermined another data processing unit comprising a first bus cycle length information storing unit operable to store a bus cycle length for accessing a predetermined address area, and the software that cannot be run on the predetermined another data processing unit, said data processing unit comprising: a second bus cycle length information storing unit operable to store a bus cycle length for accessing the predetermined address area in a random access mode; a third bus cycle length information storing unit operable to store a bus cycle length for accessing the predetermined address area in a page mode; and a page size information storing unit operable to store a size of one page for the page mode, wherein if an operation for rewriting the content stored in the first bus cycle length information storing unit is executed by said data processing unit while running the software that can be run on said predetermined another data processing unit, the content stored in said second bus cycle length information storing unit is rewritten by a value equivalent to the content to be stored in the first bus cycle length information storing unit, and said page size information storing unit indicative of the size of one page is rewritten by a value indicating that the page mode is disabled.

In accordance with this configuration, if an operation for rewriting the content stored in the first bus cycle length information storing unit is executed by the current generation data processing unit while running the compatible software on the current generation data processing unit, that is, if a write operation is executed by the current generation data processing unit during running compatible software to the address assigned to the first bus cycle length information storing unit, the page size information storing unit indicative of the size of one page is rewritten by a value indicating that the page mode is disabled. In addition to this, the content stored in the second bus cycle length information storing units is rewritten by a value equivalent to the content stored in said first bus cycle length information storing unit.

As a result, even if the previous generation data processing unit does not support a page mode, it is possible to properly run the software that can be run on the previous generation data processing unit (i.e., compatible software) also on the current generation data processing unit, and maintain the backward compatibility with regards to the access mode for accessing the address space.

In accordance with a sixth aspect of the present invention, a data processing unit is capable of running both the software that can be run on a predetermined another data processing unit comprising a first bus cycle length information storing unit operable to store a bus cycle length for accessing a predetermined address area, and the software that cannot be run on the predetermined another data processing unit, wherein the address area of said data processing unit corresponding to the predetermined address area is divided into a plurality of areas, said data processing unit comprising: a plurality of second bus cycle length information storing units provided respectively for the plurality of areas and operable to store bus cycle lengths respectively for accessing the plurality of areas in a random access mode; a plurality of third bus cycle length information storing units provided respectively for the plurality of areas and operable to store bus cycle lengths respectively for accessing the plurality of areas in a page mode; and a plurality of page size information storing units provided respectively for the plurality of areas and individually operable to store a size of one page for the page mode, wherein if an operation for rewriting the content stored in said first bus cycle length information storing unit is executed by said data processing unit while running the software that can be run on the predetermined another data processing unit, the contents stored in all said second bus cycle length information storing units are rewritten by a value equivalent to the content to be stored in the first bus cycle length information storing unit and all of said page size information storing units indicative of the size of one page is rewritten by a value indicating that the page mode is disabled. In accordance with this configuration, if an operation for rewriting the content stored in the first bus cycle length information storing unit is executed by the current generation data processing unit while running the compatible software on the current generation data processing unit, that is, if a write operation is executed by the current generation data processing unit during running compatible software to the address assigned to the first bus cycle length information storing unit, the contents stored in all the second bus cycle length information storing units are rewritten by a value equivalent to the content stored in the first bus cycle length information storing unit, and the contents stored in all the page size information storing units indicative of the size of one page are rewritten by a value indicating that the page mode is disabled.

As a result, even if the address space is not divided into a plurality of areas in the case of the previous generation data processing unit but is divided into a plurality of areas in the case of the current generation data processing unit which can set bus cycle lengths individually for the respective areas, and even if the previous generation data processing unit does not support a page mode, it is possible for the current generation data processing unit to properly run the software that can be run on the previous generation data processing unit (i.e., compatible software) and maintain the backward compatibility with regards to the access speed and the access mode to the address space.

In accordance with a seventh aspect of the present invention, a data processing unit is capable of running both the software that can be run on a predetermined another data processing unit which operates in a logical address space of "P" bits ("P" is one or a larger integer) and comprises a first bus master and a second bus master, and the software that cannot be run on the predetermined another data processing unit, wherein the logical address space of said data processing unit is addressed by address information of "Q" bits (Q is an integer larger than "P") , and divided into a first address space accessible by addresses of which the upper (Q- P) bits of Q bits are fixed respectively to "0" and a second address space corresponding to all the logical address space from which the first address space is excluded, said data processing unit comprising: a third bus master has the same function as the first bus master and can access only the first address space; a fourth bus master has the same function as the second bus master and has an additional function to access both the first address space and the second address space; and a fifth bus master has a different function than the first bus master and the second bus master have, and has a function to access both the first address space and the second address space.

In accordance with this configuration, when the software (i.e., compatible software) that can be run on the previous generation data processing unit is run on the current generation data processing unit, the third bus master and the fourth bus master of the current generation data processing unit can access the first address space only by fixing the upper (Q-P) bits of Q bits respectively to "0" in the current generation data processing unit, and the compatibility with regards to the address space can easily be maintained.

Also, since the fourth bus master of the current generation data processing unit having the same function as the second bus master of the previous generation data processing unit is provided with an additional function to access not only the first address space but also the second address space which is not accessible by the second bus master, it is possible to extend the addressable address areas while maintaining backward compatibility with the previous generation data processing unit. Furthermore, the current generation data processing unit is implemented with the fifth bus master having a new function, of which counterpart does not exist in the previous generation data processing unit, capable of accessing both the first address space and the second address space. However, the compatibility with the previous generation data processing unit shall not be affected thereby because the previous generation data processing unit has no bus master having such a function. In this manner, it is possible to implement the current generation data processing unit with the fifth bus master having a new function without giving up backward compatibility. In accordance with an eighth aspect of the present invention, a compatible processor capable of running the software that can be run on a previous generation processor, said compatible processor comprising: a plurality of compatible bus masters which are compatible respectively with previous bus masters of the previous generation processor; and a compatible bus arbitor operable to perform arbitration of bus use requests issued by said compatible bus masters, wherein the bus use requests issued by said compatible bus masters during running any implementation of the software in said compatible processor are always granted in the same order of priority as the bus use requests issued by the previous bus masters during running the any implementation of the software in the previous generation processor.

In accordance with this configuration, it is possible to provide a compatible processor in which backward compatibility with a previous generation processor is implemented with regard to bus arbitration. In accordance with a ninth aspect of the present invention, a processor comprising arithmetic logical circuitry is operable to process data and a real control register operable to control the operation of processing data, wherein a virtual control register is defined by mapping in an address of a address space of said processor, wherein a write operation for writing a value to the address of said virtual control register has a certain function in the context of software that can be run on said processor, wherein the real control register is mapped in an address of the address space of said processor such that the address of the real control register differs from the address of said virtual control register and that the real control register provides a function equivalent to the certain function in the hardware of said processor, and wherein, if the operation for writing a value to the address of said virtual control register is executed, a corresponding value is written to the real control register.

In accordance with this configuration, it is possible to provide a processor in which backward compatibility with a previous generation processor is implemented with regard to control register.

In accordance with a tenth aspect of the present invention, a compatible processor is capable of running the software that can be run on a previous generation processor, wherein a bus use request can be issued in said compatible processor for one of a plurality of purposes and granted in accordance with the order of priority among the plurality of purposes, wherein a bus use request can be issued in the previous processor for one of a plurality of purposes and granted in accordance with the order of priority among the plurality of purposes, the plurality of purposes of the previous generation processor is substantially a proper subset of the plurality of purposes of said compatible processor in terms of the bus use requests during execution of the software, and wherein the order of priority within the proper subset of the plurality of purposes of said compatible processor is equivalent to the order of priority among the plurality of purposes of the previous generation processor.

In accordance with this configuration, it is possible to provide a compatible processor in which backward compatibility with a previous generation processor is implemented with regard to bus arbitration.

Brief Description of Drawings

The aforementioned and other features and objects of the present invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of a preferred embodiment taken in conjunction with the accompanying drawings, wherein:

Fig. 1 is a block diagram showing the overall configuration of a current generation processor 100, which is a data processing unit in accordance with an embodiment of the present invention.

Fig. 2A is a view for explaining the 8-bit character number mode implemented in the current generation processor 100 as shown in Fig. 1. Fig. 2B is a view for explaining the 16-bit character number mode implemented in the current generation processor 100 as shown in Fig. 1.

Fig. 2C is a view for explaining the 16-bit aligned address pointer mode implemented in the current generation processor 100 as shown in Fig. 1. Fig. 3A is a view for explaining the 16-bit address pointer mode implemented in the current generation processor 100 as shown in Fig. 1. ^• Fig. 3B is a view for explaining the 24-bit address pointer mode implemented in the current generation processor 100 as shown in Fig. 1. Fig. 4A is a view for explaining the 16-bit extended character number mode implemented in the current generation processor 100 as shown in Fig. 1.

Fig. 4B is a view for explaining the 16-bit extended address pointer mode implemented in the current generation processor 100 as shown in Fig. 1. Fig. 4C is a view for explaining the 24-bit aligned address pointer mode implemented in the current generation processor 100 as shown in Fig. 1.

Fig. 5 is a block diagram showing the overall configuration of a previous generation processor 500, which is a data processing unit in accordance with an embodiment of the present invention.

Fig. 6 is a view for explaining the logical address space of the previous generation processor as illustrated in Fig. 5.

Fig. 7 is a view for explaining the logical address space of the current generation processor of Fig. 1. Fig. 8 is a view for showing an example of a priority level table provided in the first bus arbiter 513 of Fig. 5.

Fig. 9 is a table for showing the list of hardware control registers provided in the first bus arbiter 513 of Fig. 5.

Fig. 10 is a view for showing an example of a priority level table provided in the first bus arbiter 13 of Fig. 1. Fig. 11 is a table for showing the list of hardware control registers provided in the first bus arbiter 13 of Fig. 1.

Fig. 12 is a view for showing an example of a priority level table provided in the second bus arbiter 514 of Fig. 5. Fig. 13 is a table for showing the list of hardware control registers provided in the second bus arbiter 514 of Fig. 5.

Fig. 14 is a view for showing an example of a priority level table provided in the second bus arbiter 14 of Fig. 1.

Fig. 15 is a table for showing the list of hardware control registers provided in the second bus arbiter 14 of Fig. 1.

Fig. 16 is a view for explaining the input and output signals of the first bus arbiter 13 shown in Fig. 1.

Fig. 17 is a block diagram showing the internal configuration of the first bus arbiter 13 of Fig. 16. Fig. 18 is a view for explaining the input and output signals of the second bus arbiter 14 shown in Fig. 1.

Fig. 19 is a view for showing exemplary sizes of data as requested for the respective second bus use request purposes implemented in the current generation processor 100 as shown in Fig. 1. Fig. 20 is a block diagram showing the internal configuration of the second bus arbiter 14 of Fig. 18.

Fig. 21 is a view for explaining the state transition of the state machine 155 shown in Fig. 20.

Fig. 22 is a table for showing the list of hardware control registers provided in the second bus arbiter 514 of Fig. 1, and the hardware control registers are mapped different addresses than those shown in Fig. 15 in the logical address space of the current generation processor 100.

Best Mode for Carrying out The Invention

In what follows, several embodiments of the present invention will be explained in conjunction with the accompanying drawings. Meanwhile, like references indicate the same or functionally similar elements throughout the respective drawings, and therefore redundant explanation is not repeated. Also, when it is necessary to specify a particular bit or bits of a signal in the description or the drawings, [a] or [a:b] is suffixed to the name of the signal. While [a] stands for the a-th bit of the signal, [a:b] stands for the a-th to b-th bits of the signal. In regard to the hexadecimal expression, "H" is suffixed to the number in order to distinguish it from the decimal expression. Also, while a prefixed "Ob" is used to designate a binary number, a prefixed "Ox" is used to designate a hexadecimal number. A single bit signal takes a "1" as an assertion (truth) and a "0" as a negation (false) unless otherwise specified. Fig. 1 is a block diagram showing the overall configuration of a current generation processor 100, which is a data processing unit in accordance with an embodiment of the present invention.

The current generation processor 100 in accordance with the present invention is able to run both the software (which is referred to as compatible software in the following description) that can be run on the previous generation processor 500 and the software (which is referred to as incompatible software in the following description) that cannot be run on the previous generation processor 500. In other words, the current generation processor 100 is designed to maintain software backward compatibility with the previous generation processor 500 at the binary code level, i.e., instruction set backward compatibility. At first, the current generation processor 100 will be briefly explained, and then the previous generation processor 500 will be briefly explained.

As illustrated in Fig. 1, this processor 100 includes a central processing unit (CPU) 1, a graphics processor 3, a pixel plotter 5, a sound processor 7, a DMA (direct memory access) controller 9, a first bus arbiter 13, a second bus arbiter 14, a backup control circuit 15, a main memory 17, a timer circuit 19, an analog-to-digital converter

(ADC) 20, an input/output control circuit 21, an external memory interface circuit 23, a clock driver 29, a PLL (phase-locked loop) circuit 27, a low voltage detection circuit 25, a first bus 31 and a second bus 33.

In the present embodiment, the main memory 17 and the external memories 45, 46 and 47 are generally referred to as the "memory MEMC" in the case where they need not be distinguished. The CPU 1 performs various operations and controls the overall system in accordance with a program stored in the memory MEMC. The CPU 1 is a bus master of the first bus 31 and the second bus 33, and can access the resources connected to the respective buses.

The graphics processor 3 is a bus master of the first bus 31 and the second bus 33, and serves to convert the data stored in the memory MEMC into graphic data, and generate a video signal "VD" to be output to a television receiver (not shown in the figure) on the basis of the graphic data.

In this case, the graphic data is generated by synthesizing a background screen(s), a sprite (s) and a bitmap screen. The background screen which covers entirety of the screen of a television receiver comprises a two-dimensional array. And each array element comprises of a rectangular set of pixels. There are a first background screen and a second background screen prepared respectively as the background screen for showing depths in the background. The sprite consists of a rectangular set of pixels which can be relocated in any position of the screen of a television receiver. The rectangular set of pixels constituting each of the background screens or sprites is referred to as a character. The bitmap screen consists of a two-dimensional pixel array of which the size and location as displayed can be freely designated.

Next is a description of addressing modes in which the graphics processor 3 fetches the pattern data of a character (character pattern data) constituting a sprite from the memory MEMC. Eight types of the addressing modes are provided. Namely, there are an 8-bit character number mode, a 16-bit character number mode, a 16-bit aligned address pointer mode, a 16-bit address pointer mode, a 24-bit address pointer mode, a 16-bit extended character number mode, a 16-bit extended address pointer mode and a 24-bit aligned address pointer mode. In accordance with one of the respective modes, a logical address is converted to a real address as described in the following description

Fig. 2A is a view for explaining the 8-bit character number mode; Fig. 2B is a view for explaining the 16-bit character number mode; and Fig. 2C is a view for explaining the 16-bit aligned address pointer mode.

Fig. 3A is a view for explaining the 16-bit address pointer mode; and Fig. 3B is a view for explaining the 24-bit address pointer mode.

Fig. 4A is a view for explaining the 16-bit extended character number mode; Fig. 4B is a view for explaining the 16-bit extended address pointer mode; and Fig. 4C is a view for explaining the 24-bit aligned address pointer mode.

As shown in Fig. 2A, the 8-bit character number mode is used to select a character by an 8-bit number. As shown in Fig. 2B, the 16-bit character number mode is used to select a character by a 16-bit number. In these modes, a 24-bit base address is generated by aligning the 16-bit segment address stored in the zeroth segment register to the eighth bit position (256 byte alignment) with 8 zeros concatenated as the lower zeroth to 7th bits, and used to calculate real addresses which are spaced from each other by the size of character pattern data indicated by the number "M" of bits of one pixel and the size information "S" of a character. The number "M" of bits of one pixel is information corresponding to a color mode (M bits/pixel) and is an arbitrary value from 1 to 8. The size information "S" is the size of a character constituting a sprite, i.e., indicates what number of pixels the character is composed of. If the horizontal size of a character is "X" pixels and the vertical size is "Y" pixels, the size information S = X x Y. For example, while the horizontal size "X" is 8 pixels or 16 pixels, the vertical size "Y" is 8 pixels or 16 pixels. More specifically speaking, a 27-bit real address is generated by concatenating 3 bits (ObOOO) , as the upper bits, to a 24-bit address which is calculated as (base address) + (the number of a character) x (the number "M" of bits of one pixel.) * (the number of pixels of one character indicated by the size information "S") /8. Incidentally, the division by "8" is performed because the real address is a byte address.

In the 16-bit aligned address pointer mode, a character is selected by a 16-bit aligned address pointer. More specifically speaking, as illustrated in Fig. 2C, a 24-bit base address is generated by selecting one of segment registers (the K-th segment register, K = 0 to 7) in accordance with the upper 3 bits of the 16- bit aligned address pointer, and aligning the 16-bit segment address stored in the selected segment register to the eighth bit position (256 byte alignment) with 8 zeros concatenated as the lower zeroth to 7th bits. Then, a 27-bit real address is generated by concatenating 3 bits (ObOOO) , as the upper bits, to a 24-bit address which is calculated as the sum of this base address and a 16-bit address of the lower 13 bits of the 16-bit aligned address pointer as aligned to the third bit position (8 byte alignment) with 3 bits (ObOOO) concatenated as the zeroth to 2nd bits.

In the 16-bit address pointer mode, a character is selected by a 16-bit address pointer. More specifically speaking, as illustrated in Fig. 3A, a 24-bit base address is generated by selecting one of segment registers (the J-th segment register, J = 0 to 15) pointed to by the upper 4 bits of the 16-bit address pointer, and aligning the 16-bit segment address stored in the selected segment register to the eighth bit position (256 byte alignment) with 8 zeros concatenated as the lower zeroth to 7th bits. Then, a 27-bit real address is generated by concatenating 3 bits (ObOOO) , as the upper bits, to a 24-bit address which is calculated as the sum of this base address and the lower 12 bits of the 16-bit address pointer.

In the 24-bit address pointer mode, a character is selected by a 24-bit address pointer. More specifically speaking, as illustrated in Fig. 3B, a 27-bit real address (address pointer) is generated by concatenating 3 bits (ObOOO) , as the upper bits, to the 24-bit address pointer.

The 16-bit extended character number mode is an extended mode of the 16-bit character number mode. In this mode, as illustrated in Fig. 4A, a 27-bit base address is generated by aligning the 16-bit segment address stored in the zeroth segment register to the eleventh bit position (2K byte alignment) with 11 zeros concatenated as the lower zeroth to 10th bits, and used to calculate a real addresses which are spaced from each other by the size of character pattern data indicated by the number "M" of bits of one pixel and the size information "S". The actual implementation of this calculation is the same as that used in the 16-bit character number mode.

More specifically speaking, a 27-bit real address (address pointer) is calculated as (base address) + (character number) x (the number "M" of bits of one pixel) * (the number of the pixels of one character indicated by the size information "S") /8.

The 16-bit extended address pointer mode is an extended mode of the 16-bit address pointer mode. More specifically, as illustrated in Fig. 4B, a 27-bit base address is generated by selecting one of segment registers (the J-th segment register, J = 0 to 15) pointed to by the upper 4 bits of the 16-bit address pointer, and aligning the 16-bit segment address stored in the selected segment register to the eleventh bit position (2K byte alignment) with 11 zeros concatenated as the lower zeroth to 10th bits. A 27-bit real address (address pointer) is calculated as the sum of this base address and the lower 12 bits of the 16-bit address pointer.

In the 24-bit aligned address pointer mode, as illustrated in Fig. 4C, a 27-bit real address is generated by concatenating 3 bits (ObOOO) as the lower bits to the 24-bit address pointer as the upper 24 bits (8 byte alignment) . Even if the lower 3 bits are "0", there is no problem because the size of the smallest character pattern data is 8 bytes while any larger character pattern data has a size of an integer multiple of 8 bytes. By this system, it is possible to access a larger address space by a shorter address pointer.

Returning to Fig. 1, the graphics processor 3 is controlled by the CPU 1 through the first bus 31, and capable of issuing an interrupt request signal "INRQ" to the CPU 1.

The pixel plotter 5 is controlled by the CPU 1 through the first bus 31, and capable of drawing pixel data as given from the CPU 1. In this example, the drawing operation can be performed with individual pixels. Pixel data is data representing the display color of one pixel by M bits (M is one or a larger integer) . In the present embodiment, M = 1 to 8 as an example.

Also, the pixel plotter 5 makes it possible to perform high¬ speed drawing and effectively use the buses (the first bus 31 and the second bus 33) by virtue of a cache system. Furthermore, the pixel plotter 5 is a bus master of the first bus 31 and the second bus 33, and capable of autonomously writing data from a cache (not shown in the figure) to the memory MEMC and from the memory MEMC to the cache.

The sound processor 7 is a bus master of the first bus 31 and the second bus 33, and serves to convert data stored in the memory MEMC into sound data, and generate and output an audio signal "AU" on the basis of the sound data.

The sound data is synthesized by pitch conversion and amplitude modulation of PCM (pulse code modulation) data serving as the base data of tone quality. For the amplitude modulation, a function for reproducing waveforms of a music instrument is provided in addition to the volume control function performed in response to an instruction of the CPU 1.

Furthermore, the sound processor 7 is controlled by the CPU 1 through the first bus 31, and capable of issuing an interrupt request signal "INRQ" to the CPU 1.

The DMA controller 9 controls data transfers from the external memories 45, 46 and 47 connected to an external bus 43 to the main memory 17. Each of the external memories 45, 46 or 47 may be implemented with, for example, an SRAM (static random access memory) , a DRAM (dynamic random access memory) , a ROM (read only memory) or any other appropriate memory, or implemented as a combination of any number of such memories. On the other hand, the DMA controller 9 has the function of outputting, to the CPU 1, an interrupt request signal "INRQ" indicative of the completion of the data transfer. Particularly, the DMA controller 9 is a bus master of the first bus 31 and the second bus 33, and controlled by the CPU 1 through the first bus 31.

The main memory 17 may be implemented with one or any necessary combination of a mask ROM, an SRAM and a DRAM in accordance with the system requirements. In the present embodiment, the main memory 17 is composed of an SRAM.

The backup control circuit 15 deactivates the main memory 17 when the low voltage detection circuit 25 to be described below detects a low voltage condition. On the other hand, the main memory 17 is supplied with a power supply voltage from the battery 41. Accordingly, the data stored in the main memory 17 composed of an SRAM can be maintained even after the power supply voltages VccO and Vccl are taken away.

The first bus arbiter 13 accepts first bus use request signals from the respective bus masters of the first bus 31, performs bus arbitration among the requests, and issues a first bus use acknowledge signal to one of the respective bus masters for each bus cycle. More specifically speaking, while there are multiple sets of priority level information relating to the priority levels (priority rankings) assigned to a plurality of the bus masters in regard to the use of the first bus 31, the first bus arbiter 13 performs arbitration on the basis of one of the multiple sets of priority level information which is sequentially and cyclically selected. This will be described below in detail. Each bus master is permitted to access the first bus 31 after receiving the first bus use acknowledge signal. In this example, the first bus use request signal and the first bus use acknowledge signal are illustrated as first bus arbitration signals "FAB" in Fig. 1.

For example, the first bus 31 includes a data bus 312 (to be described below) of 8 bits, an address bus 311 (to be described below) of 15 bits and a control bus 313 (to be described below) .

The second bus arbiter 14 accepts second bus use request signals from the respective bus masters of the second bus 33, performs bus arbitration among the requests, and issues a second bus use acknowledge signal to one of the respective bus masters for each bus cycle or each sequence of a predetermined number of bus cycles corresponding to the number of bytes as required. More specifically speaking, while there are multiple sets of priority level information relating to the priority levels assigned to a plurality of the bus masters in regard to the use of the second bus 33, the second bus arbiter 14 performs arbitration on the basis of one of the multiple sets of priority level information which is sequentially and cyclically selected. This will be described below in detail.

Each bus master is permitted to access the second bus 33 after receiving the second bus use acknowledge signal. In this example, the second bus use request signal and the second bus use acknowledge signal are illustrated as second bus arbitration signals "SAB" in Fig.

1.

For example, the second bus 33 includes a data bus of 16 bits, an address bus of 27 bits and a control bus (not shown in the figure) .

The timer circuit 19 has the function of repeatedly outputting an interrupt request signal "INRQ" to the CPU 1 with a configured interval. The setting of the time interval and so forth is performed by the CPU 1 through the first bus 31. The ADC 20 converts an analog input signal to a digital signal. This digital signal is read by the CPU 1 through the first bus 31. In addition, the ADC 20 has the function of outputting an interrupt request signal "INRQ" to the CPU 1. Incidentally, an analog signal as output from an external device is input to the ADC 20, for example, through any one of six analog ports "AINO" to "AIN5" (not shown in the figure) .

The input/output control circuit 21 serves to perform the input and output operations of input and output signals to enable the communication with external input/output devices and/or external semiconductor devices . The read and write operations of input and output signals are controlled by the CPU 1 through the first bus 31. Also, the input/output control circuit 21 has the function of outputting an interrupt request signal "INRQ" to the CPU 1. Incidentally, the input and output signals are input and output, for example, through programmable input/output ports ¹¹IOO" to "1023" (not shown in the figure) .

The low voltage detection circuit 25 monitors the power supply- voltages VccO and Vccl, and issues a reset signal to the PLL circuit 27 and so forth and a reset signal "RSET" to the other circuit elements of the entire system when either the power supply voltage VccO or Vccl falls below corresponding one of reference voltages which are determined in advance individually for the respective power supply- voltages VccO and Vccl.

In this case, the power supply voltage VccO is for example + 2.5 V, which is supplied mainly to digital circuits in the processor 100. On the other hand, the power supply voltage Vccl is for example + 3.3 V, which is supplied mainly to analog circuits and I/O circuits in the processor 100.

The PLL circuit 27 generates a high frequency clock signal by multiplication of the sinusoidal signal as obtained from a crystal oscillator 37.

The clock driver 29 reinforces the high frequency clock signal as received from the PLL circuit 27 to a sufficient driving capability to supply the respective blocks with the amplified high frequency clock signal as an internal clock signal "ICLK".

The external memory interface circuit 23 has the function of connecting the second bus 33 to the external bus 43.

Next, the data transfer paths within the processor 100 shown in Fig. 1 will be explained. For example, in the case where the CPU 1 controls, as a bus master, one of the other functional blocks (the graphics processor 3, the pixel plotter -5, the sound processor 7, the DMA controller 9, the first bus arbiter 13, the second bus arbiter 14 and the like) respectively connected to the first bus 31 as a bus slave, the CPU 1 outputs write data to the first bus arbiter 13 for writing the write data to the control register of the functional block and, after arbitration, the first bus arbiter 13 transmits the write data to the control register through the first bus 31. On the other hand, the CPU 1 outputs a first bus use request signal to the first bus arbiter 13 for reading data from the functional block and, after arbitration, receives read data transmitted from the control register through the first bus 31 and the first bus arbiter 13. On the other hand, each of the graphics processor 3, the pixel plotter 5, the sound processor 7 and the DMA controller 9 has the function of outputting the first bus use request signal to the first bus arbiter 13 as a bus master of the first bus 31.

When accessing the main memory 17, a bus master outputs write data to the first bus arbiter 13 for writing the write data to the main memory 17 and the first bus arbiter 13 transmits the write data to the main memory 17 after arbitration through the first bus 31. On the other hand, a bus master outputs a first bus use request signal to the first bus arbiter 13 for reading data from the main memory 17 and receives the read data from the main memory 17 after arbitration through the first bus 31 and the first bus arbiter 13. Also, when accessing one of the external memories 45 to 47, a bus master outputs write data to the second bus arbiter 14 for writing the write data to the external memory and the second bus arbiter 14 transmits the write data to the external memory after arbitration through the second bus 33, the external memory interface circuit 23 and the external bus 43. On the other hand, a bus master outputs a second bus use request signal to the second bus arbiter 14 for reading data from one of the external memories 45 to 47 and receives the read data from the external memory after arbitration through the external bus 43, the external memory interface circuit 23, the second bus 33 and the second bus arbiter 14. Refering to Fig. 5, this processor 500 includes a central processing unit (CPU) 501, a graphics processor 503, a sound processor 507, a DMA controller 509, a first bus arbiter 513, a second bus arbiter 514, a main memory 517, a timer circuit 519, an analog-to- digital converter (ADC) 520, an input/output control circuit 521, an external memory interface circuit 523, a clock driver 529, a PLL (phase-locked loop) circuit 527, a low voltage detection circuit 525, a first bus 531, a second bus 533 and a DRAM refresh control circuit 522.

In the present embodiment, the main memory 517 and the external memory 545, 546 and 547 are generally referred to as the "memory MEMP" in the case where they need not be distinguished.

The CPU 501 performs various operations and controls the overall system in accordance with a program stored in the memory MEMP. The CPU 501 is a bus master of the first bus 531 and the second bus 533, and can access the resources connected to the respective buses.

The graphics processor 503 is a bus master of the first bus 531 and the second bus 533, and serves to convert the data stored in the memory MEMP into graphic data, and generate a video signal "VD" to be output to a television receiver (not shown in the figure) on the basis of the graphic data.

In this case, the graphic data is generated by synthesizing a background screen(s), and a sprite(s) . There are a first background screen and a second background screen prepared respectively as the background screen, in the same manner as the background screen of the current generation processor 100.

Next is a description of addressing modes in which the graphics processor 503 fetches the pattern data of a character (character pattern data) constituting a sprite from the memory MEMP. Five types of the addressing modes are provided. Namely, there are an 8-bit character number mode, a 16-bit character number mode, a 16-bit aligned address pointer mode, a 16-bit address pointer mode and a 24- bit address pointer mode. These modes are provided corresponding respectively to the 8-bit character number mode, the 16-bit character number mode, the 16-bit aligned address pointer mode, the 16-bit address pointer mode and the 24-bit address pointer mode of the current generation processor 100. However, a real address (address pointer) is finally generated as a 24-bit address (pointer) . This is because the logical address space is smaller than that of the current generation processor 100. Accordingly, unlike the current generation processor 100, the upper 3 bytes (ObOOO) are not concatenated.

Also, the graphics processor 503 is controlled by the CPU 501 through the first bus 531, and capable of issuing an interrupt request signal "INRQ" to the CPU 501.

The sound processor 507 is a bus master of the first bus 531 and the second bus 533, and serves to convert data stored in the memory MEMP into sound data, and generate and output an audio signal "AU" on the basis of the sound data.

Furthermore, the sound processor 507 is controlled by the CPU 501 through the first bus 531, and capable of issuing an interrupt request signal "INRQ" to the CPU 501.

The DMA controller 509 controls data transfer from the external memories 545 to 547 connected to the external bus 543 to the main memory 517. The external memories 545 to 547 may be implemented with any appropriate type of memories or implemented as a combination of any number of such memories, in the same manner as the external memories 45 to 47. On the other hand, the DMA controller 509 has the function of outputting, to the CPU 501, an interrupt request signal "INRQ" indicative of the completion of the data transfer. Particularly, the DMA controller 509 is a bus master of the first bus 531 and the second bus 533, and controlled by the CPU 1 through the first bus 531.

The main memory 517 may be implemented with one or any necessary combination of a mask ROM, an SRAM and a DRAM in accordance with the system requirements.

The first bus arbiter 513 accepts first bus use request signals from the respective bus masters of the first bus 531, performs bus arbitration among the requests, and issues a first bus use acknowledge signal to one of the respective bus masters for every bus cycle. More specifically speaking, while there are multiple sets of priority level information relating to the priority levels (priority rankings) assigned to a plurality of the bus masters in regard to the use of the first bus 531, the first bus arbiter 513 performs arbitration on the basis of one of the multiple sets of priority level information which is sequentially and cyclically selected.

Each bus master is permitted to access the first bus 531 after receiving the first bus use acknowledge signal. In this example, the first bus use request signal and the first bus use acknowledge signal are illustrated as first bus arbitration signals "FAB" in Fig. 5.

For example, the first bus 531 includes a data bus of 8 bits, an address bus of 15 bits and a control bus (not shown in the figure) . The second bus arbiter 514 accepts second bus use request signals from the respective bus masters of the second bus 533, performs bus arbitration among the requests, and issues a second bus use acknowledge signal to one of the respective bus masters for every bus cycle. More specifically speaking, while there are multiple sets of priority level information relating to the priority levels assigned to a plurality of the bus masters in regard to the use of the second bus 533, the second bus arbiter 514 performs arbitration on the basis of one of the multiple sets of priority level information which is sequentially and cyclically selected. Each bus master is permitted to access the second bus 533 after

• receiving the second bus use acknowledge signal. In this example, the second bus use request signal and the second bus use acknowledge signal are illustrated as second bus arbitration signals "SAB" in Fig.

5. For example, the second bus 533 includes a data bus of 8 bits, an address bus of 24 bits and a control bus (not shown in the figure) .

The timer circuit 519 has the function of repeatedly outputting an interrupt request signal "INRQ" to the CPU 501 with a configured interval. The setting of the time interval and so forth is performed by the CPU 501 through the first bus 531.

The ADC 520 converts an analog input signal to a digital signal. This digital signal is read by the CPU 501 through the first bus 531. In addition, the ADC 520 has the function of outputting an interrupt request signal "INRQ" to the CPU 501. Incidentally, an analog signal as output from an external device is input to the ADC 520, for example, through any one of six analog ports "AINO" to "AIN5" (not shown in the figure) .

The input/output control circuit 521 serves to perform the input and output operations of input and output signals to enable the communication with external input/output devices and/or external semiconductor devices. The read and write operations of input and output signals are controlled by the CPU 501 through the first bus 531. Also, the input/output control circuit 521 has the function of outputting an interrupt request signal "INRQ" to the CPU 501. Incidentally, the input and output signals are input and output, for example, through a programmable input/output port "IOO" to 1015.

The low voltage detection circuit 525 monitors the power supply voltage Vcc, and issues a reset signal to the PLL circuit 527 and a reset signal "RSET" to the other circuit elements of the entire system when the power supply voltage VccO falls below a predetermined voltage. On the other hand, in the case where the main memory 517 is implemented with an SRAM requiring the power supply from the battery 541 for maintaining data, the low voltage detection circuit 525 serves to issue a battery backup control signal "BCTL" when the power potential Vcc falls below the predetermined voltage.

The PLL circuit 527 generates a high frequency clock signal by multiplication of the sinusoidal signal as obtained from a crystal oscillator 537.

The clock driver 529 reinforces the high frequency clock signal as received from the PLL circuit 527 to a sufficient driving capability to supply the respective blocks with the amplified high frequency clock signal as an internal clock signal "ICLK".

The external memory interface circuit 523 has a function of connecting the second bus 533 to the external bus 543, and controls the bus cycle length of the second bus 533 by issuing a bus cycle completion signal "CYL" .

The DRAM refresh cycle control circuit 522 periodically and unconditionally gets the ownership of the first bus 531 to perform the refresh cycle of the DRAM at a certain interval. Needless to say, the DRAM refresh cycle control circuit 522 is provided in the case where the main memory 517 includes a DRAM.

Incidentally, the previous generation processor 500 is provided with no element corresponding to the pixel plotter 5 of the current generation processor 100. Next, the logical address space of the previous generation processor 500 will be explained, and thereafter the logical address space of the current generation processor 100 will be explained.

The previous generation processor 500 is able to output an address signal of 24 bits, i.e., has a logical address space of 16 MB. The first bus 531 is accessed by an address of 15 bits, i.e., has a physical address space of 32 KB. The second bus 533 has a physical address space of 12 MB corresponding to an address space of 24 bits a part of which is excluded therefrom. These points will be explained with reference to the drawings. Fig. 6 is a view for explaining the logical address space of the previous generation processor 500 as illustrated in Fig. 5. As shown in Fig. 6, the 24 bits of the address are mainly divided into the upper 8 bits and the lower 16 bits, wherein the upper 8 bits serves to form a bank address. Namely, the logical address space of 16 MB is divided into 256 unit spaces (data blocks) each of which has a size of 64 KB and is called a bank, so that, for example, the address "FFFFh" of the "0Oh" bank and the address "000Oh" of the "01h" bank cannot be continuously accessed by the CPU 501 and the sound processor 507. For this reason, the respective banks are illustrated in parallel in Fig. 6 for the purpose of visualizing this fact.

The logical address space of the processor 500 is mainly divided into four areas, i.e., a first bus area corresponding to the physical address space of the first bus 531, and the second bus zeroth area, the second bus first area, the second bus second area respectively corresponding to the physical address space of the second bus 533.

The second bus zeroth area is assigned to the external memory 545, the second bus first area is assigned to the external memory 546, and the second bus second area is assigned to the external memory 547. The external memory interface circuit 523 asserts the zeroth area select signal "ASSELO" when the second bus address provided on the second bus 533 points to the second bus zeroth area, asserts the first area select signal "ASSELl" when the second bus address points to the second bus first area, and asserts the second area select signal "ASSEL2" when the second bus address points to the second bus second area. Then, when the zeroth area select signal "ASSELO" is asserted, the external memory 545 is activated; when the first area select signal "ASSELl" is asserted, the external memory 546 is activated; and when the second area select signal "ASSEL2" is asserted, the external memory 547 is activated. On the other hand, the current generation processor 100 is able to output an address signal of 27 bits, i.e., has a logical address space of 128 MB. The first bus 31 serves to transmit a 15-bit address, i.e., has a physical address space of 32 KB. The second bus 33 has a physical address space of 96 MB corresponding to a 27-bit address space a part of which is excluded therefrom. This point will be explained with reference to a drawing.

Fig. 7 is a view for explaining the logical address space of the current generation processor 100 of Fig. 1. As shown in Fig. 7, the 27 bits of the address are mainly divided into the upper 11 bits and the lower 16 bits, wherein the upper 11 bits serves to form a bank address. Namely, the logical address space of 128 MB is divided into 2048 unit spaces (data blocks) each of which has a size of 64 KB and is called a bank, so that, for example, the address "FFFFh" of the "000h" bank and the address "000Oh" of the "001h" bank cannot be continuously accessed by the CPU 1 and the sound processor 7. For this reason, the respective banks are illustrated in parallel in Fig. 7 for the purpose of visualizing this fact.

The logical address space of the processor 100 is mainly divided into four areas, i.e., a first bus area corresponding to the physical address space of the first bus 31, and the second bus zeroth area, the second bus first area, the second bus second area respectively corresponding to the physical address space of the second bus 33.

The second bus zeroth area is assigned to the. external memory 45, the second bus first area to the external memory 46, and the second bus second area to the external memory 47.

The second bus arbiter 14 asserts the first area select signal "ASSELl" when the second bus address provided on the second bus 33 points to the second bus first area, and asserts the second area select signal "ASSEL2" when the second bus address points to the second bus second area.

Then, when the first area select signal "ASSELl" is asserted, the external memory 46 is activated; and when the second area select signal "ASSEL2" is asserted, the external memory 47 is activated.

The second bus address [22] is substituted for the zeroth area aelect signal "ASSELO" such that the external memory 45 is activated when the second bus address [22] is "0".

As illustrated in Fig. 6 and Fig. 7, the logical address space of the current generation processor 100 as addressed by 27-bit addresses is designed in order that the mapping of the subspace thereof with "ObOOO" assigned to the upper 3 bits is equivalent to the mapping of the 24-bit logical address space of the previous generation processor 500. Accordingly, the software that can be run on the previous generation processor 500 (i.e., compatible software) can be run also on the current generation processor 100 in the same manner. In other words, software compatibility can be maintained at the binary code level .

In the current generation processor 100, mapping compatibility can be maintained by fixing the extended upper 3 bits of the address signal to "ObOOO" in regard to the operations of the CPU 1, the sound processor 7 and the DMA controller 9, of the bus masters whose counterparts exist in the previous generation processor 500.

On the other hand, since three types of the addressing modes (the 16-bit extended character number mode, the 16-bit extended address pointer mode and the 24-bit aligned address pointer mode) are implemented in the graphics processor 3 of the current generation processor 100 in addition to the five types of the addressing modes of the graphics processor 503 of the previous generation processor 500, the full 27-bit addressing is possible in fetching character pattern data of the sprites and the background screens only in the additional addressing modes. On the contrary, the pixel plotter 5 introduced in the current generation processor 100 as a new bus master as seen from the previous generation processor 500 is able to fully access the 27- bit address space.

Next, the details of arbitration performed by the first bus arbiter 513 of the previous generation processor 500 will be explained, and then the details of arbitration performed by the first bus arbiter 13 of the current generation processor 100 will be explained.

Fig. 8 is a view for showing an example of a priority level table provided in the first bus arbiter 513 of Fig. 5. As shown in Fig. 8, while four sets of priority level information are prepared for accessing the first bus 531, each set is encoded respectively into one of priority level information numbers 0 to 3 of two bits. In Fig. 8, the priority level table provides an example of how to convert each of the priority level information numbers 0 to 3 into the corresponding priority level information set. One set of priority level information consists of the first priority level to the fourth priority level. The priority levels of accessing the first bus 531 include the first priority level which is the highest priority level while the priority decreases as the number of the priority level increases. The first bus arbiter 513 sequentially and cyclically selects one of 16 priority level registers each of which stores one of the priority level information numbers 0 to 3. Then, the first bus arbiter 513 grants the ownership of the first bus 531 to the bus master having the highest priority by selecting the bus master having the highest priority from among the bus masters issuing requests for access to the first bus 531, except for the bus master that is currently using the first bus 531, on the basis of the priority level information set corresponding to the priority level information number stored in the priority level register as selected. However, the DRAM refresh cycle control circuit 522 which is a privilege bus master is excluded from the arbitration and always selected first when it requests to use the first bus.

Fig. 9 is a table for showing the list of hardware control registers provided in the first bus arbiter 513 of Fig. 2, and the hardware control registers are mapped in the address space of the first bus of the previous generation processor 500. As shown in Fig. 9, the first bus arbiter 513 is provided with a zeroth slot priority- level register to the 15th slot priority level register. Each register is used to store a priority level information number of Fig. 7 as encoded. The CPU 1 can change the priority level information number stored in a register by accessing the register. Incidentally, in the physical address space of the first bus 531 of the previous generation processor 500, each of these registers is located in the corresponding first bus address as illustrated in the figure.

Fig. 10 is a view for showing an example of a priority level table provided in the first bus arbiter 13 of Fig. 1. As shown in Fig. 10, while four sets of priority level information are prepared for accessing the first bus 31, each set is encoded respectively into one of priority level information numbers 0 to 3 of two bits. In Fig. 10, the priority level table provides an example of how to convert each of the priority level information numbers 0 to 3 into a corresponding priority level information set.

In this case, each of the bus masters (the CPU 1, the graphics processor 3, the pixel plotter 5, the sound processor 7 and the DMA controller 9) outputs a bus use request corresponding to each purpose of using the first bus 31 (referred to as a "first bus use request purpose" in the following description) . Accordingly, each of the priority level information sets designated by one of the priority- level information numbers 0 to 3 indicates the priority levels of all the first bus use request purposes. Since there are 12 kinds of the first bus use request purposes in the case of the present embodiment, each of the priority level information sets designates the first priority level to the 12th priority level. The priority levels of accessing the first bus 31 include the first priority level which is the highest priority level while the priority decreases as the number of the priority level increases. The first bus arbiter 13 sequentially and cyclically selects one of 16 priority level registers each of which stores one of the priority level information numbers 0 to 3, and performs the arbitration of requests for access to the first bus 31 on the basis of the priority level information set corresponding to the priority level information number stored in the priority level register as selected. In this case, the first bus arbiter 13 performs the access arbitration for the respective first bus use request purposes.

In this example as illustrated in the figure, the abbreviations of the bus masters, i.e., "CPU", "GP", "SP", "DMA" and "PLT" stand respectively for the CPU 1, the graphics processor 3, the sound processor 7, the DMA controller 9 and the pixel plotter 5.

Also, the abbreviations of the first bus use request purposes in the figure, i.e., "1ST", "DAT", "TXl", "TX2", "SPR", "HDR", "CHR", "BMP", "WAV", "ENV", "DMAD" and "PLT" stand respectively for "instruction fetch", "data access", "first background array data", "second background array data", "sprite DMA", "character header", "character data", "bitmap data", "wave data", "envelope data", "DMA destination" and "pixel plotter". The respective first bus use request purposes have the following means.

The "instruction fetch" corresponds to the first bus use request purpose for which the CPU 1 fetches an instruction from the main memory 17.

The "data access" corresponds to the first bus use request purpose for which the CPU 1 accesses (for reading or writing data) the resources connected to the first bus 31.

The "first background array data" corresponds to the first bus use request purpose for which the graphics processor 3 acquires the array data of the first background screen from the main memory 17. The array data of this example contains the address information of the character pattern data of all characters in the first background screen, and may include color palette information and depth information.

The "second background array data" corresponds to the first bus use request purpose for which the graphics processor 3 acquires the array data of the second background screen from the main memory 17. The array data of this example contains the address information of the character pattern data of all characters in the second background screen, and may include color palette information and depth information. The "sprite DMA" corresponds to the first bus use request purpose for which the graphics processor 3 reads from the main memory 17 the data to be transferred to a sprite memory (not shown in the figure, but located in the graphics processor 3) . The "character header" corresponds to the first bus use request purpose for which the graphics processor 3 acquires a character header from the main memory 17. The character header consists of color palette information, information about the number of bits per pixel (N bits/pixel) of the character, flip information and so forth. The "character data" corresponds to the first bus use request purpose for which the graphics processor 3 acquires character pattern data from the main memory 17.

The "bitmap data" corresponds to the first bus use request purpose for which the graphics processor 3 reads bitmap data from the main memory 17.

The "wave data" corresponds to the first bus use request purpose for which the sound processor 7 acquires wave data from the main memory 17.

The "envelope data" corresponds to the first bus use request purpose for which the sound processor 7 acquires envelope data from the main memory 17 and writes, to the main memory 17, the read pointer to an FIFO (first-in first-out) buffer for envelope data which is virtually provided in the main memory 17.

The "DMA destination" corresponds to the first bus use request purpose for which the DMA controller 9 writes data to the main memory 17.

The "pixel plotter" corresponds to the first bus use request purpose for which the pixel plotter 5 performs read or write operations from/to the main memory 17. Next, the method of preparing the priority level table shown in Fig. 10 will be explained. The permutations (referred to as the bus use request purpose permutations) of the bus use request purposes are provided for each bus master, and then one bus use request purpose permutation for each bus master is selected taking into consideration the amounts of data transmitted to/from each bus use request purpose and the frequencies of using the bus by each bus use request purpose.

Then, the priority level table for use in the first bus arbiter 13 of the current generation processor 100 as shown in Fig. 10 is created by combining the bus use request purpose permutations as selected for the respective bus masters with the priority levels in the priority level table- for use in the first bus arbiter 513 of the previous generation processor 500 as shown in Fig. 8. This will be explained in accordance with a specific example.

In the case of the priority level information number 0 of Fig. 8 as an example, the priority levels are assigned as {SP, GP, DMA, CPU}. This is referred to as a bus master permutation in the following description. On the other hand, also by the use of the abbreviations shown in Fig. 10, the bus use request purpose permutation as selected of the sound processor 7 is {WAV, ENV}; the bus use request purpose permutation as selected of the graphics processor 3 is {BMP, CHR, HDR, SPR, TXl, TX2}; the bus use request purpose permutation as selected of the pixel plotter 5 is {PLT} (this is because there is only one bus use request purpose for accessing the first bus 31 by the pixel plotter 5) ; the bus use request purpose permutation as selected of the DMA controller 9 is {DMAD} (for the same reason as that of the pixel plotter 5) ; and the bus use request purpose permutation as selected of the CPU 1 is {DAT, 1ST}.

In this case, in correspondence with the priority level information number 0 of the previous generation processor 500 as illustrated in Fig. 8, the bus use request purpose permutation (priority level information number 0) for use in the first bus arbiter

13 of the current generation processor 100 as illustrated in Fig. 10 is obtained by substituting the bus use request purpose permutation

{WAV, ENV} for SP, the bus use request purpose permutation {BMP, CHR, HDR, SPR, TXl, TX2} for GP, the bus use request purpose permutation {DMAD} for DMA, and the bus use request purpose permutation {DAT, 1ST} for CPU, and additionally inserting the bus use request purpose permutation {PLT} into any appropriate position. This insertion of the bus use request purpose permutation {PLT} shall not disturb the order relation among the other bus masters. As a result, a priority level information set is prepared corresponding to the priority level information number 0 as illustrated in Fig. 10. Also, priority level information sets corresponding to the priority level information numbers 1 to 3 of Fig. 10 are prepared on the basis of the priority level information sets corresponding to the priority level information numbers 1 to 3 of Fig. 8.

As has been discussed above, while the number of bus access requests corresponding to purposes of using the first bus is significantly increased in the current generation processor 100 as compared with that in the previous generation processor 500, it is possible to maintain the software compatibility since the priority levels of each priority level information set in the current generation processor 100 as shown in Fig. 10 are determined on the basis of the priority level table in the previous generation processor 500 as shown in Fig. 8.

On the other hand, the pixel plotter 5 which is not implemented in the previous generation processor 500 is a bus master responsible for image processing and rarely accesses the first bus 31, and therefore the bus use request purpose of the pixel plotter 5 is positioned next to the bus use request purposes of the graphics processor 3 in priority level. Incidentally, even if the pixel plotter 5 is included in the priority level information set of the first bus 31 of the current generation processor 100, the compatibility shall not be affected thereby because the previous generation processor 500 has no a pixel plotter and the software provided for the previous generation processor 500 is run without the use of a pixel plotter.

Fig. 11 is a table for showing the list of hardware control registers provided in the first bus arbiter 13 of Fig. 1 and the hardware control registers are mapped in the address space of the first bus of the current generation processor 100. As shown in Fig. 11, the first bus arbiter 13 is provided with a zeroth slot priority level register to the 15th slot priority level register. Each register is used to store a priority level information number of Fig. 10 as encoded. The CPU 1 can change the priority level information number stored in a register by accessing the register. Incidentally, in the physical address space of the first bus 31 of the current generation processor 100, each of these registers is located in the corresponding first bus address as illustrated in the figure.

As is apparent from Fig. 9 and Fig. 11, the current generation first bus arbiter 31 and the previous generation first bus arbiter 531 have the same constituent members of the control registers and the same addresses given to the respective control registers.

Next, the details of arbitration performed by the second bus arbiter 514 of the previous generation processor 500 will be explained, and then the details of arbitration performed by the second bus arbiter 14 of the current generation processor 100 will be explained.

Fig. 12 is a view for showing an example of a priority level table provided in the second bus arbiter 514 of Fig. 2. As shown in Fig. 12, while four sets of priority level information are prepared for accessing the second bus 533, each set is encoded respectively into one of priority level information numbers 0 to 3 of two bits. In Fig. 12, the priority level table provides an example of how to convert each of the priority level information numbers 0 to 3 into a corresponding priority level information set. One set of priority level information consists of the first priority level to the fourth priority level. The priority levels of accessing the second bus 533 include the first priority level which is the highest priority level while the priority decreases as the number of the priority level increases. The second bus arbiter 514 sequentially and cyclically selects one of 8 priority level registers each of which stores one of the priority level information numbers 0 to 3. Then, the second bus arbiter 514 grants the ownership of the second bus 533 to the bus master having the highest priority by selecting the bus master having the highest priority from among the bus masters issuing requests for access to the second bus 533, except for the bus master that is currently using the second bus 533, on the basis of the priority level information set corresponding to the priority level information number stored in the priority level register as selected.

Fig. 13 is a table for showing the list of hardware control registers provided in the second bus arbiter 514 of Fig. 2 and the hardware control registers are mapped in the address space of the first bus of the previous generation processor 500. As shown in Fig. 13, the second bus arbiter 514 is provided with a zeroth slot priority level register to the seventh slot priority level register. Each register is used to store a priority level information number of Fig. 12 as encoded. The CPU 501 can change the priority level information number stored in a register by accessing the register. Incidentally, in the physical address space of the first bus 531 of the previous generation processor 500, each of these registers is located in the corresponding first bus address illustrated in the figure.

Fig. 14 is a view for showing an example of a priority level table containing a plurality of priority level information sets for use in the second bus arbiter 14 of Fig. 1. As shown in Fig. 14, while four sets of priority level information are prepared for accessing the second bus 33, each set is encoded respectively into one of priority level information numbers 0 to 3 of two bits. In Fig. 14, the priority level table provides an example of how to convert each of the priority level information numbers 0 to 3 into a corresponding priority level information set. In this case, each of the bus masters (the CPU 1, the graphics processor 3, the pixel plotter 5, the sound processor 7 and the DMA controller 9) outputs a bus use request corresponding to each purpose of using the second bus 33 (referred to as a "second bus use request purpose" in the following description) . Accordingly, each of the priority level information sets designated by one of the priority level information numbers 0 to 3 indicates the priority levels of all the second bus use request purposes. Since there are 9 kinds of the second bus use request purpose in the case of the present embodiment, each of the priority level information sets designates the first priority level to the ninth priority level. The priority levels of accessing the second bus 33 include the first priority level which is the highest priority level while the priority decreases as the number of the priority level increases. The second bus arbiter 14 sequentially and cyclically selects one of 8 priority level registers each of which stores one of the priority level information numbers 0 to 3, and performs the arbitration of requests for access to the second bus 33 on the basis of the priority level information set corresponding to the priority level information number stored in the priority level register as selected. In this case, the second bus arbiter 14 performs the access arbitration for the respective second bus use request purposes.

In this example as illustrated in this figure, the bus masters and the second bus use request purposes are given the same abbreviations as in Fig. 10. However, the abbreviation "DMAS" of the second bus use request purpose stands for "DMA source" while the respective second bus use request purposes have the following means.

The "Instruction fetch" corresponds to the second bus use request purpose for which the CPU 1 fetches instructions from the external memories 45 to 47. The "data access" corresponds to the second bus use request purpose for which the CPU 1 accesses (for reading or writing data) the external memories 45 to 47.

The "character header" corresponds to the second bus use request purpose for which the graphics processor 3 acquires a character header from the external memories 45 to 47.

The "character data" corresponds to the second bus use request purpose for which the graphics processor 3 acquires character pattern data from the external memories 45 to 47.

The "bitmap data" corresponds to the second bus use request purpose for which the graphics processor 3 reads bitmap data from the external memories 45 to 47.

The "pixel plotter" corresponds to the second bus use request purpose for which the pixel plotter 5 performs read or write operations from/to the external memories 45 to 47. The "wave data" corresponds to the second bus use request purpose for which the sound processor 7 acquires wave data from the external memories 45 to 47.

The "envelope data" corresponds to the second bus use request purpose for which the sound processor 7 acquires envelope data from the external memories 45 to 47.

The "DMA source" corresponds to the second bus use request purpose for which the DMA controller 9 reads data from the external memories 45 to 47.

Next, the method of preparing the priority level table shown in Fig. 14 will be explained. The permutations (referred to as the bus use request purpose permutations) of the bus use request purposes are provided for each bus master, and then one bus use request purpose permutation is selected taking into consideration .the amounts of data transmitted to/from each bus use request purpose and the frequencies of using the bus by each bus use request purpose.

Then, the priority level table for use in the second bus arbiter 14 of the current generation processor 100 as shown in Fig. 14 is created by combining the bus use request purpose permutations as selected for the respective bus masters with the priority levels in the priority level table for use in the second bus arbiter 514 of the previous generation processor 500 as shown in Fig. 12. This will be explained in accordance with a specific example.

In the case of the priority level information number 0 of Fig. 12 as an example, the priority levels are assigned as {SP, GP, DMA, CPU} . This is referred to as a bus master permutation in the following description. On the other hand, also by the use of the abbreviations shown in Fig. 14, the bus use request purpose permutation as selected of the sound processor 7 is {WAV, ENV}; the bus use request purpose permutation as selected of the graphics processor 3 is {BMP, CHR, HDR} ; the bus use request purpose permutation as selected of the pixel plotter 5 is {PLT} (this is because there is only one bus use request purpose for accessing the second bus 33 by the pixel plotter 5) ; the bus use request purpose permutation as selected of the DMA controller 9 is {DMAS} (for the same reason as that of the pixel plotter 5) ; and the bus use request purpose permutation as selected of the CPU 1 is { DAT , 1ST } .

In this case, in correspondence with the priority level information number 0 of the previous generation processor 500 as illustrated in Fig. 12, the bus use request purpose permutation (priority level information number 0) for use in the second bus arbiter 14 of the current generation processor 100 as illustrated in Fig. 14 is obtained by substituting the bus use request purpose permutation {WAV, ENV} for SP, the bus use request purpose permutation {BMP, CHR, HDR} for GP, the bus use request purpose permutation {DMAS} for DMA, and the bus use request purpose permutation {DAT, 1ST} for CPU, and additionally inserting the bus use request purpose permutation {PLT} into any appropriate position. This insertion of the bus use request purpose permutation {PLT} shall not disturb the order relation among the other bus masters. As a result, a priority level information set is prepared corresponding to the priority level information number 0 as illustrated in Fig. 14. Also, priority level information sets corresponding to the priority level information numbers 1 to 3 of Fig. 14 are prepared on the basis of the priority level information sets corresponding to the priority level information numbers 1 to 3 of Fig. 12.

As has been discussed above, while the number of bus access requests corresponding to purposes of using the second bus is significantly increased in the current generation processor 100 as compared with that in the previous generation processor 500, it is possible to maintain software compatibility since the priority levels of each priority level information set in the current generation processor 100 as shown in Fig. 14 are determined on the basis of the priority level table in the previous generation processor 500 as shown in Fig. 12. Incidentally, even if the pixel plotter 5 is included in the priority level information set of the second bus 33 of the current generation processor 100, the compatibility shall not be affected thereby because the previous generation processor 500 has no a pixel plotter and the software provided for the previous generation processor 500 is run without the use of a pixel plotter. Fig. 15 is a table for showing the list of hardware control registers provided in the second bus arbiter 14 of Fig. 1, and the hardware control registers are mapped in the address space of the first bus of of the current generation processor 100. As shown in Fig. 15, the second bus arbiter 14 is provided with a zeroth slot priority level register to the seventh slot priority level register. Each register is used to store a priority level information number of Fig. 14 as encoded. The CPU 1 can change the priority level information number stored in a register by accessing the register. Incidentally, in the physical address space of the first bus 31 of the current generation processor 100, each of these registers is located in the corresponding first bus address as illustrated in the figure.

As is apparent from Fig. 13 and Fig. 15, the current generation second bus arbiter 33 and the previous generation second bus arbiter 533 have the same constituent members of the control registers and the same addresses given to the respective control registers.

Meanwhile, in the case of the previous generation processor 500, it is possible to change the access speed to the second bus 533. Specifically speaking, the CPU 501 can set the bus cycle length of "the second bus zeroth area" and "the second bus first area and the second bus second area" of Fig. 6 respectively with the use of the number of clock cycles of the internal clock signal "ICLK" (2 to 8 cycles) by accessing a zeroth area access cycle number register and a first and a second area access cycle number register of Fig. 13. However, in the case of the previous generation processor 500, a page mode is not supported such that the bus cycle length for each area is always constant unless it is changed.

Also in the case of the current generation processor 100, it is possible to change the access speed to the second bus 33. However, in the case of the current generation processor 100, the CPU 1 can set the page size, the page access cycle number, the random access cycle number and the data bus width (8 bits/16 bits) respectively for each of the three areas, i.e., "the second bus zeroth area", "the second bus first area" and "the second bus second area" of Fig. 7 by accessing a zeroth area page size register, a first area page size register, a second area page size register, a zeroth area page access cycle number register, a first area page access cycle number register, a second page access cycle number register, a zeroth area random access cycle number register, a first area random access cycle number register, a second area random access cycle number register, a zeroth area bus width register, a first area bus width register, and a second area bus width register respectively as illustrated in Fig. 15.

As has been discussed above, while the previous generation processor 500 can change the way of accessing the second bus 533 only in terms of the access cycle number, the current generation processor 100 can change the way of accessing the second bus 33 in terms of the page size, the page access cycle number, the random access cycle number, and the data bus width. In addition to this, while different access cycle numbers cannot be set for the second bus first area and the second bus second area in the case of the previous generation processor 500, it is possible to independently set the access cycle numbers of the second bus first area and the second bus second area to different values in the case of the current generation processor 100.

As shown in Fig. 15, in the case of the current generation processor 100, while a virtual zeroth area access cycle number register is mapped to the same memory address in the first bus area as the zeroth area access cycle number register of the previous generation processor 500 shown in Fig. 13, a virtual first and second area access cycle number register is mapped to the same memory address of the first bus area as the first and second area access cycle number register of the previous generation processor 500 shown in Fig. 13.

When the CPU 1 of the current generation processor 100 writes data to the address assigned to the virtual zeroth area access cycle number register in the first bus area, the same data is written.also to the zeroth area random access cycle number register, and the zeroth area page size register is set to "0" (page size = 0 byte) such that the page mode is disabled. In a similar fashion, when the CPU 1 of the current generation processor 100 writes data to the address assigned to the virtual first and second area access cycle number register in the first bus area, the same data is written also to the first area random access cycle number register and the second area random access cycle number register, and the first area page size register and the second area page size register are set to "0" (page size = 0 byte) such that the page mode is disabled.

As has been discussed above, it is therefore possible to maintain the software backward compatibility of the current generation processor 100 with the previous generation processor 500. While it is possible for the current generation processor 100, unlike the previous generation processor 500, to independently set the access cycle numbers of the second bus first area and the second bus second area, this is not a problem in retaining compatibility because, when data is written to the address assigned to the virtual first and second area access cycle number register in the first bus area , the same data is written to the first area random access cycle number register and the second area random access cycle number register respectively. In this case, the adjective "virtual" is used because there is no physical instance corresponding to the zeroth area access cycle number register and the first and second area access cycle number register in the processor 100.

Meanwhile, as can be seen from Fig. 13 and Fig. 15, the external bus release request register of the previous generation processor 500 has the same configuration and the same address as the external bus release request register of the current generation processor 100.

In what follows, the first bus arbiter 13 shown in Fig. 1 will be explained in detail. Fig. 16 is a view for explaining the input and output signals of the first bus arbiter 13 shown in Fig. 1. Referring to Fig. 16, an instruction fetch address "UFA" output from the CPU 1 to the first bus arbiter 13, an instruction fetch bus use request signal "IIFB" output from the CPU 1 to the first bus arbiter 13, an instruction fetch read acknowledge signal "IIFRG" output from the first bus arbiter 13 to the CPU 1 are, respectively in the case where the first bus use request purpose is "instruction fetch", the read address, the signal indicative of a bus use request for read operation, and a signal indicating that a bus use request for reading data is granted and that the internal data "IDAI [7: O]" can be fetched.

A data access address "IDAA" output from the CPU 1 to the first bus arbiter 13, a data access write data "IDAW" output from the CPU 1 to the first bus arbiter 13, a data access bus use request signal "IDAB" output from the CPU 1 to the first bus arbiter 13, a data access write request signal "IDAWR" output from the CPU 1 to the first bus arbiter 13, a data access write acknowledge signal "IDAWG" output from the first bus arbiter 13 to the CPU 1, and a data access read acknowledge signal "IDARG" output from the first bus arbiter 13 to the CPU 1 are, respectively in the case where the first bus use request purpose is "data access", the read or write address, the data to be written, the signal indicative of a bus use request for reading or writing data, a signal indicating that the bus use request is issued for writing data, a signal indicating that a bus use request for writing data is granted, and a signal indicating that a bus use request for reading data is granted and that the internal data "IDAI [7: O]" can be fetched.

A first background array data address "FBGA" output from the graphics processor 3 to the first bus arbiter 13, a first background array data bus use request signal "FBGB" output from the graphics processor 3 to the first bus arbiter 13, and the first background array data read acknowledge signal "FBGRG" output from the first bus arbiter 13 to the graphics processor 3 are, respectively in the case where the first bus use request purpose is "first background array data", the read address, the signal indicative of a bus use request for read operation, and a signal indicating that a bus use request for reading data is granted and that the internal data "IDAI [7: 0]" can be fetched.

A second background array data address "SBGA" output from the graphics processor 3 to the first bus arbiter 13, the^' second background array data bus use request signal "SBGB" output from the graphics processor 3 to the first bus arbiter 13, and the second background array data read acknowledge signal "SBGRG" output from the first bus arbiter 13 to the graphics processor 3 are, respectively in the case where the first bus use request purpose is "second background array data", the read address, the signal indicative of a bus use request for read operation, and a signal indicating that a bus use request for reading data is granted and that the internal data "IDAI [7: O]" can be fetched.

A sprite DMA address "ISPA" output from the graphics processor 3 to the first bus arbiter 13, a sprite DMA bus use request signal "ISPB" output from the graphics processor 3 to the first bus arbiter

13, and a sprite DMA read acknowledge signal "ISPRG" output from the first bus arbiter 13 to the graphics processor 3 are, respectively in the case where the first bus use request purpose is "sprite DMA", the read address, the signal indicative of a bus use request for read operation, and a signal indicating that a bus use request for reading data is granted and that the internal data "IDAI [7: O]" can be fetched.

A character header address "ICHA" output from the graphics processor 3 to the first bus arbiter 13, a character header bus use request signal "ICHB" output from the graphics processor 3 to the first bus arbiter 13 and a character header read acknowledge signal "ICHRG" output from the first bus arbiter 13 to the graphics processor 3 , respectively in the case where the first bus use request purpose is "character header", the read address, the signal indicative of a bus use request for read operation, and a signal indicating that a bus use request for reading data is granted and that the internal data "IDAI [7:O]" can be fetched.

A character data address "ICDA" output from the graphics processor 3 to the first bus arbiter 13, a character data bus use request signal "ICDB" output from the graphics processor 3 to the first bus arbiter 13 and a character data read acknowledge signal "ICDRG" output from the first bus arbiter 13 to the graphics processor 3 are, respectively in the case where the first bus use request purpose is "character data", the read address, the signal indicative of a bus use request for read operation, and a signal indicating that a bus use request for reading data is granted and that the internal data "IDAI [7: O]" can be fetched.

A bitmap data address "IBMA" output from the graphics processor 3 to the first bus arbiter 13, a bitmap data bus use request signal "IBMB" output from the graphics processor 3 to the first bus arbiter 13, and a bitmap data read acknowledge signal "IBMRG" output from the first bus arbiter 13 to the graphics processor 3 are, respectively in the case where the first bus use request purpose is "bitmap data", the read address, the signal indicative of a bus use request for read operation, and a signal indicating that a bus use request for reading data is granted and that the internal data "IDAI [7:O]" can be fetched.

A pixel plotter address "IPPA" output from the pixel plotter 5 to the first bus arbiter 13, a pixel plotter write data "IPPW" output from the pixel plotter 5 to the first bus arbiter 13, a pixel plotter bus use request signal "IPPB" output from the pixel plotter 5 to the first bus arbiter 13, a pixel plotter write request signal "IPPWR" output from the pixel plotter 5 to the first bus arbiter 13, a pixel plotter write acknowledge signal "IPPWG" output from the first bus arbiter 13 to the pixel plotter 5, and a pixel plotter read acknowledge signal "IPPRG" output from the first bus arbiter 13 to the pixel plotter 5 are, respectively in the case where the first bus use request purpose is "pixel plotter", the read or write address, the data to be written, the signal indicative of a bus use request for reading or writing data, a signal indicating that the bus use request is issued for writing data, a signal indicating that a bus use request for writing data is granted, and a signal indicating that a bus use request for reading data is granted and that the internal data "IDAI [7: O]" can be fetched.

A wave data address "IWAA" output from the sound processor 7 to the first bus arbiter 13, a wave data bus use request signal "IWAB" output from the sound processor 7 to the first bus arbiter 13, and a wave data read acknowledge signal "IWARG" output from the first bus arbiter 13 to the sound processor 7 are, respectively in the case where the first bus use request purpose is "wave data", the read address, the signal indicative of a bus use request for read operation, and a signal indicating ^' that a bus use request for reading data is granted and that the internal data "IDAI [7: O]" can be fetched.

An envelope data address "IEVA" output from the sound processor 7 to the first bus arbiter 13, an envelope data write data "IEVW" output from the sound processor 7 to the first bus arbiter 13, an envelope data bus use request signal "IEVB" output from the sound processor 7 to the first bus arbiter 13, an envelope data write request signal "IEVWR" output from the sound processor 7 to the first bus arbiter 13, an envelope data write acknowledge signal ^■ "IEVWG" output from the first bus arbiter 13 to the sound processor 7, and an envelope data read acknowledge signal "IEVRG" output from the first bus arbiter 13 to the sound processor 7 are, respectively in the case where the first bus use request purpose is "envelope data ", the read or write address, the data to be written, the signal indicative of a bus use request for reading or writing data, a signal indicating that the bus use request -is issued for writing data, a signal indicating that a bus use request for writing data is granted, and a signal indicating that a bus use request for reading data.is granted and that the internal data "IDAI [7: O]" can be fetched. A DMA destination address "IDDA" output from the DMA controller 9 to the first bus arbiter 13, a DMA destination write data "IDDW" output from the DMA controller 9 to the first bus arbiter 13, a DMA destination bus use request signal "IDDB" output from the DMA controller 9 to the first bus arbiter 13, and a DMA destination write acknowledge signal "IDDWG" output from the first bus arbiter 13 to the DMA controller 9 are, respectively in the case where the first bus use request purpose is "DMA destination", the write address, the data to be written, the signal indicative of a bus use request for writing data, , a signal indicating that a bus use request for writing data is granted.

In this case, the above address signals "UFA", "IDAA", "FBGA", "SBGA", "ISPA", "ICHA", "ICDA", "IBMA", "IPPA", "IWAA", "IEVA" and "IDDA" are respectively 15-bit signals. Also, the signals indicative of the .above write data "IDAW", "IPPW", IEVW and IDDW are respectively 8-bit signals.

The first bus arbiter 13 outputs to the first bus 31 a first bus address "IAD", an internal write enable signal "IRW" and internal data "IDAO" after arbitration.

The first bus address "IAD" is an address signal (15 bits) to be output to the address bus 311 (refer to Fig. 18 to be described below) of the first bus 31. The internal write enable signal "IRW" is a write enable signal to be output to the control bus 313 (refer to Fig. 8) of the first bus 31. The internal write enable signal "IRW" can take a value of "1" for indicating a write enabled state and a value of "0" for indicating a read enabled state. The internal data "IDAO" is data (8 bits) to be output to the data bus 312 (refer to Fig. 8) of the first bus 31.

A multiplexer 40 shown in Fig. 16 receives a data item "FBDO" (to be described below) from the first bus arbiter 13 as well as data items "FBDl" to "FBDn" (n is an integer) from other functional blocks (for example, the graphics processor 3, the pixel plotter 5, the sound processor 7, the DMA controller 9, the second bus arbiter 14, the main memory 17 and the like) .

An address decoder 38 also shown in Fig. 16 decodes the first bus address "IAD" output from the first bus arbiter 13, and outputs a select signal to the multiplexer 40 for selecting one of the data items "FBDO" to "FBDn". The multiplexer 40 selects one of the input data items "FBDO" to "FBDn" in accordance with this select signal and outputs the selected data item as internal data "IDAI". Fig. 17 is a block diagram showing the internal configuration of the first bus arbiter 13 of Fig. 16. As shown in Fig. 17, the first bus arbiter 13 includes an address decoder 317, a zeroth slot priority level register 300 to a 15th slot priority level register 315, multiplexers 319 and 321, a read/write acknowledge signal generation circuit 327, a slot counter 323, an OR gate 324, a priority decoder 325, a multiplexers 329, 331, 333 and 335, and registers 337, 339, 341 and 343.

In this description, the term "priority level register IPRO" is used to generally represent the zeroth slot priority level register 300 to the 15th slot priority level register 315.

Each of the zeroth slot priority level register 300 to the 15th slot priority level register 315 is set to any one of the priority level information numbers 0 to 3 of Fig. 10. For example, the zeroth slot priority level register 300 to the 15th slot priority level register 315 are set respectively to the priority level information number 0, the priority level information number 3, the priority level information number 1, the priority level information number 3, the priority level information number 0, the priority level information number 3, the priority level information number 2, the priority level information number 3, the priority level information number 0, the priority level information number 3, the priority level information number 2, the priority level information number 3, the priority level information number 0, the priority level information number 3, the priority level information number 2 and the priority level information number 3. Incidentally, the priority level information numbers 0 to 3 are encoded into 2-bit numbers respectively. Accordingly, each of the zeroth slot priority level register 300 to the 15th slot priority level register 315 is a 2-bit register.

The CPU 1 serves to load appropriate numbers respectively to the zeroth slot priority level register 300 to the 15th slot priority level register 315 in order to set an arbitrary series of 16 numbers, which are selected respectively from among the priority level information numbers 0 to 3, constituting a cycle of 16 slots. Conversely, the CPU 1 can read the data which is set in any one of the zeroth slot priority level register 300 to the 15th slot priority level register 315.

The address decoder 317 decodes the first bus address "IAD" generated as a result of the bus arbitration. If the first bus address "IAD" designates any one of the zeroth slot priority level register 300 to the 15th slot priority level register 315 and if the internal write enable signal "IRW" is asserted to indicate a write enabled state, the address decoder 317 outputs a select signal to the priority level register "IPRO" that is pointed to by the first bus address "IAD"

When the select signal from the address decoder 317 is input to the priority level register "IPRO", the internal data "IDAO" is stored in the priority level register "IPRO" as a priority level information number.

The first bus address "IAD" in this case is the data access address "IDAA" as selected by a multiplexer 331 to be described below and output from the CPU 1. The internal write enable signal "IRW" in this case is the data access write request signal "IDAWR" as selected by a multiplexer 335 to be described below and output from the CPU 1. The internal data "IDAO" in this case is the data access write data "IDAW" as selected by a multiplexer 333 to be described below and output from the CPU 1.

On the other hand, the address decoder 317 decodes the first bus address "IAD" generated as a result of the bus arbitration. If the first bus address "IAD" designates any one of the zeroth slot priority level register 300 to the 15th slot priority level register 315 and if the internal write enable signal "IRW" is asserted to indicate a read enabled state, the address decoder 317 outputs to the multiplexer 319 a select signal for selecting the priority level register IPRO that is pointed to by the first bus address "IAD". The multiplexer 319 outputs as data "FBDO" the encoded priority level information number stored in the priority level register "IPRO" selected by this select signal to the multiplexer 40 of Fig. 16.

The first bus address "IAD" in this case is the data access address "IDAA" as selected by a multiplexer 331 to be described below and output from the CPU 1. The internal write enable signal "IRW" in this case is the data access write request signal "IDAWR" as selected by a multiplexer 335 to be described below and output from the CPU 1.

As has been discussed above, the CPU 1 can write data to or read data from the zeroth slot priority level register 300 to the 15th slot priority level register 315 through the first bus 31. The multiplexer 321 selects one of the zeroth slot priority level register 300 to the 15th slot priority level register 315 in accordance with the select signal "ISSEL" from the slot counter 323, and output the priority level information number stored in the priority level register "IPRO" to the priority decoder 325. The CPU 1 outputs the instruction fetch bus use request signal "IIFB" and the data access bus use request signal "IDAB" to the priority decoder 325; the graphics processor 3 outputs the first background array data bus use request signal "FBGB", the second background array data bus use request signal "SBGB", the sprite DMA bus use request signal "ISPB", the character header bus use request signal "ICHB", the character data bus use request signal "ICDB", and the bitmap data bus use request signal "IBMB" to the priority decoder 325; the pixel plotter 5 outputs the pixel plotter bus use request signal "IPPB" to the priority decoder 325; the sound processor 7 outputs the wave data bus use request signal "IWAB" and the envelope data bus use request signal "IEVB" to the priority decoder 325; and the DMA controller 9 outputs the DMA destination bus use request signal "IDDB" to the priority decoder 325.

Also, the read/write acknowledge signal generation circuit 327 outputs to the priority decoder 325 the instruction fetch read acknowledge signal "IIFRG", the data access read acknowledge signal "IDARG", the data access write acknowledge signal "IDAWG", the first background array data read acknowledge signal "FBGRG", the second background array data read acknowledge signal "SBGRG", the sprite DMA read acknowledge signal "ISPRG", the character header read acknowledge signal "ICHRG", the character data read acknowledge signal "ICDRG", the bitmap data read acknowledge signal "IBMRG", the pixel plotter read acknowledge signal "IPPRG", the pixel plotter write acknowledge signal "IPPWG", the wave data read acknowledge signal "IWARG", the envelope data read acknowledge signal "IEVRG", the envelope data write acknowledge signal "IEVWG", and the DMA destination write acknowledge signal "IDDWG".

In this description, the term "first bus use request signal FBURQ" is used to generally represent the bus use request signals "HFB", "IDAB", "FPBG", "SBGB", "ISPB", "ICHB", "ICDB", "IBMB", "IPPB", "IWAB", "IEVB" and "IDDB".

The priority decoder 325 decodes the priority level information number currently input from the multiplexer 321. Then, the priority decoder 325 selects, in accordance with the priority level information set corresponding to the priority level information number as decoded, a first bus use request purpose having the highest priority from among the first bus use request purposes corresponding to the first bus use request signals "FBURQ", which are asserted, except for the first bus use request purpose for which the first bus 31 is currently used. The first bus use request purpose for which the first bus 31 is currently used can be determined on the basis of the states of the first bus use acknowledge signals "FAGR" output from the read/write acknowledge signal generation circuit 327.

Meanwhile, the first bus use acknowledge signal "FAGR" is used to generally represent the instruction fetch read acknowledge signal "HFRG", the data access read acknowledge signal "IDARG", the data access write acknowledge signal "IDAWG", the first background array data read acknowledge signal "FBGRG", the second background array data read acknowledge signal "SBGRG", the sprite DMA read acknowledge signal "ISPRG", the character header read acknowledge signal "ICHRG", the character data read acknowledge signal "ICDRG", the bitmap data read acknowledge signal "IBMRG", the pixel plotter read acknowledge signal "IPPRG", the pixel plotter write acknowledge signal "IPPWG", the wave data read acknowledge signal "IWARG", the envelope data read acknowledge signal "IEVRG", the envelope data write acknowledge signal "IEVWG", and the DMA destination write acknowledge signal "IDDWG".

Also, the priority decoder 325 generates a bus master select signal "IBMSL[3: O]" on the basis of the first bus use request purpose as selected, and outputs it to the multiplexers 329, 331, 333 and 335. In other words, in accordance with the priority level information set corresponding to the priority level information number as decoded, the priority decoder 325 sets the bus master select signal "IBMSL [3: O]" to a value indicative of a first bus use request purpose having the highest priority from among the first bus use request purposes corresponding to the first bus use request signals "FBURQ", which are asserted, except for the first bus use request purpose for which the first bus 31 is currently used.

The OR gate 324 receives the first bus use acknowledge signals "FAGR" (IIFRG, IDARG, IDAWG, FBGRG, SBGRG, ISPRG, ICHRG, ICDRG, IBMRG, IPPRG, IPPWG, IWARG, IEVRG, IEVWG and IDDWG) from the read/write acknowledge signal generation circuit 327.

The slot counter 323 increments the value of the select signal "ISSEL [3:0]" every time the signal from the OR gate 324 changes from "0" (false) to "1" (truth) in order that the multiplexer 321 sequentially and cyclically selects one of the priority level information numbers stored in the zeroth slot priority level register 300 to the 15th slot priority level register 315. This is because the end of one bus cycle of which the bus ownership is granted to a bus master is obtained by the logical OR of the 15 first bus use acknowledge signals "FAGR".

The respective 12 input terminals of each of the multiplexers 329, 331, 333 and 335 correspond to the 12 first bus use request purposes, i.e., "instruction fetch", "data access", "first background array data", "second background array data", "sprite DMA", "character header", "character data", "bitmap data", "pixel plotter", "wave data", "envelope data" and "DMA destination".

The 12 signals input to the multiplexer 329 are respectively a code of "ObOOOOOOOOOOOl" which indicates the first bus use request purpose of "instruction fetch", a code of "ObOOOOOOOOOOlO" which indicates the first bus use request purpose of "data access", a code of "ObOOOOOOOOOlOO" which indicates the first bus use request purpose of "first background array data", a code of "ObOOOOOOOOlOOO" which indicates the first bus use request purpose of "second background array data", a code of "ObOOOOOOOlOOOO" which indicates the first bus use request purpose of "sprite DMA", a code of "ObOOOOOOlOOOOO" which indicates the first bus use request purpose of "character header", a code of "ObOOOOOlOOOOOO" which indicates the first bus use request purpose of "character data", a code of "ObOOOOlOOOOOOO" which indicates the first bus use request purpose of "bitmap data", a code of "ObOOOlOOOOOOOO" which indicates the first bus use request purpose of "pixel plotter", a code of "ObOOIOOOOOOOOO" which indicates the first bus use request purpose of "wave data", a code of "ObOIOOOOOOOOOO" which indicates the first bus use request purpose of "envelope data", a code of ObIOOOOOOOOOOO which indicates the first bus use request purpose of "DMA destination".

The multiplexer 329 selects the code corresponding to the first bus use request purpose (to which the bus ownership of the first bus 31 is to be granted) selected by the bus master select signal "IBMSL" input from the priority decoder 325, and outputs it to the register 337.

The register 337 latches the code input from the multiplexer 329, and outputs it to the read/write acknowledge signal generation circuit 327.

The read/write acknowledge signal generation circuit 327 generates the first bus use acknowledge signal "FAGR" on the basis of the code output from the register 337. More specific description is as follows.

The read/write acknowledge signal generation. circuit 327 asserts the instruction fetch read acknowledge signal "IIFRG" if the code output from the register 337 is ObOOOOOOOOOOOl. Also, the read/write

■ acknowledge signal generation circuit 327 asserts the data access read acknowledge signal "IDARG" if the code output from the register 337 is

ObOOOOOOOOOOlO and if the data access write request signal "IDAWR" is negated. Furthermore, the read/write acknowledge signal generation circuit 327 asserts the data access write acknowledge signal "IDAWG" if the code output from the register 337 is ObOOOOOOOOOOlO and if the data access write request signal "IDAWR" is asserted.

Still further, the read/write acknowledge signal generation circuit 327 asserts the first background array data read acknowledge signal "FBGRG" if the code output from the register 337 is ObOOOOOOOOOlOO. Still further, the read/write acknowledge signal generation circuit 327 asserts the second background array data read acknowledge signal "SBGRG" if the code output from the register 337 is ObOOOOOOOOlOOO. Still further, the read/write acknowledge signal generation circuit 327 asserts the sprite DMA read acknowledge signal "ISPRG" if the code output from the register 337 is ObOOOOOOOlOOOO.

Still further, the read/write acknowledge signal generation circuit 327 asserts the character header read acknowledge signal "ICHRG" if the code output from the register 337 is ObOOOOOOlOOOOO. Still further, the read/write acknowledge signal generation circuit 327 asserts the character data read acknowledge signal "ICDRG" if the code output from the register 337 is ObOOOOOlOOOOOO. Still further, the read/write acknowledge signal generation circuit 327 asserts the bitmap data read acknowledge signal "IBMRG" if the code output from the register 337 is ObOOOOlOOOOOOO.

Still further, the read/write acknowledge signal generation circuit 327 asserts the pixel plotter read acknowledge signal "IPPRG" if the code output from the register 337 is ObOOOlOOOOOOOO and if the pixel plotter write request signal "IPPWR" is negated. Still further, the read/write acknowledge signal generation circuit 327 asserts the pixel plotter write acknowledge signal "IPPWG" if the code output from the register 337 is ObOOOlOOOOOOOO and if the pixel plotter write request signal "IPPWR" is asserted.

Still further, the read/write acknowledge signal generation circuit 327 asserts the wave data read acknowledge signal "IWARG" if the code output from the register 337 is ObOOIOOOOOOOOO. Still further, the read/write acknowledge signal generation circuit 327 asserts the envelope data read acknowledge signal "IEVRG" if the code output from the register 337 is ObOIOOOOOOOOOO and if the envelope data write request signal "IEVWR" is negated. Still further, the read/write acknowledge signal generation circuit 327 asserts the envelope data write acknowledge signal "IEVWG" if the code output from the register 337 is ObOIOOOOOOOOOO and if the envelope data write request signal "IEVWR" is asserted. Still further, the read/write acknowledge signal generation circuit 327 asserts the DMA destination write acknowledge signal "IDDWG" if the code output from the register 337 is ObIOOOOOOOOOOO.

The 12 signals input to the multiplexer 331 are respectively the instruction fetch address "UFA", the data access address "IDAA", the first background array data address "FBGA", the second background array data address "SBGA", the sprite DMA address "ISPA", the character header address "ICHA", the character data address "ICDA", the bitmap data address "IBMA", the pixel plotter address "IPPA", the wave data address "IWAA", the envelope data address "IEVA" and the DMA destination address "IDDA".

Of these 12 input address signals, the multiplexer 331 outputs to the register 339 the address signal corresponding to the first bus use request purpose (to which the bus ownership of the first bus 31 is to be granted) selected by the bus master select signal "IBMSL". The register 339 latches an address signal input from the multiplexer 331, and outp'uts it as the first bus address "IAD[14: 0] " .

The 12 signals input to the multiplexer 333 are respectively "0" corresponding to the first bus use request purpose of "instruction fetch", the data access write data "IDAW", "0" corresponding to the first bus use request purpose of "the first background array data", "0" corresponding to the first bus use request purpose of "the second background array data", "0" corresponding to the first bus use request purpose of "sprite DMA", "0" corresponding to the first bus use request purpose of "character header", "0" corresponding to the first bus use request purpose of "character data", "0" corresponding to the first bus use request purpose of "bitmap data", the pixel plotter write data "IPPW", "0" corresponding to the first bus use request purpose of "wave data", the envelope data write data "IEVW" and the DMA destination write data "IDDW". In this case, the input value of "0" means that there is no write request. This is because write operation is not performed for these first bus use request purposes, i.e., "instruction fetch", "first background array data", "second background array data", "character header", "character data", "bitmap data", and "wave data". The multiplexer 333 outputs to the register 341 the input write data signal corresponding to the first bus use request (to which the bus ownership of the first bus 31 is to be granted) selected by the bus master select signal "IBMSL" from among the above 12 input write data signals. The register 341 latches write data as input from the multiplexer 333, and outputs it as the internal data "IDAO[7: 0] ".

The 12 signals input to the multiplexer 335 are respectively "0" corresponding to the first bus use request purpose of "instruction fetch", the data access write request signal "IDAWR", "0" corresponding to the first bus use request purpose of "the first background array data", "0" corresponding to the first bus use request purpose of "the second background array data", "0" corresponding to the first bus use request purpose of "sprite DMA", "0" corresponding to the first bus use request purpose of "character header", "0" corresponding to the first bus use request purpose of "character data", "0" corresponding to the first bus use request purpose of "bitmap data", the pixel plotter write request signal "IPPWR", "0" corresponding to the first bus use request purpose of "wave data", the envelope data write request signal "IEVWR" and "l"corresponding to the first bus use request purpose of "DMA destination". In this case, the input value of "0" means that there is no write request. This is because write operation is not performed for these first bus use request purposes, i.e., "instruction fetch", "first background array data", "second background array data", "character header", "character data", "bitmap data", and "wave data". Also, in this case, the input value of "1" means that there is no read request. This is because only write operation is performed corresponding to the first bus request purpose "DMA destination".

The multiplexer 335 outputs to the register 343 the input signal corresponding to the first bus use request purpose (to which the bus ownership of the first bus 31 is to be granted) selected by the bus master select signal "IBMSL" from among the above 12 input signals.

The register 343 latches the signal as input from the multiplexer 335, and outputs it as the internal write enable signal "IRW".

Next, the second bus arbiter 14 of Fig. 1 will be explained in detail.

Fig. 18 is a view for explaining the input and output signals of the second bus arbiter 14 shown in Fig. 1. As illustrated in Fig. 18, the CPU 1 serves to control the second bus arbiter 14 through the address bus 311, the data bus 312 and the control bus 313.

An instruction fetch address "EIFA" output from the CPU 1 to the second bus arbiter 14, an instruction fetch size signal "EIFS" output from the CPU 1 to the second bus arbiter 14, an instruction fetch bus use request signal "EIFB" output from the CPU 1 to the second bus arbiter 14, an instruction fetch lower byte read acknowledge signal "EIFLR" output from the second bus arbiter 14 to the CPU 1, and an instruction fetch upper byte read acknowledge signal "EIFUR" output from the second bus arbiter 14 to the CPU 1 are, respectively in the case where the second bus use request purpose is "instruction fetch ", the read address, the signal indicative of the amount of data to be requested (the signal indicative of the number of bytes to be read) , the signal indicative of a bus use request for reading data, a signal indicating that a bus use request for reading data is granted and that the lower bytes ([7:0]) of an external data input signal "EDAI" can be fetched, and a signal indicating that a bus use request for reading data is granted and that the upper bytes ([15:8]) of the external data input signal "EDAI" can be fetched.

A data access address "EDAA" output from the CPU 1 to the second bus arbiter 14, a data access write data "EDAW" output from the CPU 1 to the second bus arbiter 14, a data access bus use request signal "EDAB" output from the CPU 1 to the second bus arbiter 14, a data access write request signal "EDAWR" output from the CPU 1 to the second bus arbiter 14, a data access write acknowledge signal "EDAWG" output from the second bus arbiter 14 to the CPU 1, a data access lower byte read acknowledge signal "EDALR" output from the second bus arbiter 14 to the CPU 1 and a data access upper byte read acknowledge signal "EDAUR" output from the second bus arbiter 14 to the CPU 1 are, respectively in the case where the second bus use request purpose is "data access", the read or write address, the data to be written, the signal indicative of a bus use request for reading or writing data, a signal indicating that the bus use request is issued for writing data, a signal indicating that a bus use request for writing data is granted, a signal indicating that a bus use request for reading data is granted and that the lower bytes ([7:0]) of an external data input signal "EDAI" can be fetched, and a signal indicating that a bus use request for reading data is granted and that the upper bytes ([15:8]) of the external data input signal "EDAI" can be fetched.

A character header address "ECHA" output from the graphics processor 3 to the second bus arbiter 14, a character header size

• signal "ECHS" output from the graphics processor 3 to the second bus arbiter 14, a character header bus use request signal "ECHB" output from the graphics processor 3 to the second bus arbiter 14, a character header lower byte read acknowledge signal "ECHLR" output from the second bus arbiter 14 to the graphics processor 3 and a character header upper byte read acknowledge signal "ECHUR" output from the second bus arbiter 14 to the graphics processor 3 are, respectively in the case where the second bus use request purpose is "character header", the read address, the signal indicative of the amount of data to be requested (the signal indicative of the number of bytes to be read) , the signal indicative of a bus use request for reading data, a signal indicating that a bus use request for reading data is granted and that the lower bytes ([7:0]) of an external data input signal "EDAI" can be fetched, and a signal indicating that a bus use request for reading data is granted and that the upper bytes ([15:8]) of the external data input signal "EDAI" can be fetched.

A character data address "ECDA" output from the graphics processor 3 to the second bus arbiter 14, a character data size signal "ECDS" output from the graphics processor 3 to the second bus arbiter 14, a character data bus use request signal "ECDB" output from the graphics processor 3 to the second bus arbiter 14, a character data lower byte read acknowledge signal "ECDLR" output from the second bus arbiter 14 to the graphics processor 3 and a character data upper byte read acknowledge signal "ECDUR" output from the second bus arbiter 14 to the graphics processor 3 are, respectively in the case where the second bus use request purpose is "character data", the read address, the signal indicative of the amount of data to be requested (the signal indicative of the number of bytes to be read) , the signal indicative of a bus use request for reading data, a signal indicating that a bus use request for reading data is granted and that the lower bytes ([7:0]) of an external data input signal "EDAI" can be fetched, and a signal indicating that a bus use request for reading data is granted and that the upper bytes ([15:8]) of the external data input signal "EDAI" can be fetched. A bitmap data address "EBMA" output from the graphics processor 3 to the second bus arbiter 14, a bitmap data bus use request signal "EBMB" output from the graphics processor 3 to the second bus arbiter 14, a bitmap data lower byte read acknowledge signal "EBMLR" output from the second bus arbiter 14 to the graphics processor 3 and a bitmap data upper byte read acknowledge signal "EBMUR" output from the

^■ second bus arbiter 14 to the graphics processor 3 are, respectively in the case where the second bus use request purpose is "bitmap data", the read address, the signal indicative of a bus use request for reading data, a signal indicating that a bus use request for reading data is granted and that the lower bytes ([7:0]) of an external data input signal "EDAI" can be fetched, and a signal indicating that a bus use request for reading data is granted and that the upper bytes ([15:8]) of the external data input signal "EDAI" can be fetched.

A pixel plotter address "EPPA" output from the pixel plotter 5 to the second bus arbiter 14, a pixel plotter write data "EPPW" output from the pixel plotter 5 to the second bus arbiter 14, a pixel plotter size signal "EPPS" output from the pixel plotter 5 to the second bus arbiter 14, a pixel plotter bus use request signal "EPPB" output from the pixel plotter 5 to the second bus arbiter 14, a pixel plotter write request signal "EPPWR" output from the pixel plotter 5 to the second bus arbiter 14, a pixel plotter write acknowledge signal "EPPWG" output from the second bus arbiter 14 to the pixel plotter 5, a pixel plotter lower byte read acknowledge signal "EPPLR" output from the second bus arbiter 14 to the pixel plotter 5 and a pixel plotter upper byte read acknowledge signal "EPPUR" output from the second bus arbiter 14 to the CPU 1 are, respectively in the case where the second bus use request purpose is "pixel plotter", the read or write address, the data to be written, the signal indicative of the amount of data to be reqested (the signal indicative of the number of bytes to be read or written) , the signal indicative of a bus use request for reading or writing data, a signal indicating that the bus use request is issued for writing data, a signal indicating that a bus use request for writing data is granted, a signal indicating that a bus use request for reading data is granted and that the lower bytes ([7:0]) of an external data input signal "EDAI" can be fetched, and a signal indicating that a bus use request for reading data is granted and that the upper bytes ([15:8]) of the external data input signal "EDAI" can be fetched.

A wave data address "EWAA" output from the sound processor 7 to the second bus arbiter 14, a wave data bus use request signal "EWAB" output from the sound processor 7 to the second bus arbiter 14, a wave data lower byte read acknowledge signal "EWALR" output from the second bus arbiter 14 to the sound processor 7 and a wave data upper byte read acknowledge signal "EWAUR" output from the second bus arbiter 14 to the sound processor 7 are, respectively in the case where the

■ second bus use request purpose is "wave data", the read address, the signal indicative of a bus use request for reading data, a signal indicating that a bus use request for reading data is granted and that the lower bytes ([7:0]) of an external data input signal "EDAI" can be fetched, and a signal indicating that a bus use request for reading data is granted and that the upper bytes ([15:8]) of the external data input signal "EDAI" can be fetched.

An envelope data address "EEVA" output from the sound processor 7 to the second bus arbiter 14, an envelope data bus use request signal "EEVB" output from the sound processor 7 to the second bus arbiter 14, an envelope data lower byte read acknowledge signal "EEVLR" output from the second bus arbiter 14 to the sound processor 7 and an envelope data upper byte read acknowledge signal "EEVUR" output from the second bus arbiter 14 to the sound processor 7 are, respectively in the case where the second bus use request purpose is "envelope data", the read address, the signal indicative of a bus use request for reading data, a signal indicating that a bus use request for reading data is granted and that the lower bytes ([7:0]) of an external data input signal "EDAI" can be fetched, and a signal indicating that a bus use request for reading data is granted and that the upper bytes ([15:8])^' of the external data input signal "EDAI" can be fetched.

A DMA source address "EDSA" output from the DMA controller 9 to the second bus arbiter 14, a DMA source size signal "EDSS" output from the DMA controller 9 to the second bus arbiter 14, a DMA source bus use request signal "EDSB" output from the DMA controller 9 to the second bus arbiter 14, a DMA source lower byte read acknowledge signal "EDSLR" output from the second bus arbiter 14 to the DMA controller 9 and a DMA source upper byte read acknowledge signal "EDSUR" output from the second bus arbiter 14 to the DMA controller 9 are, respectively in the case where the second bus use request purpose is "DMA source", the read address, the signal indicative of the amount of data to be requested (the signal indicative of the number of bytes to be read) , the signal indicative of a bus use request for reading data, a signal indicating that a bus use request for reading data is granted and that the lower bytes ([7:0]) of an external data input signal "EDAI" can be fetched, and a signal indicating that a bus use request for reading data is granted and that the upper by.tes ([15:8]) of the external data input signal "EDAI" can be fetched. Here, each of the above address signals "EIFA", "EDAA", ECHA,

• ECDA, EBMA, EPPA, EWAA, EEVA and EDSA is a 27-bit signal. Also, each of the above write data "EDAW" and "EPPW" is a 16-bit signal. However, the effective data of the write data "EDAW" is the lower 8 bits of the

16-bit signal. Fig. 19 is a view for showing exemplary sizes of data as requested for the respective second bus use request purposes in accordance with the present embodiment. As shown in Fig. 19, in the case where the second bus use request purpose is "instruction fetch", the CPU 1 can request any one of 1, 2, 3 and 4 bytes as a data transmission size by outputting the instruction fetch size signal "EIFS" (variable data size) .

Accordingly, the CPU 1 can dynamically designate a data transmission size corresponding to the size of the instruction to be fetched by the instruction fetch size signal "EIFS". In the case where the second bus use request purpose is "data access", the data transmission size is fixed to one byte. In the case where the second bus use request purpose is "character header", the graphics processor 3 can request 0 byte as a data transmission size by the character header size signal "ECHS" (i.e., no data is transferred) . In the case where the second bus use request purpose is "character data", the graphics processor 3 can request any one of 1, 2, 3, ... 15 or 16 bytes as a data transmission size by the character data size signal "ECDS" (variable data size) .

There are characters of varied sizes, such as 8 x 8 pixels, 8 * 16 pixels, 16 « 8 pixels, 16 * 16 pixels and so forth. Also, there are a variety of modes corresponding to varied sizes of data per pixel such as 1, 2, 3, ... 7 or 8 bits. Accordingly, the graphics processor 3 can dynamically designate a data transmission size corresponding to the size of a character and the size of data per pixel ^' by the character data size signal "ECDS".

When the second bus use request purpose is "bitmap data", the data transmission size is fixed to 8 bytes.

When the second bus use request purpose is "pixel plotter", the pixel plotter 5 can request 1 or 2 bytes as a data transmission size by the pixel plotter size signal "EPPS" (variable data size) .

For example, in the case where the starting address has "1" as its LSB (least significant bit) , the pixel plotter 5 designates one byte as a data transmission size for starting the .access by the pixel plotter size signal "EPPS", otherwise the pixel plotter 5 designates 2 bytes as a data transmission size by the pixel plotter size signal

■ "EPPS". This is because it is useless to read/write the lower byte in the case of this one-byte access.

When the second bus use request purpose is "wave data", the data transmission size is fixed to one byte. When the second bus use request purpose is "envelope data", the data transmission size is fixed to one byte.

When the second bus use request purpose is "DMA source", the DMA controller 9 can request any one of 1, 2, 3 and 4 bytes as a data transmission size by the DMA source size signal "EDSS" (variable data size) .

Accordingly, the DMA controller 9 can dynamically designate a data transmission size corresponding to the size of the data to be transferred from the DMA source by the DMA source size signal "EDSS".

Returning to Fig. 18, the second bus arbiter 14 serves to output to the second bus 33 a second bus address "EAD", a second bus address output enable signal "EADOE", external data "EDAO", an external data output enable signal "EDAOE", an external read enable signal "ERDE", an external write enable signal "EWRE", a lower byte enable signal

"LWBE", an upper byte enable signal "UPBE", a first area select signal "ASSELl" and a second area select signal "ASSEL2". The second bus address "EAD" is an address signal (27 bits) to be output to the address bus (not shown in the figure) of the second bus 33.

The external data "EDAO" is data (16 bits) to be output to the data bus (not shown in the figure) of the second bus 33. The external data output enable signal "EDAOE" controls a tri-state buffer (not shown in the figure) for connecting the data bus of the second bus 33 to the data bus of the external bus 43 in order to switch between an output state and an Hi-Z (high impedance) state. The external read enable signal "ERDE" is a read enable signal to be output to the control bus (not shown in the figure) of the second bus 33. The external write enable signal "EWRE" is a write enable signal to be output to the control bus of the second bus 33.

The lower byte enable signal "LWBE" is a lower byte enable signal of the data bus of the second bus 33. The upper byte enable signal "UPBE" is an upper byte enable signal of the data bus of the second bus 33.

The first area select signal "ASSELl" is a signal for selecting the second bus first area of the logical address space of the processor 100. The second area select signal "ASSEL2" is a signal for selecting the second bus second area of the logical address space of the processor 100. Incidentally, the second bus address "EAD[22]" serves as a signal for selecting the second bus zeroth area of the second bus (the zeroth area select signal "ASSELO") . The second bus address output enable signal "EADOE" controls a tri-state buffer (not shown in the figure) for connecting the address bus of the second bus 33, the control bus (ERDE and EWRE) , the lower byte enable signal "LWBE", the upper byte enable signal "UPBE", the first area select signal "ASSELl", and the second area select signal "ASSEL2" to the external bus 43, in order to switch between an output state and an Hi-Z (high impedance) state.

Fig. 20 is a block diagram showing the internal configuration of the second bus arbiter 14 of Fig. 18. As shown in Fig. 20, the second bus arbiter 14 includes a first bus interface circuit 140, a multiplexer 141, an OR gate 210, a priority decoder 142, multiplexers 143 to 146, registers 230 to 233, a slot counter 147, an OR gate 148, an address decoder 149, a byte enable signal generation circuit 150, multiplexers 151 to 153, a decoder 154, a state machine 155, an external bus release request register 156, a zeroth area bus width register 160, a first area bus width register 161, a second area bus width register 162, a zeroth area random access cycle number register 170, a first area random access cycle number register 171, a second area random access cycle number register 172, a zeroth area page access cycle number register 180, a first area page access cycle number register 181, a second area page access cycle number register 182, a zeroth area page size register 190, a first area page size register 191, a second area page size register 192, and a zeroth slot priority level register 200 to a seventh slot priority level register 207. The first bus interface circuit 140 is an interface to connect the first bus 31 with the respective control registers 156, 160 to 162, 170 to 172, 180 to 182, 190 to 192 and 200 to 207.

In this description, the term "control register CR" is used to generally represent the control registers 156, 160 to 162, 170 to 172, 180 to 182, 190 to 192 and 200 to 207.

The CPU 1 can write data to or read data from the control register "CR" through the first bus interface circuit 140. More specifically speaking, the CPU 1 designates a . read operation by- negating the internal write enable signal "IRW" to read the data from the control register CR of the second bus arbiter 15 as the internal

■ data "IDAI" corresponding to the first bus address "IAD". Also, the

CPU 1 designates a write operation by asserting the internal write enable signal "IRW" to write data output as the internal data "IDAO" to the control register "CR" of the second bus arbiter 15 designated by the first bus address "IAD".

The value of the external bus release request register 156 is input to the state machine 155. When the external bus release request register 156 is set to a "1" by the CPU 1, the state machine 155 puts the address bus, the data bus and the control bus (not shown in the figure) of the external bus 43 respectively in a high impedance state. For example, in the case where an external bus use request is issued by another device sharing the external bus 43 with the processor 100, the external bus release request register 156 is set to a "1".

The zeroth area bus width register 160 is set to the information indicative of the bus width of the data bus for use in accessing the second bus zeroth area. The first area bus width register 161 is set to the information indicative of the bus width of the data bus for use in accessing the second bus first area. The second area bus width register 162 is set to the information indicative of the bus width of the data bus for use in accessing the second bus second area. In the case of the present embodiment, each of the zeroth area bus width register 160, the first area bus width register 161 and the second area bus width register 162 can be set to the information indicative of an 8 or 16-bit bus width. The zeroth area random access cycle number register 170 is set to the information indicative of the access cycle number (the number of clock cycles) corresponding to the bus cycle period required for accessing the second bus zeroth area in a random access mode. The first area random access cycle number register 171 is set to the information indicative of the access cycle number (the number of clock cycles) corresponding to the bus cycle period required for accessing the second bus first area in a random access mode. The second area random access cycle number register 172 is set to the information indicative of the access cycle number (the number of clock cycles) corresponding to the bus cycle period required for accessing the second bus second area in a random access mode. In this case, the bus cycle period (i.e., the period of one bus cycle) is designated in terms of the number of clock cycles of the internal clock signal "ICLK". In the case of the present embodiment, each of the zeroth area random access cycle number register 170, the first area random access cycle number register 171 and the second area random access cycle number register 172 is set to the information indicative of 2 to 8 cycles of the internal clock signal "ICLK". The zeroth area page access cycle number register 180 is set to the information indicative of the access cycle number (the number of clock cycles) corresponding to the bus cycle period required for accessing the second bus zeroth area in a page mode. The first area page access cycle number register 181 is set to the information indicative of the access cycle number (the number of clock cycles) corresponding to the bus cycle period required for accessing the second bus first area in a page mode. The second area page access cycle number register 182 is set to the information indicative of the access cycle number (the number of clock cycles) corresponding to the bus cycle period required for accessing the second bus second area in a page mode. In this case, the bus cycle period (i.e., the period of one bus cycle) is designated in terms of the number of clock cycles of the internal clock signal "ICLK".

In the case of the present embodiment, each of the zeroth area page access cycle number register 180, the first area page access cycle number register 181 and the second area page access cycle number register 182 is set to the information indicative of 1 to 4 cycles of the internal clock signal "ICLK".

The zeroth area page size register 190 is set to the information indicative of the page size required when the second bus zeroth area is accessed in a page mode. The first area page size register 191 is set to the information indicative of the page size required when the second bus first area is accessed in a page mode. The second area page size register 192 is set to the information indicative of the page size required when the second bus second area is accessed in a page mode. In the case of the present embodiment, each of the zeroth area page size register 190, the first area page size register 191 and the second area page size register 192 is set to the information indicative of 0, 4, 8 or 16 bytes. The CPU 1 can set the values of the control registers 160 to 162, 170 to 172, 180 to 182 and 190 to 192 in accordance with the specification of the external memories 45 to 47. In addition, the CPU 1 can set the values of the control registers 160 to 162 independently from each other, the values of the control registers 170 to 172 independently from each other, the values of the control registers 180 ^• to 182 independently from each other, and the values of the control registers 190 to 192 independently from each other.

Each of the zeroth slot priority level register 200 to the seventh slot priority level register 207 is set to one of the priority level information numbers 0 to 3 as illustrated in Fig. 14. For example, the zeroth slot priority level register 200 to the seventh slot priority level register 207 are set respectively to the priority level information number 1, the priority level information number 3, the priority level information number 1, the priority level information number 2, the priority level information number 1, the priority level information number 3, the priority level information number 1, and the priority level information number 0. Incidentally, the priority level information numbers 0 to 3 are encoded into 2-bit numbers respectively. Accordingly, each of the zeroth slot priority level register 200 to the seventh slot priority level register 207 is a 2-bit register.

The CPU 1 serves to load appropriate numbers respectively to the zeroth slot priority level register 200 to the seventh slot priority level register 207 in order to set an arbitrary series of 8 numbers, which are selected respectively from among the priority level information numbers 0 to 3, constituting a cycle of 8 slots.

The multiplexer 141 selects one of the zeroth slot priority level register 200 to the seventh slot priority level register 207 in accordance with the select signal "ESSEL" input from the slot counter 147 and outputs the priority level information number stored in the priority level register as selected to the priority decoder 142.

The CPU 1 outputs the instruction fetch bus use request signal "EIFB" and the data access bus use request signal "EDAB" to the priority decoders 142 and the OR gate 210; the graphics processor 3 outputs the character header bus use request signal "ECHB", the character data bus use request signal "ECDB", and the bitmap data bus use request signal "EBMB" to the priority decoders 142 and the OR gate 210; the pixel plotter 5 outputs the pixel plotter bus use request signal "EPPB" to the priority decoders 142 and the OR gate 210; the sound processor 7 outputs the wave data bus use request signal "EWAB" and the envelope data bus use request signal "EEVB" to the priority decoders 142 and the OR gate 210; and the DMA controller 9 outputs the DMA source bus use request signal "EDSB" to the priority decoders 142 and the OR gate 210. Also, the state machine 155 outputs to the priority decoder 142 the instruction fetch read acknowledge signal "EIFRG", the data access read acknowledge signal "EDARG", the data access write acknowledge signal "EDAWG", the character header read acknowledge signal "ECHRG", the character data read acknowledge signal "ECDRG", the bitmap data read acknowledge signal "EBMRG", the pixel plotter read acknowledge signal "EPPRG", the pixel plotter write acknowledge signal "EPPWG", the wave data read acknowledge signal "EWARG", the envelope data read acknowledge signal "EEVRG" and the DMA source read acknowledge signal "EDSRG" . In this description, the term "second bus use request signal SBURQ" is used to generally represent the bus use request signals "EIFB", "EDAB", "ECHB", "ECDB", "EBMB", "EPPB", "EWAB", "EEVB" and "EDSB".

The priority decoder 142 serves to decode the priority level information number currently input from the multiplexer 141, and select a bus master (to which the bus ownership of the second bus 33 is to be granted) having the highest priority from among the bus masters outputting the second bus use request signal "SBURQ", except for the bus master which is currently using the second bus 33, on the basis of the priority level information set corresponding to the priority level information number. More specific description is as follows.

The priority decoder 142 selects, in accordance with the priority level information set corresponding to the priority level information number as decoded, a second bus use request purpose having the highest priority from among the second bus use request purposes corresponding to the second bus use request signals "SBURQ", which are asserted, except for the second bus use request purpose for which the second bus 33 is currently used. The second bus use request purpose for which the second bus is currently used can be determined on the basis of the states of the second bus use acknowledge signals "SAGR" output from the state machine 155.

Meanwhile, the second bus use acknowledge signal "SAGR" is used to generally represent the instruction fetch read acknowledge signal "EIFRG", the data access read acknowledge signal "EDARG", the data access write acknowledge signal "EDAWG", the character header read acknowledge signal "ECHRG", the character data read acknowledge signal "ECDRG", the bitmap data read acknowledge signal . "EBMRG", the pixel plotter read acknowledge signal "EPPRG", the pixel plotter write acknowledge signal "EPPWG", the wave data read acknowledge signal "EWARG", the envelope data read acknowledge signal "EEVRG" and the DMA source read acknowledge signal "EDSRG" .

Also, the priority decoder 142 generates a bus master select signal "EBMSL [8 : 0] " on the basis of the second bus use request purpose as selected, and outputs it to the state machine 155 and the multiplexers 143 to 146. The respective bits of the bus master select signal "EBMSL[8: O]" correspond respectively to the nine second bus use request purposes. The priority decoder 142 sets the bit of the bus master select signal "BMSEL[8: O]" corresponding to the selected second bus use request purpose (to which the bus ownership of the second bus 33 is to be granted) to "1", and sets the remaining bits to "0". In other words, in accordance with the priority level information set corresponding to the priority level information number as decoded, the priority decoder 142 sets to "1" the bit corresponding to a second bus use request purpose having the highest priority from among the second bus use request purposes corresponding to the second bus use request signals "SBURQ", which are asserted, except for the second bus use request purpose for which the second bus 33 is currently used.

The state machine 155 outputs to the OR gate 148 the eleven second bus use acknowledge signals "SAGR" (EIFRG, EDARG, EDAWG, ECHRG, ECDRG, EBMRG, EPPRG, EPPWG, EWARG, EEVRG and EDSRG) .

The slot counter 147 increments the value of the select signal "ESSEL [2: 0]" every time the signal input from the OR gate 148 rises from "0" (false) to "1" (true) in order to output the select signal "ESSEL [2: O]" with which the multiplexer 141 sequentially and cyclically selects one of the priority level information numbers stored in the zeroth slot priority level register 200 to the seventh slot priority level register 207. Accordingly, it is possible to detect the end of one or more bus cycles of the bus master, to which bus ownership is granted, on the basis of the logical OR of the eleven second bus use acknowledge signals "SAGR".

While the nine second bus use request signal "SBURQ" is input to the OR gate 210, the second bus use request signal "SBR" is asserted if at least one of the nine second bus use request signal "SBURQ" is "1".

The nine signals input to each of the multiplexers 143 to 146 correspond respectively to the nine second bus use request purposes, i.e., "instruction fetch", "data access", !'character header", "character data", "bitmap data", "pixel plotter", "wave data", "envelope data" and "DMA source".

Accordingly, the multiplexer 143 receives, at its nine input terminals, the instruction fetch address "IFA", the data access address "EDAA", the character header address "ECHA", the character data address "ECDA", the bitmap data address "EBMA", the pixel plotter address "EPPA", the wave data address "EWAA", the envelope data address "EEVA" and the DMA source address "EDSA".

The multiplexer 143 outputs to the register 230 an address signal corresponding to the second bus use request purpose (to which the bus ownership of the second bus 33 is to be granted) selected from among these nine input address signals by the bus master select signal "EBMSL".

The register 230 latches the address signal as input and outputs it as the unified address "CADR[26:0] " . In this case, while the unified address "CADR[26:13" is output to the state machine 155, the remaining least significant bit "CADR[O]" is output to the byte enable signal generation circuit 150. In addition, the unified address "CADR[22:21] " is output also to the address decoder 149.

The address decoder 149 decodes the unified address "CADR[22:21] " to generate a unified first area select signal "CASELl" and a unified second area select signal "CASEL2" which are output to the multiplexers 151 to 153, the decoder 154 and the state machine 155. This will be further explained below with reference to Fig. 7.

As shown at the bottom of Fig. 7, the second bus zeroth area is designated when the address "A22" (the unified address "CADR[22]") is "0"; the second bus first area is designated when the address "A22" (the unified address "CADR[22]") is "1" and the address "A21" (the unified address "CADR[21]") is "0"; and the second bus second area is designated when the address "A22" (the unified address "CADR[22] ") is "1" and the address "A21" (the unified address "CADR[21]") is "1". Accordingly, the address decoder 149 can determine which area is selected from among the second bus zeroth area, the second bus first area and the second bus second area by decoding the unified address "CADR[22:21] ".

Then, when the unified address CADR[22:21] designates the second bus zeroth area, the address decoder 149 negates both the unified first area select signal "CASELl" and the unified second area select signal "CASEL2"; when the unified address CADR[22:21] designates the second bus first area, the address decoder 149 asserts the unified first area select signal "CASELl" and negates the unified second area select signal "CASEL2"; and when the unified address CADR[22:21] • designates the second bus second area, the address decoder 149 negates the unified first area select signal "CASELl" and asserts the unified second area select signal "CASEL2".

Returning to Fig. 20, the multiplexer 151 selects one of the three bus width registers 160 to 162 in accordance with the unified first area select signal "CASELl" and the unified second area select signal "CASEL2", and outputs the value of the selected bus width register to the state machine 155 as a unified bus width signal "CBW".

In other words, the multiplexer- 151 outputs, as the unified bus width signal "CBW", the value of the bus width register corresponding to the area which is one of the second bus zeroth area, the second bus first area and the second bus second area as designated by the unified address signal "CADR".

The multiplexer 152 selects one of the three random access cycle number registers 170 to 172 in accordance with the unified first area select signal "CASELl" and the unified second area select signal "CASEL2", and outputs the value of the random access cycle number register as selected to the state machine 155 as a unified random access cycle number signal "CRCY". In other words, the multiplexer 152 outputs, as the unified random access cycle number signal "CRCY", the value of the random access cycle number register corresponding to the area selected by the unified address signal "CADR" from among the second bus zeroth area, the second bus first area and the second bus second area. The multiplexer 153 selects one of the three page access cycle number registers 180 to 182 in accordance with the unified first area select signal "CASELl" and the unified second area select signal "CASEL2", and outputs the value of the selected page access cycle number register to the state machine 155 as a unified page access cycle number signal "CPCY".

In other words, the multiplexer 153 outputs, as the unified page access cycle number signal "CPCY", the value of the page access cycle number register corresponding to the area selected by the unified address signal "CADR" from among the second bus zeroth area, the second bus first area and the second bus second area.

The decoder 154 selects one of the three page size registers 190 to 192 in accordance with the unified first area select signal "CASELl" and the unified second area select signal "CASEL2", and decodes the value of the page size register as selected. In other words, the decoder 154 decodes the value of the page • size register corresponding to the area selected by the unified address signal "CADR" from among the second bus zeroth area, the second bus first area and the second bus second area.

Then, the decoder 154 outputs the result of decoding to the state machine 155 as a unified page boundary signal "CPB". Each of the page size registers 190 to 192 is a 2-bit register capable of designating one of the page sizes of 0, 4, 8 and 16 bytes. The decoder 154 decodes this 2-bit signal and generates the unified page boundary signal "CPB[3: 0]" serving as a mask of the second bus address "EAD[3: O]".

The multiplexer 144 receives, at the nine input terminals, the instruction fetch size signal "EIFS", the data access size signal "EDAS" which is fixedly set to "1", the character header size signal "ECHS", the character data size signal "ECDS", the bitmap data size signal "EBMS" which is fixedly set to "8", the pixel plotter size signal "EPPS", the wave data size signal "EWAS" which is fixedly set to "1", the envelope data size signal "EEVS" which is fixedly set to "1", and the DMA source size signal "EDSS".

Namely, the data access size signal "EDAS", the wave data size signal "EWAS" and the envelope data size EEVS as input are fixedly set to "1" respectively. This is because the data transmission size, which can be requested, is fixed to one byte for these respective second bus use request purposes as shown in Fig. 19. The "1" as input to the multiplexer 144 means that the data transmission size as requested is one byte. Also, the bitmap data size signal "EBMS" as input is fixedly set to "8" (refer to Fig. 19) .

The multiplexer 144 outputs to the register 231 a size signal corresponding to the second bus use request purpose (to which the bus ownership of the second bus 33 is to be granted) selected from among these nine input size signals by the bus master select signal "EBMSL".

The register 231 latches the size signal as input, and outputs it to the state machine 155 as the unified size signal "CSZ".

The multiplexer 145 receives, at the nine input terminals, a value of "0" corresponding to the second bus use request purpose of "instruction fetch", the data access write data "EDAW", a value of "0" corresponding to the second bus use request purpose of "character header", a value of "0" corresponding to the second bus use request purpose of "character data", a value of "0" corresponding to the second bus use request purpose of "bitmap data", the pixel plotter write data "EPPW", a value of "0" corresponding to the second bus use

■ request purpose of "wave data", a value of "0" corresponding to the second bus use request purpose of "envelope data", and a value of "0" corresponding to the second bus use request purpose of "DMA source".

In this case, the input value of "0" means that there is no data to be written. This is because write operation is not performed for these second bus use request purposes, i.e., "instruction fetch",

"character header", "bitmap data", "wave data", "envelope data" and

"DMA source".

The multiplexer 145 outputs to the register 232 input data corresponding to the second bus use request purpose (to which the bus ownership of the second bus 33 is to be granted) selected from among these nine input write values of the input data by the bus master select signal "EBMSL".

The register 232 latches the write data as input, and outputs it to the state machine 155 as the unified write data "CWD".

The multiplexer 146 receives, at the nine input terminals, a value of "0" corresponding to the second bus use request purpose of

"instruction fetch", the data access write request signal "EDAWR", a value of "0" corresponding to the second bus use request purpose of "character header", a value of "0" corresponding to the second bus use request purpose of "character data", a value of "0" corresponding to the second bus use request purpose of "bitmap data", the pixel plotter write request signal "EPPWR", a value of "0" corresponding to the second bus use request purpose of "wave data", a value of "0" corresponding to the second bus use request purpose of "envelope data", and a value of "0" corresponding to the second bus use request purpose of "DMA source".

In this case, the input value of "0" means that there is no write request. This is because write operation is not performed for these second bus use request purposes, i.e., "instruction fetch", "character header", "character data", "bitmap data", "wave data", "envelope data" and "DMA source".

The multiplexer 145 outputs to the register 233 an input signal corresponding to the second bus use request purpose (to which the bus ownership of the second bus 33 is to be granted) selected from among these nine input signals by the bus master select signal "EBMSL" .

The register 233 latches the signal as input, and outputs it to the state machine 155 as the unified write request .signal "CWRQ".

The byte enable signal generation circuit 150 generates a unified lower byte enable signal "CLWBE" and a unified upper byte ■ enable signal "CUPBE" in accordance with the unified address "CADR[O]", the unified bus width signal "CBW" and the unified write request signal "CWRQ", and outputs them to the state machine 155. More specific description is as follows. At first, the explanation will be given in the case where the unified write request signal "CWRQ" is "0" (read operation) . When the unified bus width signal "CBW" designates a data bus width of 16 bits, the byte enable signal generation circuit 150 asserts the unified lower byte enable signal "CLWBE" and the unified upper byte enable signal "CUPBE" irrespective of the value of the unified address "CADR[O] ".

On the other hand, when the unified bus width signal "CBW" designates a data bus width of 8 bits, the byte enable signal generation circuit 150 asserts the unified lower byte enable signal "CLWBE" and negates the unified upper byte enable signal "CUPBE" in the case where the unified address "CADR[O]" is "0", and negates the unified lower byte enable signal "CLWBE" and asserts the unified upper byte enable signal "CUPBE" in the case where the unified address "CADR[O]" is "1". As has been discussed above, the read operation is performed in units of 16 bits in the^' area where the bus width is set to 16 bits, and performed in units of 8 bits in the area where the bus width is set to 8 bits.

Next, the explanation will be given in the case where the unified write request signal "CWRQ" is "1" (write operation) . Irrespective of the value of the unified bus width signal "CBW", the byte enable signal generation circuit 150 asserts the unified lower byte enable signal "CLWBE" and negates the unified upper byte enable signal "CUPBE" in the case where the unified address "CADR[O]"^' is "0", and negates the unified lower byte enable signal "CLWBE" and asserts the unified upper byte enable signal "CUPBE" in the case where the unified address "CADR[O]" is "1".

As has been discussed above, the write operation is performed always in units of 8 bits in both the area where the bus width is set to 16 bits and the area where the bus width is set to 8 bits.

The state machine 155 defines a plurality of states IDLE, FREE, WRITE, READ and STEAL with regard to the access to the second bus 33, controls the second bus address "EAD", the second bus address output enable signal "EADOE", the external data output "EDAO", the external data output enable signal "EDAOE", the external read enable signal "ERDE", the external write enable signal "EWRE", the lower byte enable signal "LWBE", the upper byte enable signal "UPBE" and the first area select signal "ASSELl", the second area select signal "ASSEL2", and also controls the instruction fetch upper byte read acknowledge signal "EIFUR", the instruction fetch lower byte read acknowledge signal "EIFLR", the data access lower byte read acknowledge signal "EDALR", the data access upper byte read acknowledge signal "EDAUR", the data access write acknowledge signal "EDAWG", the character header lower byte read acknowledge signal "ECHLR", the character header upper byte read acknowledge signal "ECHUR", the character data lower byte read acknowledge signal "ECDLR", the character data upper byte read acknowledge signal "ECDUR", the bitmap data lower byte read acknowledge signal "EBMLR", the bitmap data upper byte read acknowledge signal "EBMUR", the pixel plotter lower byte read acknowledge signal "EPPLR", the pixel plotter upper byte read acknowledge signal "EPPUR", the pixel plotter write acknowledge signal "EPPWG", the wave data lower byte read acknowledge signal "EWALR", the wave data upper byte read acknowledge signal "EWAUR", the envelope data lower byte read acknowledge signal "EEVLR", the envelope data upper byte read acknowledge signal "EEVUR", the DMA source lower byte read acknowledge signal "EDSLR", the DMA source upper byte read acknowledge signal "EDSUR", the instruction fetch read acknowledge signal "EIFRG", the data access read acknowledge signal "EDARG", the character header read acknowledge signal "ECHRG", the character data read acknowledge signal "ECDRG", the bitmap data read acknowledge signal "EBMRG", the pixel plotter read acknowledge signal "EPPRG", the wave data read acknowledge signal "EWARG", the envelope data read acknowledge signal "EEVRG" and the DMA source read acknowledge signal "EDSRG". Fig. 21 is a view for explaining the state transition of the state machine 155 shown in Fig. 20. As shown in Fig. 21, the IDLE state STO is a state in which there is no use request for the second bus 33. In the FREE state STl, the state machine 155 accepts a request for releasing the external bus 43 from the CPU 1 (the external bus release request register 156 is set to "1") and puts the second bus address "EAD", the external data output "EDAO", the external read enable signal "ERDE", the external write enable signal "EWRE", the lower byte enable signal "LWBE", the upper byte enable signal "UPBE", the first area select signal "ASSELl" and the second area select signal "ASSEL2" respectively in a Hi-Z (high impedance) state. The WRITE state ST2 is taken for write cycles. The write cycle can be repeatedly performed for writing multiple bytes.

The READ state ST3 is taken for read cycles. The read cycle can be repeatedly performed for reading multiple bytes. However, if the sound processor 7 issues a read request after a multiple byte read operation is granted, the state machine 155 changes its state to the STEAL state ST4 such that the multiple byte read operation is interrupted by the sound processor 7 for its read operation.

The STEAL state ST4 is provided for permitting the interrupt by the sound processor 7 during the read operation by another bus master, because the bus use request issued by the sound processor 7 assumes an overriding urgency.

With reference to the figure, the state transition will be explained. Meanwhile, in the figure, the symbol " Λ " means a logical AND; " v " means a logical OR; "<" is a less than sign; " ≥ " is a greater than/equal sign; and "=" is an equal sign.

In the case of the present invention, if a conditional expression in the figure is satisfied, the state transition corresponding to the satisfied conditional expression takes place on the subsequent rising edge of the internal clock signal "ICLK". At first, the state transition from the IDLE state STO will be explained .

When the external bus release request register 156 takes a value of "1", then the state machine 155 changes its state to the FREE state STl. On the other hand, when the external bus release request register 156 takes a value of "0", when the second bus use request signal "SBR" takes a value of "1" and when the unified write request signal "CWRQ" takes a value of "1", then the state machine 155 changes its state to the WRITE state ST2. Furthermore, when the external bus release request register 156 takes a value of "0", when the second bus use request signal "SBR" takes a value of "1" and when the unified write request signal "CWRQ" takes a value of "0", then the state machine 155 changes its state to the READ state ST3. Incidentally, it means a read request if the second bus use request signal "SBR" takes a value of "1" and the unified write request signal "CWRQ" takes a value of "0".

On the other hand, when the external bus release request register 156 takes a value of "0" and when the second bus use request signal "SBR" takes a value of "0", then the state machine 155 changes its state to the same IDLE state STO.

Next, the state transition from the FREE state STl will be explained.

^* When a cycle count "CYC" of a cycle counter is "1" and the external bus release request register 156 takes a value of "0", then the state machine 155 changes its state to the IDLE state STO.

In this case, the cycle counter is a 3-bit counter. The initial value of the cycle count "CYC" in the FREE state STl is "0", i.e., "ObOOO" which is decremented by one for every one cycle of the internal clock signal "ICLK". "ObOOO" as the initial value of the cycle counter "CYC" means 8 cycles of the internal clock signal "ICLK". Next, the transition from the WRITE state ST2 will be explained. When the cycle count "CYC" takes a value of "1", when a byte count "BYC" takes a value smaller than "2", when the external bus release request register 156 takes a value of "0", and when the second bus use request signal "SBR" takes a value of "0", then the state machine 155 changes its state to the IDLE state STO.

In this case, the initial value of the cycle count "CYC" in the

WRITE state ST2 is the random access cycle number corresponding to the unified random access cycle number signal "CRCY". Also, the initial value of the byte count "BYC" in the WRITE state ST2 (refer to Fig. 19) is the size corresponding to the unified size signal "CSZ" which is decremented by one every time a 1-byte write operation is completed.

Furthermore, when the cycle count "CYC" takes a value of "1", when the byte count "BYC" is smaller than "2", and when the external bus release request register 156 takes a value of "1", the state machine 155 changes its state to the FREE state STl.

Still further, when the cycle count "CYC" takes a value of "1", when the byte count "BYC" is smaller than "2", when the external bus release request register 156 takes a value of "0", when the second bus use request signal "SBR" takes a value of "1", and when the unified write request signal "CWRQ" takes a value of "1", then the state machine 155 changes its state to the same WRITE state ST2.

Still further, when the cycle count "CYC" takes a value of "1", when the byte count "BYC" is smaller than "2", when the external bus release request register 156 takes a value of "0", when the second bus use request signal "SBR" takes a value of "1", and when the unified write request signal "CWRQ" takes a value of "0", then the state machine 155 changes its state to the READ state ST3.

Next, the state transition from the READ state ST3 will be explained.

When the cycle count "CYC" takes a value of "1", when the condition 1 as described in Fig. 21 is false, when the external bus release request register 156 takes a value of "0", and when the second bus use request signal "SBR" takes a value of "0", then the state machine 155 changes its state to the IDLE state STO.

In this case, the initial value of the cycle count "CYC" in the READ state ST3 is the random access cycle number corresponding to the unified random access cycle number signal "CRCY" or the page access cycle number corresponding to the unified page access cycle number signal "CPCY".

The condition 1 is the logical OR of the following three Boolean expressions corresponding to the condition that the second bus width signal "SBW" takes a value of "1", that the second bus address "EAD[O]" takes a value of "0" and that the byte count "BYC" is no smaller than 3, the condition that the second bus width signal "SBW" takes a value of "1", that the second bus address "EAD[O]" takes a value of "1" and that the byte count "BYC" is no smaller than 2, and the condition that the second bus width signal "SBW" takes a value of "0" and that the byte count "BYC" is no smaller than 2. When the second bus width signal "SBW" takes a value of "0" the bus width as required is^' 8 bits, and when the second bus width signal "SBW" takes a value of "1" the bus width as required is 16 bits. On the other hand, the initial value of the byte count "BYC" in the READ state ST3 is the size corresponding to the unified size signal "CSZ" (refer to Fig. 19) , while the byte count "BYC" is decremented by one every time one byte read operation is completed. Also, when the second bus address "EAD[O]" takes a value of "0" the lower byte of a 16-bit data is designated, and when the second bus address "EAD[O]" takes a value of "1" the upper byte of a 16-bit data is designated. Accordingly, if the condition 1 is true, it is meant that when the bus width as required is 16 bits, since there are three or more remaining bytes to be read including the lower byte which is designated by the current second bus address "EAD[O]", all the remaining bytes cannot be read by one bus cycle, that when the bus width as required is 16 bits, since there are two or more remaining bytes to be read including the upper byte which is designated by the current second bus address "EAD[O]", all the remaining bytes cannot be read by one bus cycle, or that when the bus width as required is 8 bits, since there are two or more remaining bytes to be read, all the remaining bytes cannot be read by one bus cycle.

Conversely, if the condition 1 is false, it is meant that when the bus width as required is 16 bits, since there are not more than two remaining bytes to be read including the lower byte which is designated by the current second bus address "EAD[O]", all the remaining bytes can be read by one bus cycle, that when the bus width as required is 16 bits, since there is only one remaining byte to be read, i.e., the upper byte which is designated by the current second bus address "EAD[O]", the remaining byte can be read together by one bus cycle, or that when the bus width as required is 8 bits, since there is only one byte to be read, this byte can be read by one bus cycle.

By the way, when the cycle count "CYC" takes a value of "1", when the condition 1 is false, and when the external bus release request register 156 takes a value of "1", then the state machine 155 changes its state to the FREE state STl.

On the other hand, when the cycle count "CYC" takes a value of "1", when the condition 1 is false, when the external bus release request register 156 takes a value of "0", when the second bus use request signal "SBR" takes a value of "1", and when the unified write request signal "CWRQ" takes a value of "1", then the state machine 155 changes its state to the WRITE state ST2.

Furthermore, when the cycle count "CYC" takes a value of "1", when the condition 1 is false, when the external bus release request register 156 takes a value of "0", when the second bus use request signal "SBR" takes a value of "1", and when the unified write request signal "CWRQ" takes a value of "0", then the state machine 155 changes its state to the same the READ state ST3.

Still further, when the cycle count "CYC" takes a value of "1", when the condition 1 is true, and when the condition 2 also described in Fig. 21 is true, the state machine 155 changes its state to the STEAL state ST4.

In this case, the condition 2 is a condition that is true when the wave data bus use request signal "EWAB" takes a value of "1" or when the envelope data bus use request signal "EEVB" takes a value of "1".

Accordingly, even during the read operation by a bus master other than the sound processor 7, when the sound processor 7 outputs a wave data bus use request signal "EWAB" or an envelope data bus use request signal "EEVB", the state machine 155 changes its state to the STEAL state ST4 such that the read operation is interrupted by the sound processor 7 for its read operation if the cycle count "CYC" takes a value of "1". However, the state transition to the STEAL state

ST4 requires the condition 1 to be true, and therefore it is required that all the remaining read data cannot be read in one bus cycle. In other words, if the condition 1 is false, i.e., if all the remaining read data can be read in one. bus cycle, the READ state ST3 is maintained in order to finish the read operation by the bus master.

Next, the state transition from the STEAL state ST4 will be explained. When the cycle count "CYC" takes a value of "1", the state machine 155 changes its state to the READ state ST3.

Next, the state transition as illustrated in Fig. 21 will be explained in detail on the basis of the description of the state machine 155 by the use of an HDL (hardware description language) . In this case, the following conditions are assumed. The logic reflects changes on the subsequent rising edge of the internal clock signal "ICLK" as described above. The logic is described basically in positive logic. However, the unified lower byte enable signal "CLWBE", the unified upper byte enable signal "CUPBE", the upper byte enable signal "UPBE", and the lower byte enable signal "LWBE" are negative logic. Also, while the symbol "=" means an equal sign in conditional statements, the same symbol means assignment in other statements.

Furthermore, the following description includes a write acknowledge signal "WRAC", a write data latch value "WDSV", a random access cycle number latch value "RACSV", a second bus address latch value "EADSV", a first area select signal latch value "FSSV", a second area select signal latch value "SSSV", the second bus width signal "SBW", a second bus width latch value "SBWSV", a read acknowledge signal "REGR", a read acknowledge latch value "REGRSV", a page access cycle number latch value "PACSV", a lower byte read acknowledge signal "LWRG", and an upper byte read acknowledge signal "UPRG", which are not illustrated in Fig. 20 because these signals are internal signals of the state machine 155. [IDLE state STO] The state machine 155 operates in order that the second address output enable signal "EADOE" = 1, that the external data output enable signal "EDAOE" = 0 (that is, the data bus of the second bus 33 is put in an Hi-Z state) , that the external write enable, signal "EWRE" = 0, and that the external read enable signal "ERDE" = 0. If the external bus release request register 156 = 1, the FREE

■ common logic to be described below is executed; else if the second bus use request signal "SBR" = 1, the ACCESS common logic to be described below is executed; or else the IDLE common logic to be described below is executed. [FREE State STl]

(1) <In the case where the cycle count "CYC" ≠ 1>

The cycle count "CYC" is decremented by one.

(2) <In the case where it is not true cycle count "CYC" ≠ 1, i.e., the cycle count "CYC" = 1> The state machine 155 operates in order that the second bus address output enable signal "EADOE" = 0.

If the external bus release request register 156 = 0, the state machine 155 operates in order that the second bus address output enable signal EADOE = 1 and changes its state to the IDLE state STO. [WRITE state ST2]

(1) <In the case where the cycle count "CYC" ≠ 1>

(1-1) The state machine 155 operates in order that the write acknowledge signal "WRAC[8:O]" = ObOOOOOOOOO, that the external write enable signal "EWRE" = 1, and that the external data output enable signal "EDAOE" = 1. Incidentally, the right acknowledge signal "WRAC[8:O]" is negated^' because the data write operation to the external memories 45 to 47 has not been completed yet in a halfway bus cycle.

(1-2) If the second bus address "EAD[O]" = 1, the state machine 155 operates in order that the external data "EDAO[15:8]" = the write data latch value "WDSV[15:8] " and the external data "EDAO[7:0]" = the write data latch value "WDSV[15:8] ". Because the write operation to the external memories 45 to 47 is performed in units of bytes, the external data "EDAO[15:8]" is written in the case where the data bus width is 16 bits, and the external data "EDAO[7: O]" is written in the case where the data bus width is 8 bits.

On the other hand, in the case where it is not true that the second bus address "EAD[O]" = 1, i.e., the second bus address "EAD[O]" = 0, the state machine 155 operates in order that the external data "EDAO[15: O]" = the write data latch value "WDSV[15:0] ". Because the write operation is performed in units of bytes, the external data "EDAO[7:O]" is written to the external memories 45 to 47. (1-3) The cycle count "CYC" is decremented by one.

(2) <In the case where it is not true that the cycle count "CYC" ≠ 1, i.e., the cycle count "CYC" = 1 and where the byte count "BYC" > 2>

The state machine 155 operates in order that the write acknowledge signal "WRAC[8:O]" = ObOOOOOOOOO, that the external write enable signal "EWRE" = 0, that the external data output enable signal "EDAOE" = 0, that the cycle count "CYC" = the random access cycle number latch value RACSV, that the second bus address "EAD[26:0]" = the second bus address "EAD[26:0]" + 1, and that the upper byte enable signal "UPBE" = ^' the logical inversion of the second bus address "EAD[O]". Meanwhile, the byte count "BYC" is decremented by one. Incidentally, the right acknowledge signal "WRAC[8:0]" is negated because there is remaining data to be written.

(3) <In the case where it is not true that the cycle count "CYC" ≠ 1, i.e., the cycle count "CYC" = 1 and where it is not true that the byte count "BYC" > 2, i.e., the byte count "BYC" = 1 >

The state machine 155 operates in order that the external write enable signal "EWRE" = 0, and that the external data output enable signal "EDAOE" = 0. If the external bus release request register 156 =

1, the FREE common logic to be described below is executed; else if the second bus use request signal "SBR" = 1, the ACCESS common logic to be described below is executed; or else the IDLE common logic to be described below is executed. [READ state ST3]

(1) The state machine 155 operates in order that the external write enable signal "EWRE" = 0, and that the external data output enable signal "EDAOE" = 0. (2) <In the case where the cycle count "CYC" ≠ 1>

The state machine 155 operates in order that the cycle count "CYC" is decremented by one and that the external read enable signal "ERDE" = 1. (3) <In the case where it is not true that the cycle count "CYC" ≠ 1, i.e., the cycle count "CYC" = 1 and the condition 1 of Fig. 21 is true> (3-1) <In the case where the condition 2 of Fig. 21 is true>

(3-1-1) The state machine 155 operates in order that the external read enable signal "ERDE" = 0. (3-1-2) If the second bus width signal "SBW" = 1 and the second bus address "EAD[O]" = 0 and byte count "BYC" > 3, then the state machine 155 operates in order that the byte count "BYC" is decremented by two and the second bus address latch value "EADSV[26: 0] " = the second bus address "EAD[26:0]" + 2. On the other hand, in the other cases as already mentioned, if the byte count "BYC" > 2, the state • machine 155 operates in order that the byte count "BYC" is decremented by one and that the second bus address latch value "EADSV[26: 0] " = the second bus address "EAD[26: O]" + 1.

(3-1-3) The state machine 155 operates in order that the second bus address "EAD[26: I]" = the unified address "CADR[26: 1] ", that the second bus address "EAD[O]" = the unified lower byte enable signal "CLWBE", that the first area select signal "ASSELl" = the unified first area select signal "CASELl", that the second area select signal "ASSEL2" = the unified second area select signal "CASEL2", that the second bus width latch value SBWSV = the second bus width signal "SBW", that the second bus width signal "SBW" = the unified bus width signal "CBW", that the upper byte enable signal "UPBE" = the unified upper byte enable signal "CUPBE", that the cycle count "CYC" = the unified random access cycle number signal "CRCY", that the read acknowledge latch value REGRSV = the read acknowledge signal "REGR", that the read acknowledge signal "REGR" = the bus master select signal "EBMSL", and that the state is changed to the STEAL state ST4. (3-2) <In the case where the condition 2 of Fig. 21 is false>

(3-2-1) The state machine 155 operates in order that the first area select signal "ASSELl" = the first area select latch value FSSV, and that the second area select signal "ASSEL2" = the second area select latch value SSSV.

(3-2-2) If the second bus width signal "SBW" = 1, if the second bus address "EAD[O]" = 0 and if the byte count "BYC" > 3, then the state machine 155 operates in order that the byte count "BYC" is decremented by two and that the second bus address "EAD[26:0]" = the second bus address "EAD[26:0]" + 2. On the other hand, in the cases other than mentioned, if the byte count "BYC" > 2, the state machine 155 operates in order that the byte count "BYC" is decremented by one and that the second bus address "EAD[26:0]" = the second bus address "EAD[26: O]" + 1.

(3-2-3) In the case where the second bus width signal "SBW" = 1, the state machine 155 operates in order that the upper byte enable signal "UPBE" = 0, and otherwise, i.e., in the case where the second bus width signal "SBW" = 0, the state machine 155 operates in order that the upper byte enable signal "UPBE" = the logical inversion of the second bus address "EAD[O]". (3-2-4) <In the case where the second bus width signal "SBW" = 1>

If the logical OR of the respective bits of the second bus address "EAD[3: I]" and the respective bits of the unified page boundary signal "CPB[3:l]^π is not "Oblll", the state machine 155 operates in order that the cycle count "CYC" = the unified page access cycle number signal "CPCY" and that the external read enable signal "ERDE" = 1. On the other hand, if the logical OR of the respective bits of the second bus address "EAD[3:1]^M and the respective bits of the unified page boundary signal "CPB[3: I]" is "Oblll", the state machine 155 operates in order that the cycle count "CYC" = the random access cycle number latch value RACSV and that the external read enable signal "ERDE" = 0. This will be explained in detail below. In the case of the present embodiment, for example, the decoder 154 outputs, as the page boundary signal "CPB", "Obllll" for a page size of 0 byte, "ObIlOO" for a page size of 4 bytes, "ObIOOO" for a page size of 8 bytes, and "ObOOOO" for a page size of 16 bytes.

In this case, the second bus width signal "SBW" = 1 means the data bus width of the second bus 33 is 16 bits, that is, one word of the external memories 45 to 47 consists of 16 bits. In such a case, when the second bus address "EAD" is updated to designate the next word, the second bus address "EAD[O]" is not changed with a value of "0" while the second bus address "EAD[26:1]^?I is incremented by one. With this fact in mind, it is assumed for explanation that "ObIlOO" (indicative of ^' 4 bytes) is assigned to the page boundary signal "CPB[3: 0]". In this case, because the page size is 4 bytes, there are different second bus addresses "EAD[3:1]" in the same page, for example, "ObOOO" and "ObOOl". In other words, in the case where one page consists of 4 bytes, the second bus address "EAD[I]" is incremented within the same page as "ObO" "ObI".

Accordingly, the second bus address "EAD[I]" indicates "ObI" to point to the last word of a 4 byte page. Therefore, the logical OR of the respective bits of the page boundary signal "CPB[3:1]" (ObIlO) and the respective bits of the second bus address "EAD[3: I]" (0b**l) pointing to. the last word in the page is necessarily "Oblll". In this manner, it is judged whether or not the word pointed to by the second bus address "EAD" is the last word of a page. Incidentally, "*" is used to be replaced by an arbitrary binary value. (3-2-5) <In the case where the second bus width signal "SBW" = 0>

If the logical OR of the respective bits of the second bus address "EAD[3: 0]" and the respective bits of the unified page boundary signal "CPB[3: O]" is not "Obllll", the. state machine 155 operates in order that the cycle count "CYC" = the unified page access cycle number signal "CPCY" and that the external read enable signal

• "ERDE" = 1. On the other hand, if the logical OR of the respective bits of the second bus address "EAD[3:0]" and the respective bits of the unified page boundary signal "CPB[3:0]" is "Obllll", the state machine 155 operates in order that the cycle count "CYC" = the random access cycle number latch value RACSV and that the external read enable signal "ERDE" = 0. This point will be explained in detail below.

In this case, the second bus width signal "SBW" = 0 means the data bus width of the second bus 33 is 8 bits, that is, one word of the external memories 45 to 47 consists of 8 bits. In such a case, when the second bus address "EAD" is updated to designate the next word, the second bus address "EAD[26:0]" is incremented by one.

With this fact in mind, it is assumed for explanation that "ObIlOO" (indicative of 4 bytes) is assigned to the page boundary signal "CPB[3:0]". In this case, because the page size is 4 bytes, there are different second bus addresses "EAD[3:0]^?I in the same page, for example, "ObOOOO", "ObOOOl", "ObOOlO" and "ObOOIl". In other words, in the case where one page consists of 4 bytes, the second bus address "EAD[IrO]" is incremented within the same page as "ObOO" "ObOl "ObIO "ObIl". Accordingly, the second bus address "EAD[IrO]" indicates "ObIl" to point to the last word of a 4 byte page. Therefore, the logical OR of the respective bits of the page boundary signal "CPB[3: O]" (ObIlOO) and the respective bits of the second bus address "EAD[3:O]" (0b**ll) pointing to the last word in the page is necessarily "Obllll". In this manner, it is judged whether or not the word pointed to by the second bus address "EAD" is the last word of a page. Incidentally, "*" is used to be replaced by an arbitrary binary value.

(4) <In the case where it is not true that the cycle count "CYC" ≠ 1 in the READ state ST3, i.e., the cycle count "CYC" = 1 and the condition 1 of Fig. 21 is false>

The state machine 155 operates in order that the external read enable signal ERDE = 0. If the external bus release request register 156 = 1, the FREE common logic to be described below is executed; else if the second bus use request signal "SBR" = 1, the ACCESS common logic to be described below is executed; or else the IDLE common logic to be described below is executed. [STEAL State ST4]

(1) <In the case where the cycle count "CYC" ≠ 1> .

The state machine 155 operates in order that the external read enable signal "ERDE" = 1 and that the cycle count "CYC" is decremented by one.

(2) <In the case where it is not true that the cycle count "CYC" ≠ 1, i.e., the cycle count "CYC" = 1>

(2-1) The state machine 155 operates in order that the external read enable signal "ERDE" = 0, that the second bus address "EAD[26:0]^?I = the second bus address latch value "EADSV[26: 0] ", that the first area select signal "ASSELl" = the first area select signal latch value FSSV, that the second area select signal "ASSEL2" = the second area select signal latch value SSSV, and that the second bus width signal "SBW" = the second bus width latch value SBWSV.

(2-2) If the second bus width latch value SBWSV = 1, the state machine 155 operates in order that the upper byte enable signal "UPBE" = 0, otherwise (i.e., if the second bus width latch value SBWSV = 0) the state machine 155 operates in order that the upper byte enable signal "UPBE" = the logical inversion of the second bus address latch value "EADSV[O] ".

(2-3) The state machine 155 operates in order that the cycle count "CYC" = the random access cycle number latch value "RACSV[2: 0] ", that the read acknowledge signal "REGR[8:0]" = the read acknowledge latch value "REGRSV[8: 0] ", and that the state is changed to the READ state ST3 .

[IDLE Common Logic]

The state machine 155 operates in order that the read acknowledge signal "REGR[8:0]" = 0 , and that the state is changed to the IDLE state STO. [FREE Common Logic]

The state machine 155 operates in order that the second bus address "EAD[26: O]" = 0x4000000, that the upper byte enable signal "UPBE" = 1, that the first area select signal "ASSELl" = 0, that the second area select signal "ASSEL2" = 0, that the cycle count "CYC" = 0, and that the state is changed to the FREE state STl.

In this case, "0x4000000" is the address which is not accessed for neither read nor write operations. In this case, the cycle count "CYC" is "0" which means one bus cycle is an 8-clock cycle. Incidentally, the lower byte enable signal "LWBE" is controlled in the same behavior as the second bus address "EAD[O]". [ACCESS Common Logic]

(1) The state machine 155 operates in order .that the second bus width signal "SBW" = the unified bus width signal "CBW", the second bus address "EAD[26:l]^π = the unified address "CADR[26: 1] ", that the

• second bus address "EAD[O]" = the unified lower byte enable signal

"CLWBE", that the upper byte enable signal "UPBE" = the unified upper byte enable signal "CUPBE", that the first area select signal "ASSELl"

= the unified first area select signal "CASELl", that the first area select latch value FSSV = the unified first area select signal "CASELl", that the second area select signal "ASSEL2" = the unified second area select signal "CASEL2", that the second area select latch value SSSV = the unified second area select signal "CASEL2", that the cycle count "CYC" = the unified random access cycle number signal "CRCY", that the random access cycle number latch value RACSV = the unified random access cycle number signal "CRCY", that page access cycle number latch value PACSV = the unified page access cycle number signal "CPCY" and the byte count "BYC" = the unified size signal "CSZ". (2) <In the case where the unified write request signal "CWRQ" = 1 > The state machine 155 operates in order that the write acknowledge signal "WRAC[8: O]" = the bus master select signal "EBMSL[8:0]'\ that the read acknowledge signal "REGR[8:0]" ObOOOOOOOOO, that the write data latch value "WDSV[15:0]" = the unified write data "CWD[15:0]", and that the state is changed to the WRITE state ST2. (3) <In the case where it is not true that the unified write request signal "CWRQ" = 1, i.e., the unified write request signal "CWRQ" = 0>

The state machine 155 operates in order that the read acknowledge signal "REGR[8:0]" = the bus master select signal "EBMSL[8:O]" and that the state is changed to the READ state ST3. [Read Acknowledge Signal Generation Logic]

(1) <In the case where cycle count "CYC" = 1>

(1-1) <In the case where the second bus width signal "SBW" = 1 (indicative of 16-bit bus width)> The state machine 155 operates in order that the lower byte read acknowledge signal "LWRG[8:0]" = the read acknowledge signal "REGR[8:0]", and that the upper byte read acknowledge signal "UPRG[8:O]" = the read acknowledge signal "REGR[8:0]". (1-2) <In the case where it is not true that the second bus width signal "SBW" = 1, i.e., the second bus width signal "SBW" = 0 (indicative of 8-bit bus width)>

If the second bus address "EAD[O]" = 0, the state machine 155 operates in order that the lower byte read .acknowledge signal "LWRG[8:O]" = the read acknowledge signal "REGR[8:0]'\ and that the upper byte read acknowledge signal "UPRG[8:0]^M = ObOOOOOOOOO.

If it is not true that the second bus address "EAD[O]" = 0, i.e., the second bus address "EAD[O]" = 1, the state machine 155 operates in order that the lower byte read acknowledge signal "LWRG[8:0]"= ObOOOOOOOOO, and that the upper byte read acknowledge signal "UPRG[8:O]" = the read acknowledge signal "REGR[8:O]".

(2) <In the case where it is not true that cycle count "CYC" = 1>

The state machine 155 operates in order that the lower byte read acknowledge signal "LWRG[8:0]" = 0b000000000, and that the upper byte read acknowledge signal "UPRG[8:0]" = 0b000000000. (3) The state machine 155 operates in order that the read acknowledge signals "REGR[O]" to "REGR[8]" are, respectively, the wave data read acknowledge signal "EWARG", the envelope data read acknowledge signal "EEVRG", the bitmap data read acknowledge signal "EBMRG", the character data read acknowledge signal "ECDRG", the character header read acknowledge signal "ECHRG", the pixel plotter read acknowledge signal "EPPRG", the DMA source read acknowledge signal "EDSRG", the data access read acknowledge signal "EDARG" and the instruction fetch read acknowledge signal "EIFRG".

(4) The state machine 155 operates in order that the lower byte read acknowledge signal "LWRG[O]" to "LWRG[8]^IT are, respectively, the wave data lower byte read acknowledge signal "EWALR", the envelope data lower byte read acknowledge signal "EEVLR", the bitmap data lower byte read acknowledge signal "EBMLR", the character data lower byte read acknowledge signal "ECDLR", the character header lower byte read acknowledge signal "ECHLR", the pixel plotter lower byte read acknowledge signal "EPPLR", the DMA source lower byte read acknowledge signal "EDSLR", the data access lower byte read acknowledge signal "EDALR" and the instruction fetch lower byte read acknowledge signal "EIFLR". (5) The state machine 155 operates in order that the upper byte read acknowledge signals "UPRG[O]" to "UPRG[8]" are, respectively, the wave data upper byte read acknowledge signal "EWAUR", the envelope data upper byte read acknowledge signal "EEVUR", the bitmap data upper byte read acknowledge signal "EBMUR", the character data upper byte read acknowledge signal "ECDUR", the character header upper byte read acknowledge signal "ECHUR", the pixel plotter upper byte read acknowledge signal "EPPUR", the DMA source upper byte read acknowledge signal "EDSUR", the data access upper byte read, acknowledge signal "EDAUR" and the instruction fetch upper byte read acknowledge signal "EIFUR" . [Write Acknowledge Signal Generation Logic]

The state machine 155 operates in order that the write acknowledge signal "WRAC[5]" is the pixel plotter write acknowledge signal "EPPWG" and that the write acknowledge "WRAC[7]" is the data access write acknowledge signal "EDAWG".

By the way, in accordance with the present embodiment as discussed above, the CPU 1, the graphics processor 3, the sound processor 7 and the DMA controller 9 of the current generation processor 100 have the same functions as the CPU 501, the graphics processor 503, the sound processor 507, and the DMA controller 509 of the previous generation processor 500 respectively. However, the graphics processor 3 provides new functions introduced in addition to the functions of the graphics processor 503.

Because of this, in the case of the current generation processor 100, the CPU 1, the graphics processor 3, the sound processor 7 and the DMA controller 9 are called a common bus master group. Furthermore, in the case of the current generation processor 100, the pixel plotter 5 is concatenated to the common bus master group to constitute a current generation bus master group. Also, in the case of the previous generation processor 500, the CPU 501, the graphics processor 503, the sound processor 507, and the DMA controller 509 are called a common bus master group.

In the case where a plurality of second bus use request purposes belong to one bus master in accordance with the priority level information set of the second bus arbiter 14 of the current generation processor 100, consecutive priority rankings are assigned to such second bus use request purposes of said one bus master. This will be explained with reference to the priority level information set corresponding to the priority level information number 0 of Fig. 14 as an example. For example, the graphics processor 3 has three second bus use request purposes, i.e., the character header "HDR", the character data "CHR", and the bitmap data "BMP", to which are respectively assigned consecutive priority rankings, i.e., the third priority level, the fourth priority level and the fifth priority level. Because of this, as seen from the software that can be run on the previous generation processor 500 (i.e., compatible software) in which bus use requests are not distinctively issued for the respective bus use request purposes, the priority level information set of the second bus arbiter 14 serves as that prepared in order to assign one priority level to each bus master.

In addition to this, the order of priority among the respective bus masters belonging to the common bus master group in accordance with the priority level information set of the second bus arbiter 14 is identical with the order of priority among the corresponding bus masters of the previous generation processor 500 in accordance with the priority level information set of the second bus arbiter 514. This will be explained with respect to the priority level information set corresponding to the priority level information number 0 of Fig. 12 and the priority level information set corresponding to the priority level information number 0 of Fig. 14. As illustrated in Fig. 14, when considering only the common bus master group and disregarding the second bus use request purposes, i.e., considering only the bus masters belonging to the common bus master group, the priority rankings are the sound processor 7, the graphics processor 3, the DMA controller 9 and the CPU 1 as listed from that having the highest priority in the case of the current generation processor 100. On the other hand, as shown in Fig. 12, the priority rankings are the sound processor 507, the graphics processor 503, the DMA controller 509 and the CPU 501 as listed from that having the highest priority in the case of the previous generation processor 500. As can be seen from these facts, the second bus arbiter 14 and the second bus arbiter 514 are equivalent with regard to the order of priority among the bus masters belonging to the common bus master group.

This is true also with respect to the relationship between the order of priority for use in the first bus arbiter 12 of the current generation processor 100 and the order of priority for use in the first bus arbiter 512 of the previous generation processor 500.

As a result, even if the bus masters of the current generation processor 100 issue bus use requests on the basis of the respective bus use request purposes, it is possible to properly run the software that can be run on the previous generation processor 500 (i.e., compatible software) also in the current generation processor 100, and maintain the backward compatibility with regard to bus arbitration.

Also, in the case of the previous generation processor 500, it is possible to set the access cycle number for accessing the second bus first area of the logical address space and the access cycle number for accessing the second bus second area of the logical address space only to a common value. That is, as shown in. Fig. 13, the second bus first area and the second bus second area share the same register for setting the access cycle number.

On the other hand, in the case of the current generation processor 100, the access cycle number for accessing the second bus first area and the access cycle number for accessing the second bus second area of the logical address space can be adjusted independently from each other. In other words, as shown in Fig. 15, the register 171 for setting the random access cycle number of the second bus first area and the register 172 for setting the random access cycle number of the second bus second area are separately provided (refer to Fig. 20) . Nevertheless, when an operation is executed by the current generation processor 100 during running compatible software for rewriting the virtual first and second area access cycle number register as illustrated in Fig. 15, i.e., when a write operation is executed by the current generation processor 100 during running compatible software to the address assigned to the virtual first and second area access cycle number register (which is the same address as assigned to the first and second area access cycle number register of the previous generation processor 500) , both the first area random access cycle number register 171 and the second area random access cycle number register 172 of the current generation processor 100 are rewritten by the data to be loaded to the virtual first and second area access cycle number register (that is the data to be loaded to the first and second area access cycle number register of the previous generation processor 500) . As a result, with regard to the access cycle number (i.e., the access speed) , while the address space is not divided into a plurality of areas in the case of the previous generation processor 500 but is divided into a plurality of areas in the case of the current generation processor 100, it is possible for the current generation processor 100 to properly run the software that can be run on the previous generation processor 500 (i.e., compatible software) and maintain the backward compatibility with regards to the access speed to the address space.

In addition to this, the previous generation processor 500 is not provided with functions to use a page mode for accessing the memories 545 to 547 connected to the external bus 543. Contrary to this, the current generation processor 100 is provided with functions to use a page mode for accessing the memories 45. to 47 connected to the external bus 43. Nevertheless, when an operation is executed by the current

• generation processor 100 during running compatible software for rewriting the virtual zeroth area access cycle number register as illustrated in Fig. 15, i.e., when a write operation is executed by the current generation processor 100 during running compatible software to the address assigned to the virtual zeroth area access cycle number register (which is the same address as assigned to the zeroth area access cycle number register of the previous generation processor 500) , the zeroth area random access cycle number register 170 of the current generation processor 100 is rewritten by the data to be loaded to the virtual zeroth area access cycle number register (that is the data to be loaded to the zeroth area access cycle number register of the previous generation processor 500) , and at the same time the zeroth area page size register 190 is set to "0" indicative of a page size of "0" so that the page mode is disabled. As a result, even if the previous generation processor 500 does not support a page mode, it is possible to properly run the software that can be run on the previous generation processor 500 (i.e., compatible software) also in the current generation processor 100, and maintain the backward compatibility with regards to the access mode for accessing the address space. Furthermore, in accordance with the present embodiment, when an operation is executed by the current generation processor 100 during running compatible software for rewriting the virtual first and second area access cycle number register as illustrated in Fig. 15, i.e., when a write operation is executed by the current generation processor 100 during running compatible software to the address assigned to the virtual first and second area access cycle number register, both the first area random access cycle number register 171 and the second area random access cycle number register 172 of the current generation processor 100 are rewritten by the data to be loaded to the virtual first and second area access cycle number register, and at the same time both the first area page size register 191 and the second area page size register 192 are set to "0" indicative of a page size of "0" so that the page mode is disabled. As a result, with regard to the access cycle number (i.e., the access speed) , even though the address space is not divided into a plurality of areas in the case of the previous generation processor 500 but is divided into a plurality of areas in the case of the current generation processor 100 while the previous generation processor 500 does not support a page mode, it is possible for the current generation processor 100 to properly run the software that can be run on the previous generation processor 500 (i.e., compatible software) and maintain the backward compatibility with regards to the access speed and the access mode for accessing the address space. Furthermore, in accordance with the present embodiment, the logical address space of the previous generation processor 500 is accessed by an address of "P" bits ("P" is one or a larger integer, which is 24 in the example shown in Fig. 6) . On the other hand, the logical address space of the current generation processor 100 is accessed by an address of "Q" bits ("Q" is an integer larger than P, i.e., two or a larger integer, which is 27 in the example shown in Fig. 7) . The logical address space of the current generation processor 100 is divided into a first address space (corresponding to the logical address space of the previous generation processor 500) accessible by addresses of which the upper (Q-P) bits are fixed respectively to "0", and a second address space corresponding to all the logical address space from which the first address space is excluded.

Accordingly, when compatible software which is prepared for the previous generation processor 500 is run by the current generation processor 100, the compatible software can access the first address space equivalent to the whole logical address space of the previous generation processor 500 while the current generation processor 100 serves to fix the upper (Q — P) bits respectively to "0", and the compatibility with regards to the address space can easily be maintained.

Also, the graphics processor 3 of the current generation processor 100 has the same functions as the graphics processor 503 of the previous generation processor 500, and also has additional functions (i.e., corresponding to three types of new addressing modes) to access not only the first address space but also the second address space which cannot be accessed by the graphics processor 503, while maintaining backward compatibility with the previous generation processor 500.

Furthermore, the current generation processor 100 is implemented with the pixel plotter 5 having a new function, of which counterpart does not exist in the previous generation processor 500, capacle of accessing both the first address space and the second address space. Incidentally, the compatibility with the previous generation processor 500 shall not be affected thereby because the previous generation processor 500 has no bus master corresponding to the pixel plotter 5. • In this manner, it is possible to implement the current generation processor 100 with bus masters having new a function without giving up backward compatibility.

By the way, in accordance with the present embodiment, the following advantages are realized by the functions of the second bus arbiter 14 of the current generation processor 100.

The second bus arbiter 14 grants to a bus master the bus cycles corresponding to the size requested by the bus master (refer to Fig. 19), so that the bus master can successively read or write data. Since the respective bus masters are permitted to successively use the bus in this manner and, at the same time, arbitration is always performed once for every series of the bus cycles corresponding to the requested size, it is possible to increase the rate of operating the bus and decrease the latency of the responsive to the bus use request from a bus master as short as possible.

In addition to this, since the size signal "EIFS", "ECHS", "ECDS", "EPPS" or "EDSS" indicative of the size of data to be read or written is issued by a bus master as a size signal indicative of the necessary and sufficient size for data transmission, the state machine 155 can set an optimal number of bus cycles. Accordingly, in this case, it is possible to further improve the rate of operating the bus and further shorten the latency of the response to a bus use request.

In addition, the state machine 155 grants the ownership for "N" bus cycles to the bus master selected by the priority decoder 142 in accordance with the following equation (called the optimal bus cycle number calculating equation in the following explanation) . N = ((A + B - 1) /W) - (A/W) + 1

In the above equation, "A" is address information issued when a bus master issues a bus use request and is a byte address pointing to the first byte of data to be read or written. This address "A" is equivalent to the unified address "CADR" of Fig. 20.

"B" is the size information of data to be read or written by a bus master, and is the number of the bytes of the data. This number "B" is equivalent to the unified size signal "CSZ" of Fig. 20. As thus described, in the case of the present embodiment, a bus master designates the size of data to be read or written in terms of the number of bytes .

"W" is the number of bytes corresponding to the data bus width of the area pointed to by the address information "A". This number "W" is equivalent to the number of bytes indicated by the unified bus width signal "CBW" of Fig. 20. Namely, if the unified bus width signal "CBW" is "0", the data bus width is one byte ( = 8 bits); and if the unified bus width signal "CBW" is "1" the data bus width is 2 bytes ( = 16 bits) . The address information "A" indicates the ordinal number of the byte, from which the data read or write operation starts, as counted from the zeroth byte. Thus, the number (A 4- B - 1) indicates the ordinal number of the byte, at which the data read or write operation ends, as counted from the zeroth byte. Since the number "W" of bytes of the data bus width of the area designated by the address information "A" indicates the number of bytes of one word of the external memories 45 to 47 to be connected, the number (A + B - 1)/W indicates the ordinal number of the word, at which the data read or write operation ends, as counted from the zeroth word, and the number (A/W) indicates the ordinal number of the word, from which the data read or write operation starts, as counted from the zeroth word. In other words, the number "N" indicates the number of words to be read or written. Accordingly, as easily understood, if it is assumed that one word data is transferred in one bus cycle, the number "N" indicates the number of bus cycles required for transferring data.

Furthermore, the CPU 1 can set the number "W" of bytes of the data bus width for each of the areas (the second bus zeroth area, the second bus first area and the second bus second area as illustrated in Fig. 7) by loading a value to each of the zeroth area bus width register 160, the first area bus width register 161 and the second area bus width register 162.

The address decoder 149 judges which of the three areas (the second bus zeroth area, the second bus first area and the second bus second area) is designated by the address information "A" issued by the bus master as selected by the priority decoder 142, i.e., the unified address "CADR", and the multiplexer 151 selects the data bus width of one of the three areas in accordance with the result of judgment and outputs the data bus width signal as selected to the state machine 155 as the unified bus width "CBW".

The state machine 155 calculates the number "N" on the basis of the optimal bus cycle number calculating equation by the use of the number "W" of bytes indicated by the unified bus width signal "CBW".

Accordingly, even in the case where the address space is divided into a plurality of areas having different data bus widths, the state machine 155 can grant to each bus master the bus ownership of the necessary and sufficient bus cycles corresponding to the data bus width of the area to be accessed.

Furthermore, when the sound processor 7 outputs a bus use request (a wave data bus use request signal "EWAB" or an envelope data bus use request signal "EEVB") while the second bus 33 is used by a bus master other than the sound processor I₁ the state machine 155 interrupts the use of the bus by the bus master and grants bus ownership to the sound processor 7 on the condition that the number of the remaining bus cycles is not smaller than a predetermined number.

Accordingly, it is possible to preferentially proceed with the urgent process of a bus master such as the sound processor 7 without delay while maintaining the advantages of successive bus cycles given to the respective bus masters. The details are as follows. While the general throughput of data transmitted by the bus can be increased by granting bus ownership to the respective bus masters for successive bus cycles, the latency from issuing a bus use request by the bus master to obtaining bus ownership tends to increase. However, in the case where there is a bus master which is responsible for processing such an urgent task that bus ownership must be granted within a predetermined time period after issuing a bus use request, the increase of the latency may cause a trouble in the operation of the system. In this situation, while increasing the throughput, it is possible to avoid the disadvantages associated with the increased latency by accepting the interrupt for granting bus ownership to a bus master responsible for processing an urgent task if the bus master issues a bus use request and if the number of the remaining bus cycles granted to the current bus master using the bus is not smaller than a predetermined number. As thus described, the bus use request of the sound processor 7 is given priority so that discontinuity can be prevented from occurring in the output of the audio signal "AU".

Furthermore, while the first bus arbiter 13 performs arbitration of the respective first bus use request purposes (refer to Fig. 10) , the second bus arbiter 14 performs arbitration of the respective second bus use request purposes (refer to Fig. 14) . Accordingly, there are the following effects.

Namely, in the case where bus masters respectively have a plurality of bus use request purposes, if the bus arbiter performs the arbitration only of the respective bus masters, an additional circuit

• must be provided in the respective bus masters for performing arbitration of bus use requests issued by a plurarity of bus use request purposes, resulting in a greater hardware size. In addition, depending upon the circuit configuration, a time overhead may occur from the arbitration of the bus use request purposes in the respective bus masters. However, in the case where the bus arbiter (the first bus arbiter 13, the second bus arbiter 14) performs arbitration of the respective bus use request purposes in accordance with the present embodiment, the above disadvantages shall not occur. Furthermore, a plurality of bus masters are capable of issuing the size signals "EIFS", "ECDS", "EPPS" and "EDSS" indicative of different sizes for the respective second bus use request purposes (refer to Fig. 19) . This is possible also for the respective first bus use request purposes. As has been discussed above, since a size signal indicative of a different size can be issued for each bus use request purpose corresponding to its necessary data size, it is possible to reduce the number of ineffective data accesses, further improve the rate of operating the bus and further shorten the latency of the response to a bus use request. Furthermore, the distribution of bus cycles among the respective bus masters can be controlled by sequentially and cyclically selecting one of multiple sets of priority level information (16 priority level registers 300 to 315 each of which stores one of the priority level information numbers 0 to 3 of Fig. 10 for the first bus arbiter 13, and 8 priority level registers 200 to 207 each of which stores one of the priority level information numbers 0 to 3 of Fig. 14 for the second bus arbiter 14) .

Still further, the period of one bus cycle for each area (the second bus zeroth area, the second bus first area or the second bus second area) can be optimized corresponding to the speed of the external memories 45 to 47 connected to the second bus 33 by loading appropriate values to the registers 170 to 172 and 180 to 182 via the CPU 1 for setting the bus cycle periods. Also, it is expected to reduce the power consumption by dynamically changing the bus cycle period through the CPU 1 in accordance with the current operation mode.

Furthermore, since the random access cycle number and the page access cycle number can be dynamically set by the CPU 1, the number of clock cycles corresponding to one bus cycle period can be optimized in accordance with the random access speed of the external memories 45 to 47 connected to the second bus 33 and the page access speed in the page mode of the external memories 45 to 47.

Still further, if the number of bus cycles granted to a bus master having bus ownership is "1", the state machine 155 uses the unified random access cycle number signal "CRCY" as the bus cycle period.

In this case, the number of bus cycles of "1" granted to a bus master means that the number N calculated on the basis of the optimal bus cycle number calculating equation is 1, and therefore, for example, it means that if the bus width indicated by the unified bus width signal "CBW" is 2 bytes, the size indicated by the unified size signal "CSZ" is 2 bytes, or that if the bus width indicated by the unified bus width signal "CBW" is 1 byte, the size indicated by the unified size signal "CSZ" is 1 byte. On the other hand, in the case where the number of bus cycles granted to a bus master having bus ownership is "2" or more, the state machine 155 uses as the bus cycle period in the first bus cycle the unified random access cycle number signal "CRCY", and uses as the bus cycle period in the subsequent bus cycles the unified page access cycle number signal "CPCY" if the current second bus address "EAD" points to the same page as the second bus address "EAD" in the previous bus cycle and the unified random access cycle number signal "CRCY" if the current second bus address "EAD" points to a page different from the page pointed to by the second bus address "EAD" in the previous bus cycle.

In this case, the number of bus cycles of "2" or more granted to a bus master means that the number N calculated on the basis of the optimal bus cycle number calculating equation is 2 or more, and therefore, for example, it means that if the bus width indicated by the unified bus width signal "CBW" is 2 bytes, the size indicated by the unified size signal "CSZ" is 4 bytes, or that if the bus width indicated by the unified bus width signal "CBW" is 1 byte, the size indicated by the unified size signal "CSZ" is 2 byte.

As has been discussed above, in the case where the second bus 33 is connected to the external memories 45 to 47 accessible in a page mode, it is possible to optimize the length of bus cycle periods (i.e. the number of clocks per bus cycle) .

Furthermore, appropriate values can be loaded to the registers 190 to 192 by the CPU 1 in order to dynamically set the page sizes. Because of this, it is possible to set the page sizes corresponding to • the external memories 45 to 47.

Furthermore, while the address space of the second bus 33 is divided into the three areas (refer to Fig. 7) in accordance with the present embodiment, it is possible to separately set the number "W" of bytes of the data bus width, the random access cycle number, the page access cycle number, and the page size for each area by loading appropriate values respectively to the registers 160 to 162, 170 to 172, 180 to 182 and 190 to 192. Then, the address decoder 149 judges which of the three areas (the second bus zeroth area, the second bus first area and the second bus second area) is designated by the address information "A" issued by the bus master as selected by the priority decoder 142, i.e., the unified address "CADR", and the multiplexers 151 to 153 and the decoder 154 select one of the three areas in accordance with the result of judgment and outputs the unified bus width signal "CBW", the unified random access cycle number signal "CRCY", the unified page access cycle number signal "CPCY" and the unified page boundary signal "CPB" to the state machine 155.

The state machine 155 calculates the number "N" on the basis of the optimal bus cycle number calculating equation from the number "W" of bytes of the data bus width indicated by the unified bus width "CBW" .

Accordingly, in the case where the address space of the external memories 45 to 47 is divided into a plurality of areas having different random access speeds, different page access speeds, different page sizes and different data bus widths, the second bus arbiter 14 switches the random access cycle number, the page access cycle number, the page size and the data bus width each time arbitration is performed in accordance with the settings of the area to be accessed in order to optimize the bus cycle period (i.e., the period of one bus cycle ) and the number of the bus cycles granted to a bus master.

Incidentally, the present invention is not limited to the above embodiments, and a variety of variations and modifications may be effected without departing from the spirit and scope thereof, as described in the following exemplary modifications.

(1) In the case of the current generation processor 100 as described above, bus arbitration is performed for the respective bus use request purposes. Nevertheless, in the case of the current generation processor 100, it is possible to perform bus arbitration among bus masters in the same manner as the previous generation processor 500.

In this case, the order of priority among the bus masters of the common bus master group for use in the first bus arbiter 13 of the current generation processor 100 are determined in order to be identical with the order of priority among the bus masters of the common bus master group for use in the first bus arbiter 513 of the previous generation processor 500. Likewise, the order of priority among the bus masters of the common bus master group for use in the second bus arbiter 14 of the current generation processor 100 are determined in order to be identical with the order of priority among the bus masters of the common bus master group for use in the second bus arbiter 514 of the previous generation processor 500.

By this configuration, even if a new bus master (the pixel plotter 5 in the case of the above example) is introduced into the current generation processor 100 in addition to those corresponding to the bus masters implemented in the previous generation processor 500, it is possible to properly run the software that can be run on the previous generation processor 500 (i.e., compatible software) also in the current generation processor 100, and maintain the backward compatibility with regard to bus arbitration. (2) The current generation processor 100 can be designed in order that, when an operation is executed by the current generation processor 100 during running compatible software for rewriting the virtual zeroth area access cycle number register as illustrated in Fig. 15, i.e., when a write operation is executed by the current generation processor 100 during running compatible software to the address assigned to the virtual zeroth area access cycle number register, both the zeroth area random access cycle number register 170 and the zeroth area page access cycle number register 180 of the current generation processor 100 is rewritten by the data to be loaded to the virtual zeroth area access cycle number register.

In the same way, the current generation processor 100 can be designed in order that, when an operation is executed by the current generation processor 100 during running compatible software for rewriting the virtual first and second area access cycle number register as illustrated in Fig. 15, i.e., when a write operation is executed by the current generation processor 100 during running compatible software to the address assigned to the virtual first and second area access cycle number register, both the first area random access cycle number register 171 and the second area random access

■ cycle number register 172 of the current generation processor 100 and both the first area page access cycle number register 181 and the second area page access cycle number register 182 are rewritten by the data to be loaded to the virtual first and second area access cycle number register. Meanwhile, in this case, the range for values that can be set in the random access cycle number register is equal to the range for values that can be set in the page access cycle number register.

As a result, since the random' access mode and the page mode become substantially equivalent to each other, even if the previous generation processor 500 supports only a random access mode, it is possible to properly run the software that can be run on the previous generation processor 500 (i.e., compatible software) also in the current generation processor 100, and maintain the backward compatibility with regards to the access mode for accessing the address space.

(3) In the case of the current generation processor 100 as described above, the virtual zeroth area access cycle number register and the virtual first and second area access cycle number register are mapped, in the address space, to the addresses of the corresponding registers of the previous generation processor 500. However, it is possible to map the respective registers of the current generation processor 100 in the address space without using such virtual registers. Fig. 22 is a table for showing the list of hardware control registers provided in the second bus arbiter 14 of Fig. 1, and the hardware control registers are mapped in different addresses than those shown in Fig. 15 in the logical address space of the current generation processor 100. As illustrated in Fig. 22, the address assigned to the zeroth area random access cycle number register of the current generation processor 100 is identical to the address assigned to the zeroth area access cycle number register of the previous generation processor 500. Similarly, the address assigned to the first area random access cycle number register of the current generation processor 100 is identical to the address assigned to the first and second area access cycle number register of the previous generation processor 500.

By this configuration, in the case where the software that can be run on the previous generation processor 500 (i.e., compatible software) is run on the current generation processor 100, the zeroth

• area random access cycle number register of the current generation processor 100 is accessed by executing an instruction for accessing the zeroth area access cycle number register. When running the compatible software, the zeroth area random access cycle number register of the current generation processor 100 serves as the zeroth area access cycle number register of the previous generation processor 500 so that there is no problem in maintaining the compatibility. Also, in the case where the compatible software is run on the current generation processor 100 and an instruction for accessing the first and second area access cycle number register is executed, the first area random access cycle number register of the current generation processor 100 is accessed. In this case, when an instruction for rewriting the first and second area access cycle number register in the current generation processor 100 is executed, it is required not only to rewrite the first area random access cycle number register but also to rewrite the second area random access cycle number register.

Accordingly, the current generation processor 100 has to change the process which is performed by this rewriting instruction depending upon whether the software currently running is the compatible software or the incompatible software. In the case where the compatible software is run, if the instruction for rewriting the first area random access cycle number register (i.e., the instruction for rewriting the first and second area access cycle number register) is executed, the current generation processor 100 also rewrites the second area random access cycle number register in order to keep the first area random access cycle number register and the second area random access cycle number register in a state of coherence. On the other hand, in the case where the incompatible software is run, if the instruction for rewriting the first area random access cycle number register is executed, the current generation processor 100 rewrites only the first area random access cycle number register. In accordance with one of possible implementations for this scheme, there are two operation modes in the current generation processor 100, i.e., a compatible mode indicating that the compatible software is currently running and an incompatible mode indicating that the incompatible software is currently running. The compatible mode is the default mode of the current generation processor 100. The incompatible software includes an instruction for switching the compatible mode to the incompatible mode in its start-up routine. Alternatively, it is possible to implement a switching mechanism between the compatible mode and the incompatible mode by the use of a control register.

The foregoing description of the embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and obviously many modifications and variations are possible in light of the above teaching. The embodiment was chosen in order to explain most clearly the principles of the invention and its practical application thereby to enable others in the art to utilize most effectively the invention in various embodiments and with various modifications as are suited to the particular use contemplated.

Claims

1. A data processing unit capable of running both the software that can be run on a predetermined another data processing unit comprising a first bus master group consisting of a predetermined plural number of bus masters and a first bus arbitor operable to perform bus arbitration in accordance with first priority ranking information about the order of priority among the plurality of bus masters belonging to the first bus master group, and the software that cannot be run on the predetermined another data processing unit, said data processing unit comprising: a second bus master group including bus masters which are provided corresponding respectively to the bus masters belonging to the first bus master group and further including one or more additional bus masters; and a second bus arbitration unit operable to perform bus arbitration in accordance with second priority ranking information about the order of priority among the bus masters belonging to said second bus master group, wherein the order of priority among the bus masters

■ corresponding to the bus masters belonging to the first bus master group in accordance with the second priority ranking information is identical with the order of priority in accordance with the first priority ranking information.

2. A data processing unit capable of running both the software that can be run on a predetermined another data processing unit comprising a first bus master group consisting of a predetermined plural number of bus masters and a first bus arbitor operable to perform bus arbitration in accordance with first priority ranking information about the order of priority among the plurality of bus masters belonging to the first bus master group, and the software that cannot be run on the predetermined another data processing unit, said data processing unit comprising: a second bus master group including bus masters which are provided corresponding respectively to the bus masters belonging to the first bus master group, each bus master belonging to said second bus master group being capable of issuing a bus use request for one or more bus use request purpose; and a second bus arbitor operable to perform bus arbitration on the basis of a second priority ranking information which determines the order of priority among all the bus use request purposes of the bus masters belonging to said second bus master group, wherein at least one of the bus masters belonging to said second bus master group is capable of issuing bus use requests for a plurality of the included bus use request purposes, and consecutive priority rankings are assigned to the plurality of the bus use request purposes, and wherein the order of priority among the bus masters in accordance with the second priority ranking information is identical with the order of priority among the corresponding bus masters in accordance with the first priority ranking information.

3. A data processing unit capable of running both the software that can be run on a predetermined another data processing unit comprising a first bus cycle length information storing unit operable to store a bus cycle length for accessing a predetermined address area, and the software that cannot be run on the predetermined another data processing unit, wherein the address area of said data processing unit corresponding to the predetermined address area is divided into a plurality of areas, wherein said data processing unit is provided with a plurality of second bus cycle length information storing units which are provided respectively for the plurality of areas and operable to store bus cycle lengths respectively for accessing the plurality of areas, wherein if an operation for rewriting the content stored in the first bus cycle length information storing unit is executed by said data processing unit while running, in said data processing unit, the software that can be run on the predetermined another data processing unit, the contents stored in all the second bus cycle length information storing units are rewritten by a value equivalent to the content stored in the first bus cycle length information storing unit.

4. A data processing unit capable of running both the software that can be run on a predetermined another data processing unit comprising a first bus cycle length information storing unit operable to store a bus cycle length for accessing a predetermined address area, and the software that cannot be run on the predetermined another data processing unit, said data processing unit comprising: a second bus cycle length information storing unit operable to store a bus cycle length for accessing the predetermined address area in a first access mode; and a third bus cycle length information storing unit operable to store a bus cycle length for accessing the predetermined address area in a second access mode, wherein if an operation for rewriting the content stored in the first bus cycle length information storing unit is executed by said data processing unit while runningthe software that can be run on the predetermined another data processing unit, the content stored in said second bus cycle length information storing unit and the content stored in said third bus cycle length information storing unit are rewritten by a value equivalent to the content to be stored in the first bus cycle length information storing unit.

5. A data processing unit capable of running both the software that can be run on a predetermined another data processing unit comprising a first bus cycle length information storing unit .operable to store a bus cycle length for accessing a predetermined address area, and the software that cannot be run on the predetermined another data processing unit, said data processing unit comprising: a second bus cycle length information storing unit operable to store a bus cycle length for accessing the predetermined address area in a random access mode; a third bus cycle length information storing unit operable to store a bus cycle length for accessing the predetermined address area in a page mode; and a page size information storing unit operable to store a size of one page for the page mode, wherein if an operation for rewriting the content stored in the first bus cycle length information storing unit is executed by said data processing unit while running the software that can be run on said predetermined another data processing unit, the content stored in said second bus cycle length information storing unit is rewritten by a value equivalent to the content to be stored in the first bus cycle length information storing unit, and said page size information storing unit indicative of the size of one page is rewritten by a value indicating that the page mode is disabled.

6. A data processing unit capable of running both the software that can be run on a predetermined another data processing unit comprising a first bus cycle length information storing unit operable to store a bus cycle length for accessing a predetermined address area, and the software that cannot be run on the predetermined another data processing unit, wherein the address area of said data processing unit corresponding to the predetermined address area is divided into a plurality of areas, said data processing unit comprising: a plurality of second bus cycle length information storing units provided respectively for the plurality of areas and operable to store bus cycle lengths respectively for accessing the plurality of areas in a random access mode; a plurality of third bus cycle length information storing units provided respectively for the plurality of areas and operable to store bus cycle lengths respectively for accessing the plurality of areas in a page mode; and a plurality of page size information storing units provided respectively for the plurality of areas and individually operable to store a size of one page for the page mode, wherein if an operation for rewriting the content stored in said first bus cycle length information storing unit is executed by said data processing unit while running the software that can be run on the predetermined another data processing unit, the contents stored in all said second bus cycle length information storing units are rewritten by a value equivalent to the content to be stored in the first bus cycle length information storing unit and all of said page size information storing units indicative of the size of one page is rewritten by a value indicating that the page mode is disabled.

7. A data processing unit capable of running both the software that can be run on a predetermined another data processing unit which operates in a logical address space of "P" bits ("P" is one or a larger integer) and comprises a first bus master and a second bus master, and the software that cannot be run on the predetermined another data processing unit, wherein the logical address space of said data processing unit is addressed by address information of "Q" bits (Q is an integer larger than "P") , and divided into a first address space accessible by addresses of which the upper (Q ^~ P) bits of Q bits are fixed respectively to "0" and a second address space corresponding to all the logical address space from which the first address space is excluded, said data processing unit comprising: a third bus master has the same function as the first bus master and can access only the first address space; a fourth bus master has the same function as the second bus master and has an additional function to access both the first address space and the second address space; and a fifth bus master has a different function than the first bus master and the second bus master have, and has a function to access both the first address space and the second address space.

8. A compatible processor capable of running the software that can be run on a previous generation processor, said compatible processor comprising: a plurality of compatible bus masters which are compatible respectively with previous bus masters of the previous generation processor; and a compatible bus arbitor operable to perform arbitration of bus • use requests issued by said compatible bus masters, wherein the bus use requests issued by said compatible bus masters during running any implementation of the software in said compatible processor are always granted in the same order of priority as the bus use requests issued by the previous bus masters during running the any implementation of the software in the previous generation processor.

9. A processor comprising arithmetic logical circuitry operable to process data and a real control register operable to control the operation of processing data, wherein a virtual control register is defined by mapping in an address of a address space of said processor, wherein a write operation for writing a value to the address of said virtual control register has a certain function in the context of software that can be run on said processor, wherein the real control register is mapped in an address of the address space of said processor such that the address of the real control register differs from the address of said virtual control register and that the real control register provides a function equivalent to the certain^' function in the hardware of said processor, and wherein, if the operation for writing a value to the address of said virtual control register is executed, a corresponding value is written to the real control register.

10. A compatible processor capable of running the software that can be run on a previous generation processor, wherein a bus use request can be issued in said compatible processor for one of a plurality of purposes and granted in accordance with the order of priority among the plurality of purposes, wherein a bus use request can be issued in the previous processor for one of a plurality of purposes and granted in accordance with the order of priority among the plurality of purposes, the plurality of purposes of the previous generation processor is substantially a proper subset of the plurality of purposes of said compatible processor in terms of the bus use requests during execution of the software, and wherein the order of priority within the proper subset of the plurality of purposes of said compatible processor is equivalent to the order of priority among the plurality of purposes of the previous generation processor.