JP2008505386A - Data processing device and compatible processor - Google Patents

Abstract

  A processor capable of maintaining backward compatibility with previous generation processors is provided. When the current generation processor 100 writes a value on the address where the 0th area access cycle number register is arranged in the previous generation processor 500, the same value is written to the 0th area random access cycle number register 170, and The value of the 0th area page size register 190 is set to 0 (page size = 0 bytes), and page mode access is not performed. When the current generation processor 100 writes a value on the address where the first and second area access cycle number registers are arranged in the previous generation processor 500, the same value is stored in the first area random access cycle number register 171 and the first area access cycle number register 171. The two area random access cycle number register 172 is written, and the values of the first area page size register 191 and the second area page size register 192 are set to 0, and the page mode access is not performed.

Description

  The present invention relates to a data processing device and a compatible processor having backward compatibility with previous generation data processing devices.

  Various techniques for realizing backward compatibility with previous generation processors are disclosed in documents such as Japanese Patent Application Laid-Open Nos. 11-2332098, 11-2332099, and 3-248240. Yes.

  Although not disclosed in the above document, the following can be cited as a target for realizing backward compatibility.

  The first is backward compatibility for bus arbitration.

  The second is backward compatibility with respect to the access speed when accessing each area of the address space divided into a plurality of areas.

  The third is backward compatibility for the access mode when accessing the address space.

  The fourth is backward compatibility with the structure of the address space to be accessed.

  Therefore, an object of the present invention is to provide a data processing device and a compatible processor that can realize backward compatibility with the previous generation data processing device with respect to bus arbitration.

  Another object of the present invention is to provide a data processor and a compatible processor capable of realizing backward compatibility with the data processor of the previous generation with respect to the access speed to each area of the address space.

  Still another object of the present invention is to provide a data processing device and a compatible processor capable of realizing backward compatibility with the previous generation data processing device in the access mode to the address space.

  Still another object of the present invention is to provide a data processing apparatus and a compatible processor capable of realizing backward compatibility with the previous generation data processing apparatus with respect to the structure of the address space to be accessed.

  According to the first aspect of the present invention, the data processing device determines a priority order between a first bus master group including a predetermined number (two or more) of bus masters and the bus masters included in the first bus master group. A first bus arbitration unit that performs bus arbitration according to the first priority order information, and software that can be executed by another predetermined data processing device and software that cannot be executed by the predetermined another data processing device A data processing device that can also execute software, is compatible with the first bus master group, and further includes a second bus master group including one or more bus masters, and the second bus master group includes the second bus master group Second bus arbitration means for performing bus arbitration according to second priority information that defines priorities among bus masters, and the second priority information in the second priority information Priorities among compatible bus master to one bus master group master is the same as the first priority information.

  According to this configuration, the priority between the bus masters of the first bus master group in the second priority information of the current generation data processing device is the same as the first priority information of the previous generation data processing device. The software (compatible software) that can be executed in both the current generation data processing device in which a new bus master is added to the bus master included in the previous generation data processing device and the previous generation data processing device can be executed normally. , Backward compatibility with bus arbitration is maintained.

  According to the second aspect of the present invention, the data processing device determines a priority order between a first bus master group including a predetermined number (two or more) of bus masters and the bus masters included in the first bus master group. A first bus arbitration unit that performs bus arbitration according to the first priority order information, and software that can be executed by another predetermined data processing device and software that cannot be executed by the predetermined another data processing device A data processing apparatus that can also execute software, and corresponds to each of the bus masters included in the first bus master group, and requests the use of the bus for each bus use request factor that is a factor requesting use of the bus. The priority order between the bus use request factors of the second bus master group including a plurality of bus masters and all the bus masters included in the second bus master group is defined. A second bus arbitration unit that performs bus arbitration according to the second priority information, and when the second priority information includes a plurality of bus use request factors in one bus master, Successive priorities are assigned to the plurality of bus use request factors, and the priorities among the bus masters in the second priority information are the same as the priorities between the corresponding bus masters in the first priority information. It is.

  According to this configuration, in the second priority information of the current generation data processing device, when a plurality of bus use request factors are included in one bus master, the priority order consecutive to the plurality of bus use request factors Is assigned. For this reason, the second priority order information sets the priority order for each bus master from software (compatible software) that can be executed in the previous generation data processing device that does not make a bus use request for each bus use request factor. looks like. Moreover, the priority between the bus masters of the first bus master group in the second priority information of the current generation data processing device is the priority between the corresponding bus masters in the first priority information of the previous generation data processing device. The same.

  As a result, even when the bus master of the current generation data processing device makes a bus use request for each bus use request factor, the software (compatible software) that can be executed in the previous generation data processing device can be executed normally. Backwards compatibility for bus arbitration is maintained.

  According to the third aspect of the present invention, the data processing device includes a predetermined other data processing device including a first bus cycle period length information storage unit that determines a bus cycle period length when accessing a predetermined address area. A data processing apparatus capable of executing both executable software and software that cannot be executed by the predetermined other data processing apparatus, wherein the predetermined address area as an access target by the data processing apparatus includes a plurality of software The data processing device includes a plurality of second bus cycle period length information storage units that respectively correspond to the plurality of areas and determine a bus cycle period length when accessing the corresponding area, The software executed by the predetermined data processing device executed by the data processing device is: When the operation of rewriting the contents of the first bus cycle period length information storage means is performed, all the contents of the second bus cycle period length information storage means are stored in the first bus cycle period length information storage means. Rewritten to be the same as the contents.

  According to this configuration, when the compatible software executed by the current generation data processing apparatus performs an operation of rewriting the contents of the first bus cycle period length information storage means, that is, by the current generation data processing apparatus. When the executed compatible software performs a write operation on the address where the first bus cycle period length information storage means is arranged, the contents of all the second bus cycle period length information storage means are the first. Is rewritten to be the same as the contents of the bus cycle period length information storage means.

  As a result, the address area is not divided into multiple areas for the previous generation data processor, but is divided into multiple areas for the current generation data processor, and the bus cycle period length can be set for each area. Even in such a case, software (compatible software) that can be executed in the previous generation data processing apparatus can be normally executed, and backward compatibility with respect to the access speed to the address area is maintained.

  According to the fourth aspect of the present invention, the data processing device includes a predetermined other data processing device including a first bus cycle period length information storage unit that determines a bus cycle period length when accessing a predetermined address area. A data processing apparatus capable of executing both executable software and software that cannot be executed by the predetermined another data processing apparatus, and a bus for accessing the predetermined address area in a first access mode Second bus cycle period length information storage means for determining a cycle period length; and third bus cycle period length information storage means for determining a bus cycle period length when accessing the predetermined address area in a second access mode; The software that is executed by the data processing apparatus and that can be executed by the other predetermined data processing apparatus When the air performs an operation of rewriting the contents of the first bus cycle period length information storage means, the contents of the second bus cycle period length information storage means and the third bus cycle period length information storage The contents of the means are rewritten so as to be the same as the contents of the first bus cycle period length information storage means.

  According to this configuration, when the compatible software executed by the current generation data processing apparatus performs an operation of rewriting the contents of the first bus cycle period length information storage means, that is, by the current generation data processing apparatus. When the executed compatible software performs a write operation on the address where the first bus cycle period length information storage unit is arranged, the second bus cycle period length information storage unit corresponding to the first access mode And the contents of the third bus cycle period length information storage means corresponding to the second access mode are the same as the contents of the first bus cycle period length information storage means of the previous generation data processing device. To be rewritten.

  As a result, since the first access mode and the second access mode are substantially the same mode, the previous generation data processing apparatus supports only one of the first access mode and the second access mode. Even in this case, software (compatible software) that can be executed in the previous generation data processing apparatus can be executed normally, and backward compatibility with the access mode to the address area is maintained.

  According to the fifth aspect of the present invention, the data processing device includes a predetermined other data processing device including a first bus cycle period length information storage unit that determines a bus cycle period length when accessing a predetermined address area. A data processing device capable of executing both executable software and software that cannot be executed by the predetermined another data processing device, and a bus cycle period when accessing the predetermined address area in a random access mode A second bus cycle period length information storage unit for determining a length; a third bus cycle period length information storage unit for determining a bus cycle period length for accessing the predetermined address area in a page mode; Page size information storage means for determining the size of one page, and the data processing device The second bus cycle period when the software executable by the predetermined another data processing apparatus performs an operation of rewriting the contents of the first bus cycle period length information storage means. The length information storage means is rewritten to be the same as the content of the first bus cycle period length information storage means, and the size of one page indicated by the page size information storage means invalidates the page mode. It is rewritten to the value to be.

  According to this configuration, when the compatible software executed by the current generation data processing apparatus performs an operation of rewriting the contents of the first bus cycle period length information storage means, that is, by the current generation data processing apparatus. When the executed compatible software performs a write operation on the address where the first bus cycle period length information storage unit is arranged, the size of one page indicated by the page size information storage unit invalidates the page mode. This value is rewritten to prevent the page mode from being accessed. Moreover, the contents of the second bus cycle period length information storage means are rewritten so as to be the same as the contents of the first bus cycle period length information storage means.

  As a result, even if the previous generation data processing apparatus does not support the page mode, the software (compatible software) that can be executed in the previous generation data processing apparatus can be executed normally, and the address area access mode is supported. Backwards compatibility is maintained.

  According to the sixth aspect of the present invention, the data processing device includes a predetermined another data processing device including first bus cycle period length information storage means for determining a bus cycle period length when accessing a predetermined address area. Is a data processing apparatus capable of executing both software that can be executed and software that cannot be executed by the predetermined another data processing apparatus, and a plurality of the predetermined address areas to be accessed by the data processing apparatus A plurality of second bus cycle period length information for determining a bus cycle period length corresponding to each of the plurality of areas and accessing the corresponding area in a random access mode. The storage means and each of the plurality of areas correspond to each other, and the corresponding area is accessed in the page mode. A plurality of third bus cycle period length information storage means for determining the bus cycle period length, and a plurality of page size information storage means for determining the size of one page in the page mode respectively corresponding to the plurality of areas. And when the software executed by the data processing device and executable by the predetermined other data processing device performs an operation of rewriting the contents of the first bus cycle period length information storage means, The second bus cycle period length information storage means is rewritten so that the content of the second bus cycle period length information storage means is the same as that of the first bus cycle period length information storage means, and all the page size information storage means indicate 1 The page size is rewritten to a value that invalidates the page mode.

  According to this configuration, when the compatible software executed by the current generation data processing apparatus performs an operation of rewriting the contents of the first bus cycle period length information storage means, that is, by the current generation data processing apparatus. When the executed compatible software performs a write operation on the address where the first bus cycle period length information storage means is arranged, the contents of all the second bus cycle period length information storage means are the first. Is rewritten to be the same as the contents of the bus cycle period length information storage means, and the size of one page indicated by all the page size information storage means is rewritten to a value invalidating the page mode, and access by the page mode is performed. Will not be performed.

  As a result, the address area is not divided into multiple areas for the previous generation data processor, but is divided into multiple areas for the current generation data processor, and the bus cycle period length can be set for each area. Even if the previous generation data processing device does not support page mode, software (compatible software) that can be executed in the previous generation data processing device can be executed normally. The backward compatibility with respect to the access speed and access mode to the address area is maintained.

  According to the seventh aspect of the present invention, the data processing device includes a logical address space indicated by address information of P (P is an integer of 1 or more) bits, a first predetermined number of first bus masters and a second bus master. A data processing apparatus capable of executing both software that can be executed by a predetermined other data processing apparatus including a predetermined number of second bus masters and software that cannot be executed by the predetermined other data processing apparatus. The logical address space of the data processing apparatus is indicated by Q (Q is an integer greater than or equal to 2) bits of address information, and the upper (QP) bits of the Q-bit address information are “0”. , And a second address space including all other spaces, and the data processing device includes the first predetermined number of third bus masters, A second predetermined number of fourth bus masters and a third predetermined number of fifth bus masters, wherein the third bus master has the same function as the first bus master, and the first address The fourth bus master has the same function as the second bus master, and has an additional function capable of accessing both the first address space and the second address space. The fifth bus master has a function different from that of the first bus master and the second bus master, and has a function capable of accessing both the first address space and the second address space.

  According to this configuration, when software (compatible software) that can be executed in the previous generation data processing apparatus is executed in the current generation data processing apparatus, the upper (QP) bits of the Q-bit address information are set to “0”. In this case, the third bus master and the fourth bus master of the current generation data processing apparatus can access the first address space, and compatibility with the address space can be easily maintained.

  In addition, the fourth bus master of the current generation data processing device having the same function as the second bus master of the previous generation data processing device is not only accessible by the second bus master in addition to the first address space. The address area can be extended while maintaining backward compatibility with the previous generation data processing apparatus.

  Furthermore, in the current generation data processing apparatus, a fifth bus master having a new function compared to the previous generation data processing apparatus is provided so that both the first address space and the second address space can be accessed. Yes. However, since the previous generation data processing apparatus is not provided with a bus master having such a function in the first place, it does not have any influence on maintaining backward compatibility with the previous generation data processing apparatus. As described above, in the current generation data processing apparatus, it is possible to add the fifth bus master having a new function while maintaining backward compatibility.

  According to the eighth aspect of the present invention, the compatible processor capable of executing software executable by the previous generation processor includes a plurality of compatible bus masters compatible with each of the previous generation bus masters of the previous generation processor, Compatible bus arbitration means for arbitrating a bus use request issued by the compatible bus master, and any software that can be executed by a previous generation processor is compatible with the compatible processor during execution of the software. The bus use request issued by the bus master is accepted in the same priority as the bus use request issued by the bus master during execution of the software in the previous generation processor.

  According to this configuration, it is possible to provide a compatible processor capable of realizing backward compatibility with the previous generation processor for bus arbitration.

  According to the ninth aspect of the present invention, in a processor including an arithmetic logic circuit that processes data and a physical control register that controls data processing operations, a virtual register is transferred to an address in the logical address space of the processor. In the software configuration executable by the processor, an instruction to write a value to the virtual register address has a certain function, and the logical address space address of the processor Is mapped to the physical control register, and the address of the physical control register is different from the address of the virtual register, and the physical control register has a function equivalent to the certain function, and the hardware of the processor. And writing a value to the address of the virtual register If the decree is executed, the corresponding value is written to the physical control register.

  According to this configuration, it is possible to provide a processor that can realize backward compatibility with the previous generation processor for the control register.

  According to the tenth aspect of the present invention, according to the compatible processor capable of executing the software executable by the previous generation processor, in the compatible processor, the bus use request is issued based on a plurality of factors. The bus use request issued by the previous generation processor is issued based on a plurality of factors, even within the previous generation processor. And the plurality of factors of the previous generation processor are a substantial subset of the factors of the compatible processor with respect to bus usage requirements during execution of the software. And the priority within the subset of the factors of the compatible processor is between the factors of the previous generation processor. The same as the priority.

  According to this configuration, it is possible to provide a compatible processor capable of realizing backward compatibility with the previous generation processor for bus arbitration.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is incorporated. In the present specification and drawings, when it is necessary to indicate which bit of a signal, [a: b] or [a] is added after the signal name. [A: b] means the a-th bit to the b-th bit of the signal, and [a] means the a-th bit of the signal. Hexadecimal numbers are expressed by adding “H” at the end of the numbers to distinguish them from decimal numbers. “0b” means a binary number, and “0x” means a hexadecimal number. For 1-bit signals, “1” is asserted (true) and “0” is negated (false) unless otherwise specified.

  FIG. 1 is a block diagram showing an overall configuration of a current generation processor 100 as a data processing apparatus according to an embodiment of the present invention.

  FIG. 5 is a block diagram showing the overall configuration of the previous generation processor 500 as the data processing apparatus according to the embodiment of the present invention.

  The current generation processor 100 according to the present embodiment includes software that can be executed by the previous generation processor 500 (hereinafter referred to as compatible software) and software that cannot be executed by the previous generation processor 500 (hereinafter referred to as non-software). Any software can be executed. That is, the current generation processor 100 has backward compatibility of software at the binary code level, that is, backward compatibility of the instruction set, with respect to the previous generation processor 500. First, an overview of the current generation processor 100 will be described, and then an overview of the previous generation processor 500 will be described.

  As shown in FIG. 1, the processor 100 includes a central processing unit (CPU) 1, a graphic processor 3, a pixel plotter 5, a sound processor 7, a DMA (direct memory access) controller 9, and a first bus arbiter 13. , Second bus arbiter 14, backup control circuit 15, main memory 17, timer circuit 19, A / D converter (ADC: analog to digital converter) 20, input / output control circuit 21, external memory interface circuit 23, clock driver 29, PLL A (phase-locked loop) circuit 27, a low voltage detection circuit 25, a first bus 31, and a second bus 33 are included.

  Here, in the present embodiment, when it is not necessary to distinguish between the main memory 17 and the external memories 45, 46, and 47, they are described as “memory MEMC”.

  The CPU 1 performs various calculations and control of the entire system according to a program stored in the memory MEMC. The CPU 1 is a bus master of the first bus 31 and the second bus 33 and can access resources connected to the respective buses.

  The graphic processor 3 is a bus master of the first bus 31 and the second bus 33, converts data stored in the memory MEMC into graphic data, and further adjusts it to a television receiver (not shown) based on this data. A video signal VD is generated and output.

  Here, the graphic data is synthesized from the background screen, the sprite, and the bitmap screen. The background screen has a two-dimensional array and has a size that covers the entire screen of the television receiver. Each array element is composed of a rectangular pixel set. A first background screen and a second background screen are prepared as background screens so that a deep background can be formed. A sprite consists of one rectangular pixel set that can be placed at any position on the screen of a television receiver. A rectangular pixel group constituting a background screen or sprite is called a character. The bitmap screen consists of a two-dimensional pixel array whose size and position can be freely set.

  An addressing mode when the graphic processor 3 fetches pattern data (character pattern data) of characters constituting a sprite from the memory MEMC will be described. Eight types of addressing modes are prepared. That is, 8-bit character number mode, 16-bit character number mode, 16-bit pointer mode with alignment, 16-bit address pointer mode, 24-bit address pointer mode, 16-bit extended character number mode, 16-bit extended address pointer mode, and with alignment A 24-bit pointer mode is prepared. Then, conversion to a real address is performed according to each mode as described below.

  2A is an explanatory diagram of the 8-bit character number mode, FIG. 2B is an explanatory diagram of the 16-bit character number mode, and FIG. 2C is an explanatory diagram of the 16-bit pointer mode with alignment.

  3A is an explanatory diagram of the 16-bit address pointer mode, and FIG. 3B is an explanatory diagram of the 24-bit address pointer mode.

  4A is an explanatory diagram of the 16-bit extended character number mode, FIG. 4B is an explanatory diagram of the 16-bit extended address pointer mode, and FIG. 4C is an explanatory diagram of the 24-bit pointer mode with alignment.

  As shown in FIG. 2A, in the 8-bit character number mode, characters are selected using 8-bit numbers. As shown in FIG. 2B, in the 16-bit character number mode, characters are selected using a 16-bit number.

  In these modes, a 24-bit base address (256-byte alignment, that is, all the lower 8 bits are all “0”) is generated from the 16-bit segment address stored in the 0th segment register. The real addresses arranged at the capacity of one character indicated by the bit number M of one pixel and the size information S are calculated. The bit number M of one pixel is information indicating a so-called color mode (M bits / pixel), and can be set to any value from 1 to 8. The size information S is information indicating the size of the character constituting the sprite, that is, how many pixels the character is composed of. If the horizontal size of the character is X pixels and the vertical size is Y pixels, the size information S = X × Y. For example, the horizontal size X is 8 pixels or 16 pixels, and the vertical size Y is 8 pixels or 16 pixels.

  Specifically, it is higher than the 24-bit address calculated by (base address) + (character number) × (number of bits of one pixel M) × (number of pixels of one character indicated by size information S) / 8. By adding 3 bits (0b000), a 27-bit real address is generated. Note that the division by “8” is because the real address is a byte address.

  In the 16-bit pointer mode with alignment, a character is selected by using a 16-bit address pointer with alignment. Specifically, as shown in FIG. 2C, a 24-bit base is generated from the 16-bit segment address stored in the K-th segment register (K = 0 to 7) indicated by the upper 3 bits of the aligned 16-bit pointer. An address (256 byte alignment, ie, all the lower 8 bits are “0”) is generated. 3 bits (0b000) above the 24-bit address that is the sum of this base address and the lower 13 bits of the aligned 16-bit pointer with 3 bits (0b000) added (8-byte alignment) Is added to generate a 27-bit real address (address pointer).

  In the 16-bit address pointer mode, characters are selected using a 16-bit address pointer. Specifically, as shown in FIG. 3A, a 24-bit base is generated from the 16-bit segment address stored in the J-th segment register (J = 0 to 15) indicated by the upper 4 bits of the 16-bit address pointer. An address (256 byte alignment, ie, all the lower 8 bits are “0”) is generated. Three bits (0b000) are added to the upper part of the 24-bit address that is the sum of the base address and the lower 12 bits of the 16-bit address pointer to generate a 27-bit real address.

  In the 24-bit address pointer mode, characters are selected using a 24-bit address pointer. Specifically, as shown in FIG. 3B, a value obtained by adding 3 bits (0b000) to the upper part of the 24-bit address pointer is a 27-bit real address (address pointer).

  The 16-bit extended character number mode is an extended version of the 16-bit character number mode. As shown in FIG. 4A, in this mode, a 27-bit base address (2K byte alignment, that is, all the lower 11 bits are “0”) generated from the 16-bit segment address stored in the 0th segment register. Based on the bit number M of one pixel and the size information S, real addresses arranged at every character capacity are calculated. A specific calculation method is the same as in the 16-bit character number mode.

  Specifically, a 27-bit real address (address pointer) by (base address) + (character number) × (number of bits of one pixel M) × (number of pixels of one character indicated by size information S) / 8 Is generated.

  The 16-bit extended address pointer mode is an extended version of the 16-bit address pointer mode. Specifically, as shown in FIG. 4B, the 27-bit base address (from the 16-bit segment address stored in the J-th segment register (J = 0 to 15) indicated by the upper 4 bits of the 16-bit address pointer) 2K byte alignment, that is, all the lower 11 bits are “0”). The sum of this base address and the lower 12 bits of the 16-bit address pointer is a 27-bit real address (address pointer).

  In the 24-bit pointer mode with alignment, as shown in FIG. 4C, the 24-bit pointer is the upper 24 bits of the 27-bit real address, and the lower 3 bits are occupied by “0” (8-byte alignment). Even if the lower 3 bits are set to “0”, the capacity of the smallest character pattern data is 8 bytes, and the capacity of the larger character pattern data is an integral multiple of 8 bytes, so there is no inconvenience. . Rather, this makes it possible to access a large address space with a limited number of bits.

  Returning to FIG. 1, the graphic processor 3 is controlled by the CPU 1 through the first bus 31 and has a function of generating an interrupt request signal INRQ to the CPU 1.

  The pixel plotter 5 is controlled by the CPU 1 through the first bus 31 and executes drawing of pixel data given from the CPU 1. In this case, drawing in units of pixels is possible. The pixel data here is data representing the display color of one pixel in M bits (M is an integer of 1 or more). In the present embodiment, examples where M = 1 to 8 are given.

  The pixel plotter 5 realizes high-speed drawing and efficient use of the buses (the first bus 31 and the second bus 33) by the cache system. Further, the pixel plotter 5 is a bus master of the first bus 31 and the second bus 33, and can autonomously write from a cache (not shown) to the memory MEMC and from the memory MEMC to the cache.

  The sound processor 7 is a bus master of the first bus 31 and the second bus 33, converts data stored in the memory MEMC into sound data, and further generates and outputs an audio signal AU based on the sound data.

  Sound data is synthesized by performing pitch conversion and amplitude modulation on PCM (pulse code modulation) data, which is a basic timbre. In the amplitude modulation, in addition to the volume control instructed by the CPU 1, a function for reproducing the waveform of the musical instrument is prepared.

  The sound processor 7 is controlled by the CPU 1 through the first bus 31 and has a function of generating an interrupt request signal INRQ to the CPU 1.

  The DMA controller 9 manages data transfer from the external memories 45, 46, 47 connected to the external bus 43 to the main memory 17. As the external memories 45, 46, 47, for example, any memory such as SRAM (static random access memory), DRAM (dynamic random access memory), or ROM (read only memory) can be used. Absent. The DMA controller 9 has a function of generating an interrupt request signal INRQ for the CPU 1 in order to notify the completion of data transfer. Further, the DMA controller 9 is a bus master of the first bus 31 and the second bus 33, and is controlled by the CPU 1 through the first bus 31.

  The main memory 17 includes necessary ones of a mask ROM, SRAM, and DRAM. In the present embodiment, the main memory 17 is composed of SRAM.

  The backup control circuit 15 deactivates the main memory 17 when a low voltage detection circuit 25 described later detects a low voltage. The main memory 17 is supplied with a power supply voltage from the battery 41. Therefore, even when the supply of the power supply voltages Vcc0 and Vcc1 is stopped, the data in the main memory 17 as the SRAM is retained.

  The first bus arbiter 13 receives a first bus use request signal from each bus master of the first bus 31, performs arbitration, and issues a first bus use permission signal to one bus master every bus cycle. Specifically, a plurality of priority information sets that determine priorities of a plurality of bus masters with respect to the first bus 31 are prepared, and the first bus arbiter 13 selects a plurality of priority information sets sequentially and cyclically. Then, arbitration is performed according to the selected priority order information set. Details will be described later.

  Each bus master is permitted to use the first bus 31 by receiving the first bus use permission signal. Here, the first bus use request signal and the first bus use permission signal are shown as a first bus arbitration signal FAB in FIG.

  The first bus 31 includes, for example, an 8-bit data bus 312 (described later), a 15-bit address bus 311 (described later), and a control bus 313 (described later).

  The second bus arbiter 14 receives the second bus use request signal from each bus master of the second bus 33, performs arbitration, and transfers the first bus master to one bus master every one or more bus cycles corresponding to the requested number of bytes. Issue 2 bus use permission signal. Specifically, a plurality of priority information sets that determine priorities of the plurality of bus masters with respect to the second bus 33 are prepared, and the second bus arbiter 14 selects the plurality of priority information sets sequentially and cyclically. Then, arbitration is performed according to the selected priority information set. Details will be described later.

  Each bus master is permitted to use the second bus 33 by receiving the second bus use permission signal. Here, the second bus use request signal and the second bus use permission signal are shown as the second bus arbitration signal SAB in FIG.

  The second bus 33 includes, for example, a 16-bit data bus, a 27-bit address bus, and a control bus (not shown).

  The timer circuit 19 has a function of generating an interrupt request signal INRQ for the CPU 1 based on a set time interval. The time interval and the like are set by the CPU 1 via the first bus 31.

  The ADC 20 converts an analog input signal into a digital signal. This digital signal is read by the CPU 1 via the first bus 31. Further, the ADC 20 has a function of generating an interrupt request signal INRQ for the CPU 1. An external analog signal is input to the ADC 20 via, for example, six analog ports AIN0 to AIN5 (not shown).

  The input / output control circuit 21 communicates with an external input / output device or an external semiconductor element via an input / output signal. Input / output signals are read / written from the CPU 1 via the first bus 31. The input / output control circuit 21 has a function of generating an interrupt request signal INRQ for the CPU 1. The input / output signals are input / output via, for example, programmable input / output ports IO0 to IO23 (not shown).

  The low voltage detection circuit 25 monitors the power supply voltages Vcc0 and Vcc1, and when any one of the power supply voltages falls below a predetermined voltage, a reset signal for the PLL circuit 27 and other system-wide reset signals. Issue a RSET.

  Here, the power supply voltage Vcc0 is, for example, +2.5 V, and is mainly supplied to a digital circuit in the processor 100. The power supply voltage Vcc1 is, for example, + 3.3V, and is mainly supplied to the analog circuit and the I / O unit in the processor 100.

  The PLL circuit 27 generates a high frequency clock signal obtained by multiplying the sine wave signal obtained from the crystal resonator 37.

  The clock driver 29 amplifies the high-frequency clock signal received from the PLL circuit 27 to a sufficient signal strength and supplies it to each block as the internal clock ICLK.

  The external memory interface circuit 23 has a function for connecting the second bus 33 to the external bus 43.

  A data transfer path in the processor 100 of FIG. 1 will be described. For example, the CPU 1 serving as the bus master has other function blocks (graphic processor 3, pixel plotter 5, sound processor 7, DMA controller 9, first bus arbiter 13, second bus arbiter 14, etc.) connected to the first bus 31 as a bus slave. Etc.), the write data to the control registers of these functional blocks is given to the first bus arbiter 13, and after arbitration, is given to each functional block from the first bus 31. On the other hand, read data from the control registers of these functional blocks is given to the CPU 1 via the first bus 31 and the first bus arbiter 13 after arbitration. However, the graphic processor 3, the pixel plotter 5, the sound processor 7, and the DMA controller 9 have a function of making a bus use request to the first bus arbiter 13 as a bus master of the first bus 31.

  When the bus master accesses the main memory 17, the write data is given to the first bus arbiter 13, and after arbitration, is given from the first bus 31 to the main memory 17. On the other hand, the read data is given to the bus master via the first bus 31 and the first bus arbiter 13 after arbitration. When the bus master accesses the external memories 45 to 47, the write data is given to the second bus arbiter 14, and after arbitration, the second bus 33 passes through the external memory interface circuit 23 and the external bus 43. To the external memory. On the other hand, the read data is given to the bus master via the external bus 43, the external memory interface circuit 23, the second bus 33, and the second bus arbiter 14 after arbitration.

  Referring to FIG. 5, a processor 500 includes a central processing unit (CPU) 501, a graphic processor 503, a sound processor 507, a DMA controller 509, a first bus arbiter 513, a second bus arbiter 514, a main memory 517, and a timer circuit 519. , A / D converter (ADC) 520, input / output control circuit 521, external memory interface circuit 523, clock driver 529, PLL circuit 527, low voltage detection circuit 525, first bus 531, second bus 533, and DRAM refresh control A circuit 522 is included.

  Here, in this embodiment, when it is not necessary to distinguish between the main memory 517 and the external memories 545, 546, and 547, they are expressed as “memory MEMP”.

  The CPU 501 performs various calculations and control of the entire system according to a program stored in the memory MEMP. The CPU 501 is a bus master of the first bus 531 and the second bus 533, and can access resources connected to the respective buses.

  The graphic processor 503 is a bus master of the first bus 531 and the second bus 533, converts data stored in the memory MEMP into graphic data, and further adjusts it to a television receiver (not shown) based on this data. A video signal VD is generated and output.

  Here, the graphic data is synthesized from the background screen and the sprite. Similar to the current generation processor 100, a first background screen and a second background screen are prepared as background screens.

  An addressing mode when the graphic processor 503 fetches character pattern data constituting a sprite from the memory MEMP will be described. Five types of addressing modes are prepared. That is, an 8-bit character number mode, a 16-bit character number mode, a 16-bit pointer mode with alignment, a 16-bit address pointer mode, and a 24-bit address pointer mode are prepared. These modes are the same as the 8-bit character number mode, 16-bit character number mode, aligned 16-bit pointer mode, 16-bit address pointer mode, and 24-bit address pointer mode in the current generation processor 100. However, the real address (address pointer) finally generated is 24 bits. This is because the logical address space of the current generation processor 100 is narrower. Therefore, unlike the current generation processor 100, 3 bits (0b000) are not added to the upper order.

  The graphic processor 503 is controlled by the CPU 501 through the first bus 531 and has a function of generating an interrupt request signal INRQ to the CPU 501.

  The sound processor 507 is a bus master of the first bus 531 and the second bus 533, converts data stored in the memory MEMP into sound data, and further generates and outputs an audio signal AU based on the sound data.

  The sound processor 507 is controlled by the CPU 501 through the first bus 531 and has a function of generating an interrupt request signal INRQ to the CPU 501.

  The DMA controller 509 manages data transfer from the external memories 545 to 547 connected to the external bus 543 to the main memory 517. As the external memories 545 to 547, any memory can be used similarly to the external memories 45 to 47, and the number thereof is not limited. The DMA controller 509 has a function of generating an interrupt request signal INRQ for the CPU 501 in order to notify the completion of data transfer. Further, the DMA controller 509 is a bus master of the first bus 531 and the second bus 533, and is controlled by the CPU 1 through the first bus 531.

  The main memory 517 includes necessary ones among a mask ROM, an SRAM, and a DRAM.

  The first bus arbiter 513 receives a first bus use request signal from each bus master of the first bus 531, performs arbitration, and issues a first bus use permission signal to one bus master every bus cycle. Specifically, a plurality of priority information sets that determine priorities of the plurality of bus masters with respect to the first bus 531 are prepared, and the first bus arbiter 513 selects the plurality of priority information sets sequentially and cyclically. Then, arbitration is performed according to the selected priority order information set.

  Each bus master is permitted to use the first bus 531 by receiving the first bus use permission signal. Here, the first bus use request signal and the first bus use permission signal are shown as a first bus arbitration signal FAB in FIG.

  The first bus 531 includes, for example, an 8-bit data bus, a 15-bit address bus, and a control bus (not shown).

  The second bus arbiter 514 receives the second bus use request signal from each bus master of the second bus 533, performs arbitration, and issues a second bus use permission signal to one bus master every bus cycle. Specifically, a plurality of priority information sets that determine the priority order of the plurality of bus masters with respect to the second bus 533 are prepared, and the second bus arbiter 514 sequentially and cyclically selects the plurality of priority information sets. Then, arbitration is performed according to the selected priority information set.

  Each bus master is permitted to use the second bus 533 by receiving the second bus use permission signal. Here, the second bus use request signal and the second bus use permission signal are shown as a second bus arbitration signal SAB in FIG.

  The second bus 533 includes, for example, an 8-bit data bus, a 24-bit address bus, and a control bus (not shown).

  The timer circuit 519 has a function of generating an interrupt request signal INRQ for the CPU 501 based on a set time interval. The time interval and the like are set by the CPU 501 via the first bus 531.

  The ADC 520 converts an analog input signal into a digital signal. This digital signal is read by the CPU 501 via the first bus 531. The ADC 520 has a function of generating an interrupt request signal INRQ to the CPU 501. Note that an external analog signal is input to the ADC 520 via, for example, six analog ports AIN0 to AIN5 (not shown).

  The input / output control circuit 521 performs communication with an external input / output device or an external semiconductor element via an input / output signal. Input / output signals are read / written from the CPU 501 via the first bus 531. The input / output control circuit 521 has a function of generating an interrupt request signal INRQ for the CPU 501. The input / output signals are input / output via, for example, programmable input / output ports IO0 to IO15.

  The low voltage detection circuit 525 monitors the power supply voltage Vcc and issues a reset signal for the PLL circuit 527 and other system-wide reset signals RSET when the power supply voltage Vcc falls below a certain voltage. In addition, when the main memory 517 is constituted by an SRAM and the data retention of the SRAM by the battery 541 is required, the battery backup control signal BCTL is issued when the power supply voltage Vcc is equal to or lower than a predetermined voltage. .

  The PLL circuit 527 generates a high frequency clock signal obtained by multiplying the sine wave signal obtained from the crystal resonator 537.

  The clock driver 529 amplifies the high frequency clock signal received from the PLL circuit 527 to a sufficient signal strength and supplies the amplified signal to each block as the internal clock ICLK.

  The external memory interface circuit 523 controls the bus cycle length of the second bus 533 by issuing a function for connecting the second bus 533 to the external bus 543 and a cycle end signal CYL of the second bus 533. It has a function.

  The DRAM refresh control circuit 522 unconditionally acquires the right to use the first bus 531 at regular intervals, and performs a DRAM refresh operation. The DRAM refresh control circuit 522 is provided when the main memory 517 includes a DRAM.

  Further, the previous generation processor 500 does not have a device corresponding to the pixel plotter 5 included in the current generation processor 100.

  Next, the logical address space of the previous generation processor 500 will be described, and then the logical address space of the current generation processor 100 will be described.

  The previous generation processor 500 has a 24-bit address signal, ie, a 16 megabyte logical address space. The first bus 531 has a 15-bit address, that is, a physical address space of 32 kilobytes. The second bus 533 has a 12-megabyte physical address space obtained by removing a part from the 24-bit address space. These points will be described with reference to the drawings.

  FIG. 6 is an explanatory diagram of the logical address space of the processor 500 of the previous generation shown in FIG. As shown in FIG. 6, the 24-bit address is roughly divided into upper 8 bits and lower 16 bits, and the upper 8-bit address functions as a bank address. That is, the 16 megabyte logical address space is divided into 256 unit spaces called 64 kilobyte banks. For example, the FFFFh address of 00h bank and the 0000h address of 01h bank are for CPU 501 and sound processor 507. Are not continuous. Therefore, in FIG. 6, in order to express this clearly, each bank is shown in parallel.

  The logical address space of the processor 500 is roughly divided into four areas, the first bus area corresponding to the physical address space of the first bus 531 and the second bus 0th corresponding to the physical address space of the second bus 533, respectively. An area, a second bus first area, and a second bus second area.

  The second bus 0th area is assigned to the external memory 545, the second bus first area is assigned to the external memory 546, and the second bus second area is assigned to the external memory 547.

  When the second bus address supplied from the second bus 533 indicates the second bus 0th area, the external memory interface circuit 523 asserts the 0th area select signal ASSEL0, and the second bus address is When the second bus first area is indicated, the first area select signal ASSEL1 is asserted. When the second bus address indicates the second bus second area, the second area select signal ASSEL2 is asserted. To do. When the 0th area select signal ASSEL0 is asserted, the external memory 545 is activated. When the first area select signal ASSEL1 is asserted, the external memory 546 is activated and the second area select signal ASSEL2 is activated. Is asserted, the external memory 547 is activated.

  On the other hand, the current generation processor 100 has a 27-bit address signal, that is, a logical address space of 128 megabytes. The first bus 31 has a 15-bit address, that is, a physical address space of 32 kilobytes. The second bus 33 has a 96 megabyte physical address space obtained by removing a part from the 27-bit address space. These points will be described with reference to the drawings.

  FIG. 7 is an explanatory diagram of the logical address space of the current generation processor 100 shown in FIG. As shown in FIG. 7, the 27-bit address is roughly divided into upper 11 bits and lower 16 bits, and the upper 11-bit address functions as a bank address. That is, the 128 megabyte logical address space is divided into 2048 unit spaces called 64 kilobyte banks. For example, the FFhh address of the 000h bank and the 0000h address of the 001h bank are for the CPU 1 and the sound processor 7. Are not continuous. Therefore, in FIG. 7, in order to express this clearly, each bank is shown in parallel.

  The logical address space of the processor 100 is roughly divided into four areas, the first bus area corresponding to the physical address space of the first bus 31 and the second bus No. 0 corresponding to the physical address space of the second bus 33, respectively. An area, a second bus first area, and a second bus second area.

  The second bus 0th area is assigned to the external memory 45, the second bus first area is assigned to the external memory 46, and the second bus second area is assigned to the external memory 47.

  The second bus arbiter 14 asserts the first area select signal ASSEL1 when the second bus address given from the second bus 33 points to the second bus first area, and the second bus address is changed to the second bus address. When the second bus second area is indicated, the second area select signal ASSEL2 is asserted.

  When the first area select signal ASSEL1 is asserted, the external memory 46 is activated, and when the second area select signal ASSEL2 is asserted, the external memory 47 is activated.

  The 0th area select signal ASSEL0 is substituted by the second bus address [22]. If the second bus address [22] indicates “0”, the external memory 45 is activated.

  As shown in FIGS. 6 and 7, in the logical address space of the current-generation processor 100 consisting of 27-bit addresses, the mapping of the space in which the upper 3 bits indicate “0b000” is mapped from the 24-bit address of the previous-generation processor 500. It is the same as the mapping of the logical address space. Therefore, in the current generation processor 100, software that can be executed in the previous generation processor 500 (that is, compatible software) can be executed as it is. That is, compatibility at the binary code level of software is maintained.

  In the current generation processor 100, among the bus masters mounted in the previous generation processor 500, the CPU 1, the sound processor 7, and the DMA controller 9 always have the expanded upper 3-bit address output as “0b000”. By doing so, the compatibility of the mapping is maintained.

  However, in the graphic processor 3, there are three types of addressing modes (16-bit extended character number mode, 16-bit extended address pointer mode, and 24-bit pointer with alignment) in the five types of addressing modes in the graphic processor 503 of the previous generation processor 500. Therefore, in the sprite and background screen character data fetching by the graphic processor 3, addressing using all 27 bits is possible only when these added addressing modes are used. Further, the pixel plotter 5 which is a bus master newly added from the previous generation processor 500 to the current generation processor 100 can access the entire 27-bit address space.

  Next, details of arbitration by the first bus arbiter 513 of the previous generation processor 500 will be described, and then details of arbitration by the first bus arbiter 13 of the current generation processor 100 will be described.

  FIG. 8 is a view for showing an example of a priority table included in the first bus arbiter 513 of FIG. As shown in FIG. 8, four priority information sets are selected as priority information for access to the first bus 531, each of which indicates one of the four sets. 3 encoded. FIG. 8 shows an example in which the priority order table converts priority order information numbers 0 to 3 to corresponding priority order information sets. One priority information set is constituted by the first to fourth priorities. The priority of the access to the first bus 531 is the highest in the first priority, and the priority becomes lower as the number increases. The first bus arbiter 513 sequentially and cyclically selects the 16 priority registers holding any of the priority information numbers 0 to 3. The first bus arbiter 513 then excludes the bus masters that are currently using the first bus 531 from the bus masters that are requesting the first bus use according to the priority information set corresponding to the selected priority information number. The bus master having the highest priority is selected and the first bus use permission is given. However, the DRAM refresh control circuit 522, which is a privileged bus master, is excluded from the arbitration target and treated with priority.

  FIG. 9 is a diagram showing a list of hardware control registers provided in the first bus arbiter 513 of FIG. 2 and mapped to the address space of the first bus of the processor 500 of the previous generation. As shown in FIG. 9, the first bus arbiter 513 includes a 0th slot priority register to a 15th slot priority register. Each register holds information obtained by encoding the priority information number in FIG. The CPU 1 can change the held priority information number by accessing these registers. Note that these registers are arranged in the physical address space of the first bus 531 of the previous generation processor 500 at the position indicated by the corresponding first bus address in the figure.

  FIG. 10 is a view for showing an example of a priority table included in the first bus arbiter 13 of FIG. As shown in FIG. 10, four priority information sets are prepared as priority information for access to the first bus 31, each of which indicates a 2-bit priority information number 0 to 3 indicating one of the four sets. Is encoded. In FIG. 10, the priority table converts the priority information numbers 0 to 3 into corresponding priority information sets.

  Here, the bus master (CPU 1, graphic processor 3, pixel plotter 5, sound processor 7, and DMA controller 9) is called a factor that requests the use of the first bus 31 (hereinafter referred to as “first bus use request factor”). ) Make a bus use request every time. Accordingly, each of the priority information sets indicated by the priority information numbers 0 to 3 indicates the priority of all the first bus use request factors. In the present embodiment, since there are twelve types of first bus use request factors, each of the priority order information sets is constituted by the first priority order 1 to the twelfth priority order. The priority of access to the first bus 31 is the highest in the first priority, and the priority becomes lower as the number increases. The first bus arbiter 13 sequentially and cyclically selects the 16 priority registers holding any of the priority information numbers 0 to 3, and sets the priority information numbers held in the selected priority registers. Access arbitration to the first bus 31 is performed according to the corresponding priority information set. In this case, the first bus arbiter 13 performs access arbitration for each first bus use request factor.

  Here, in the figure, the abbreviations “CPU”, “GP”, “SP”, “DMA”, and “PLT” of the bus master are CPU1, graphic processor 3, sound processor 7, DMA controller 9, and pixel plotter, respectively. 5 is shown.

  In the figure, the abbreviations “IST”, “DAT”, “TX1”, “TX2”, “SPR”, “HDR”, “CHR”, “BMP”, “WAV”, “ “ENV”, “DMAD”, and “PLT” are “instruction fetch”, “data access”, “first background array data”, “second background array data”, “sprite DMA”, “character”, respectively. “Header”, “Character data”, “Bitmap data”, “Wave data”, “Envelope data”, “DMA destination”, and “Pixel plotter” are shown. The meaning of each first bus use request factor is as follows.

  “Instruction fetch” means that the CPU 1 fetches an instruction from the main memory 17 as a first bus use request factor.

  “Data access” means that the CPU 1 accesses a resource connected to the first bus 31 (data read / write) is the first bus use request factor.

  The “first background array data” means that the graphic processor 3 acquires the array data of the first background screen from the main memory 17 as a first bus use request factor. The array data in this case consists of pattern data address information of all characters of the first background screen, and may include color palette information and depth information.

  The “second background array data” means that the graphic processor 3 acquires the array data of the second background screen from the main memory 17 as a first bus use request factor. The array data in this case consists of pattern data address information of all characters of the second background screen, and may include color palette information and depth information.

  “Sprite DMA” indicates that the first bus use request factor is that the graphic processor 3 reads data to be transferred from the main memory 17 to the sprite memory (not shown, but arranged inside the graphic processor 3). means.

  “Character header” means that the graphic processor 3 acquires the character header from the main memory 17 as a first bus use request factor. The character header includes color palette information, information on the number of bits of one pixel (N bits / pixel) of the character, flip information, and the like.

  “Character data” means that the graphic processor 3 acquires character pattern data from the main memory 17 as a first bus use request factor.

  “Bitmap data” means that the graphic processor 3 reads bitmap data from the main memory 17 as a first bus use request factor.

  “Wave data” means that the acquisition of wave data from the main memory 17 by the sound processor 7 is the first bus use request factor.

  “Envelope data” is obtained when the sound processor 7 obtains envelope data from the main memory 17, or a read pointer of an envelope FIFO (first-in first-out) virtually configured in the main memory 17. This means that writing is the first bus use request factor.

  “DMA destination” means that the DMA controller 9 writes data to the main memory 17 as a first bus use request factor.

  “Pixel plotter” means that the pixel plotter 5 reads / writes to / from the main memory 17 as a first bus use request factor.

  Here, a method of creating the priority table in FIG. 10 will be described. The bus usage request factor permutation (referred to as bus usage request factor permutation) is obtained for each bus master, and one bus usage request factor permutation is selected for each bus master in consideration of the amount of data transfer and the frequency of bus usage. To do.

  Then, by combining the bus use request factor permutation and the priority order in the priority table used by the first bus arbiter 513 of the previous generation processor 500 shown in FIG. 8, the current generation processor 100 shown in FIG. A priority table used by the first bus arbiter 13 is created. A specific example will be described.

  Taking the priority information number 0 in FIG. 8 as an example, the priority is {SP, GP, DMA, CPU} using the abbreviations in FIG. This is called a bus master permutation. Also, using the abbreviations in FIG. 10, the bus use request factor permutation selected for the sound processor 7 is {WAV, ENV}, and the bus use request factor permutation selected for the graphic processor 3 is {BMP, CHR, HDR, SPR, TX1, TX2} and the bus use request factor permutation for the pixel plotter 5 is {PLT} (because the bus use request factor for the first bus 31 of the pixel plotter 5 is 1). The bus use request factor permutation for the DMA controller 9 is {DMAD} (for the same reason as the pixel plotter 5), and the bus use request factor permutation selected for the CPU 1 is {DAT, IST }.

  Then, the bus use request factor permutation {WAV, ENV} for the bus master permutation SP, the bus use request factor permutation {BMP, CHR, HDR, SPR, TX1, TX2} for the bus master permutation GP, and the bus master permutation The bus use request factor permutation {DMAD} is replaced for the DMA of the bus master, and the bus use request factor permutation {DAT, IST} is replaced for the CPU of the bus master permutation, and the bus use request factor permutation {PLT} of the bus master PLT is appropriately positioned. In addition to the priority information number 0 of the previous generation processor 500 shown in FIG. 8, the bus use request factor for the first bus arbiter 13 of the current generation processor 100 shown in FIG. A permutation (priority information number 0) is obtained. The insertion of the bus use request factor permutation {PLT} does not affect the order relationship of other bus masters. As a result, as shown in FIG. 10, a priority information set corresponding to priority information number 0 is created. Similarly, priority information sets corresponding to priority information numbers 1 to 3 in FIG. 10 are created based on priority information sets corresponding to priority information numbers 1 to 3 in FIG.

  As described above, in the current generation processor 100, the factor for requesting access to the first bus is significantly increased compared to the previous generation processor 500, but the previous generation priority table shown in FIG. Based on the priority order in each priority order information set of the current generation in FIG. 10, the software compatibility can be maintained.

  By the way, the pixel plotter 5 is a bus master that is not provided in the previous generation processor 500, but is a bus master related to image processing and rarely accesses the first bus 31. Prioritized after bus use request factors. Note that even if the pixel plotter 5 is included in the priority information set of the first bus 31 in the current generation processor 100, the previous generation processor 500 does not have a pixel plotter. A pixel plotter is never used and has no effect on maintaining compatibility.

  FIG. 11 is a diagram showing a list of hardware control registers provided in the first bus arbiter 13 of FIG. 1 and mapped to the address space of the first bus of the processor 100 of the current generation. As shown in FIG. 11, the first bus arbiter 13 includes a 0th slot priority register to a 15th slot priority register. Each register holds a priority information number obtained by encoding the priority information number shown in FIG. The CPU 1 can change the held priority information number by accessing these registers. These registers are arranged in the physical address space of the first bus 31 of the current generation processor 100 at the position indicated by the corresponding first bus address in the figure.

  As is apparent from FIGS. 9 and 11, the configuration and mapping of the control registers are the same in the first bus arbiter 31 of the current generation and the first bus arbiter 531 of the previous generation.

  Next, details of arbitration by the second bus arbiter 514 of the previous generation processor 500 will be described, and then details of arbitration by the second bus arbiter 14 of the current generation processor 100 will be described.

  FIG. 12 is a view for showing an example of a priority table included in the second bus arbiter 514 of FIG. As shown in FIG. 12, four priority information sets are selected as the priority information for access to the second bus 533, each of which indicates a 2-bit priority information number 0-3 indicating one of the four sets. Is encoded. In FIG. 12, the priority table converts the priority information numbers 0 to 3 into corresponding priority information sets. One priority information set is constituted by the first to fourth priorities. As for the priority of access to the second bus 533, the first priority is the highest, and the priority decreases as the number increases. The second bus arbiter 514 sequentially and cyclically selects eight priority registers holding any of the priority information numbers 0 to 3. The second bus arbiter 514 then excludes the bus masters that are currently using the second bus 533 among the bus masters requesting the second bus use according to the priority information set corresponding to the selected priority information number. The bus master having the highest priority is selected and the second bus use permission is given.

  FIG. 13 is a diagram showing a list of hardware control registers provided in the second bus arbiter 514 of FIG. 2 and mapped to the address space of the first bus of the processor 500 of the previous generation. As shown in FIG. 13, the second bus arbiter 514 includes a 0th slot priority order register to a seventh slot priority order register. Each register holds information obtained by encoding the priority information number in FIG. The CPU 501 can change the priority information number held by accessing these registers. Note that these registers are arranged in the physical address space of the first bus 531 of the previous generation processor 500 at the position indicated by the corresponding first bus address in the figure.

  FIG. 14 is a view showing an example of a priority table that the second bus arbiter 14 of FIG. 1 has. As shown in FIG. 14, four priority information sets are selected as the priority information of access to the second bus 33, and each of them indicates a 2-bit priority information number 0-3 indicating one of the four sets. Is encoded. FIG. 14 shows an example of a priority table that converts priority information numbers 0 to 3 into corresponding priority information sets.

  Here, the bus master (CPU 1, graphic processor 3, pixel plotter 5, sound processor 7, and DMA controller 9) is called a factor that requests the use of the second bus 33 (hereinafter referred to as “second bus use request factor”). ) Make a bus use request every time. Therefore, each of the priority information sets indicated by the priority information numbers 0 to 3 indicates the priority of all the second bus use request factors. In the present embodiment, since there are nine types of second bus use request factors, each of the priority order information sets is constituted by the first priority order 1 to the ninth priority order. The priority of access to the second bus 33 is the highest in the first priority, and the priority becomes lower as the number increases. The second bus arbiter 14 sequentially and cyclically selects eight priority registers holding any of the priority information numbers 0 to 3, and sets the priority information numbers held in the selected priority registers. Access arbitration to the second bus 33 is performed according to the corresponding priority information set. In this case, the second bus arbiter 14 performs access arbitration for each second bus use request factor.

  Here, in the figure, the abbreviations of the bus master and the second bus use request factor are the same as those in FIG. However, the abbreviation “DMAS” of the second bus use request factor indicates “DMA source”, and the meaning of each second bus use request factor is as follows.

  “Instruction fetch” means that the CPU 1 fetches an instruction from the external memories 45 to 47 is the second bus use request factor.

  “Data access” means that the CPU 1 accesses the external memories 45 to 47 (data read / write) as a second bus use request factor.

  “Character header” means that the graphic processor 3 obtains the character header from the external memories 45 to 47 as a second bus use request factor.

  “Character data” means that the graphic processor 3 acquires character pattern data from the external memories 45 to 47 as a second bus use request factor.

  “Bitmap data” means that the graphic processor 3 acquires bitmap data from the external memories 45 to 47 as a second bus use request factor.

  “Pixel plotter” means that the pixel plotter 5 reads / writes to / from the external memories 45 to 47 as a second bus use request factor.

  “Wave data” means that the acquisition of wave data from the external memories 45 to 47 by the sound processor 7 is the second bus use request factor.

  “Envelope data” means that the acquisition of envelope data from the external memories 45 to 47 by the sound processor 7 is the second bus use request factor.

  “DMA source” means that the DMA controller 9 reads data from the external memories 45 to 47 as a second bus use request factor.

  Here, a method of creating the priority table in FIG. 14 will be described. The bus usage request factor permutation (referred to as bus usage request factor permutation) is obtained for each bus master, and one bus usage request factor permutation is selected for each bus master in consideration of the amount of data transfer and the frequency of bus usage. To do.

  Then, by combining the bus use request factor permutation and the priority order in the priority order table used by the second bus arbiter 514 of the previous generation processor 500 shown in FIG. 12, the current generation processor 100 shown in FIG. A priority table used by the second bus arbiter 14 is created. A specific example will be described.

  Taking the priority information number 0 in FIG. 12 as an example, the priority is {SP, GP, DMA, CPU} using the abbreviations in FIG. This is called a bus master permutation. Further, using the abbreviations of FIG. 14, the bus use request factor permutation selected for the sound processor 7 is {WAV, ENV}, and the bus use request factor permutation selected for the graphic processor 3 is {BMP, CHR, HDR}, the bus use request factor permutation for the pixel plotter 5 is {PLT} (because there is one bus use request factor for the second bus 33 of the pixel plotter 5). Assume that the bus use request factor permutation for the DMA controller 9 is {DMAS} (for the same reason as the pixel plotter 5), and the bus use request factor permutation selected for the CPU 1 is {DAT, IST}.

  The bus use request factor permutation {WAV, ENV} is assigned to the bus master permutation SP, the bus use request factor permutation {BMP, CHR, HDR} is assigned to the bus master permutation GP, and the bus master permutation DMA is assigned to the bus. When the use request factor sequence {DMAS} is replaced with the bus use request factor sequence {DAT, IST} for the CPU in the bus master sequence, and the bus use request factor sequence {PLT} of the bus master PLT is added to an appropriate position, FIG. 14 corresponds to the priority information number 0 of the previous generation processor 500 shown in FIG. 14, and the bus use request factor permutation (priority information number) for the second bus arbiter 14 of the current generation processor 100 shown in FIG. 0) is obtained. The insertion of the bus use request factor permutation {PLT} does not affect the order relationship of other bus masters. As a result, as shown in FIG. 14, a priority information set corresponding to priority information number 0 is created. Similarly, based on the priority information sets corresponding to the priority information numbers 1 to 3 in FIG. 12, the priority information sets corresponding to the priority information numbers 1 to 3 in FIG. 14 are created.

  As described above, in the current generation processor 100, the second bus access request factor is significantly increased compared to the previous generation processor 500, but the previous generation priority table shown in FIG. Based on the priority order set in each priority order information set of the current generation in FIG. 14, the software compatibility can be maintained. Even if the pixel plotter 5 is included in the priority order information set of the second bus 33 in the current generation processor 100, the previous generation processor 500 does not have a pixel plotter. A pixel plotter is never used and has no effect on maintaining compatibility.

  FIG. 15 is a diagram showing a list of hardware control registers provided in the second bus arbiter 14 of FIG. 1 and mapped to the address space of the first bus of the processor 100 of the current generation. As shown in FIG. 15, the second bus arbiter 14 includes a 0th slot priority register to a seventh slot priority register. Each register holds a priority information number obtained by encoding the priority information number shown in FIG. The CPU 1 can change the held priority information number by accessing these registers. These registers are arranged in the physical address space of the first bus 31 of the current generation processor 100 at the position indicated by the corresponding first bus address in the figure.

  As apparent from FIGS. 13 and 15, the configuration and mapping of the control registers holding the priority information numbers are the same in the second bus arbiter 33 of the current generation and the second bus arbiter 533 of the previous generation.

  In the previous generation processor 500, the access speed for the second bus 533 can be set. Specifically, the CPU 501 accesses the “0th area access cycle number register” of FIG. 13 and the first and second area access cycle number registers, thereby performing the “second bus 0th area” and “ The bus cycle length can be determined by the number of cycles of the internal clock ICLK (2 to 8 cycles) for the “2 bus first area and second bus second area”. However, since the previous generation processor 500 does not support the page mode, the bus cycle length for each area is always constant unless the setting is changed.

  On the other hand, the current generation processor 100 can also set the access speed for the second bus 33. However, in the current generation processor 100, the CPU 1 has the 0th area page size register, the 1st area page size register, the 2nd area page size register, the 0th area page access cycle number register, and the first area page access shown in FIG. Cycle number register, second area page access cycle number register, zeroth area random access cycle number register, first area random access cycle number register, second area random access cycle number register, zeroth area bus width register, first area By accessing the bus width register and the second area bus width register, three areas of “second bus 0 area”, “second bus first area”, and “second bus second area” in FIG. Respectively, page size, number of page access cycles, random access cycles , And the data bus width (8-bit / 16-bit) can be determined.

  As described above, in the previous generation processor 500, only the number of access cycles can be set for the second bus 533, whereas in the current generation processor 100, the page size, the number of page access cycles, the random number The number of access cycles and the data bus width can be determined. Moreover, in the previous generation processor 500, the second bus first area and the second bus second area have the same setting of the number of access cycles, whereas in the current generation processor 100, the second bus second area. Independent setting is possible for each of the first area and the second area of the second bus.

  As shown in FIG. 15, in the current generation processor 100, a virtual 0th area corresponding to the 0th area access cycle number register and the first and second area access cycle number registers of the previous generation processor 500 shown in FIG. The area access cycle number register and the virtual first and second area access cycle number registers are arranged at the same first bus address as the processor 500 of the previous generation.

  When the CPU 1 of the current generation processor 100 writes a value on the first bus address where the virtual 0th area access cycle number register is arranged, the same value is written to the 0th area random access cycle number register, The value of the 0th area page size register is set to “0” (page size = 0 byte), and access in the page mode is not performed. Similarly, when the CPU 1 of the current generation processor 100 writes a value on the first bus address where the virtual first and second area access cycle number registers are arranged, the same value is obtained as the first area random access cycle number. The value is written in the register and the second area random access cycle number register, and the values of the first area page size register and the second area page size register are set to “0” (page size = 0 byte), respectively. Access will not be performed.

  As described above, the current generation processor 100 can realize backward compatibility of software with respect to the previous generation processor 500. In the current generation processor 100, unlike the previous generation processor 500, the number of access cycles is set independently for the second bus first area and the second bus second area. When a value is written on the first bus address where the second area access cycle number register is arranged, the same value is written to the first area random access cycle number register and the second area random access cycle number register, respectively. It will not interfere with maintaining compatibility.

  Here, the term “virtual” is used in the processor 100 because the 0th area access cycle number register and the first and second area access cycle number registers do not exist as entities.

  As can be seen from FIGS. 13 and 15, the register requesting to open the external bus 543 in the previous generation processor 500 and the register requesting to open the external bus 43 in the current generation processor 100 have the same configuration and Mapping.

  Next, the first bus arbiter 13 of FIG. 1 will be described in more detail.

  FIG. 16 is an explanatory diagram of input / output signals for the first bus arbiter 13 of FIG. Referring to FIG. 16, instruction fetch address IIFA from CPU 1 to first bus arbiter 13, instruction fetch bus request signal IIFB from CPU 1 to first bus arbiter 13, and instruction fetch / read from first bus arbiter 13 to CPU 1 The permission signal IIFRG receives a read address, a signal indicating a read bus use request, and a read bus use request when the first bus use request factor is “instruction fetch”, and the internal data IDAI [7: 0] is a signal indicating that fetching is possible.

  Data access address IDAA from CPU 1 to first bus arbiter 13, data access / write data IDA from CPU 1 to first bus arbiter 13, data access bus request signal IDAB from CPU 1 to first bus arbiter 13, CPU 1 to first bus arbiter The data access / write request signal IDAWR to 13, the data access / write acceptance signal IDAWG from the first bus arbiter 13 to the CPU 1, and the data access / read permission signal IDARG from the first bus arbiter 13 to the CPU 1, respectively. Read address or write address when the use request factor is “data access”, data to be written, a signal indicating a read or write bus use request, a signal indicating that the bus use request is a write request, a write Signal indicating that the use request is received, and the read bus use request is accepted, the internal data IDAI [7: 0] is a signal, indicating that it is possible fetch.

  A first background array data address FBGA from the graphic processor 3 to the first bus arbiter 13, a first background array data bus request signal FBGB from the graphic processor 3 to the first bus arbiter 13, and a graphic processor from the first bus arbiter 13 The first background array data / read permission signal FBGRG 3 is a read address when the first bus use request factor is “first background array data”, a signal indicating a read bus use request, and a read Is a signal indicating that the internal data IDAI [7: 0] can be fetched.

  The second background array data address SBGA from the graphic processor 3 to the first bus arbiter 13, the second background array data bus request signal SBGB from the graphic processor 3 to the first bus arbiter 13, and the graphic processor from the first bus arbiter 13 The second background array data / read permission signal SBGRG to 3 is a read address, a signal indicating a read bus use request, and a read when the first bus use request factor is “second background array data”, respectively. Is a signal indicating that the internal data IDAI [7: 0] can be fetched.

  Sprite DMA address ISPA from graphic processor 3 to first bus arbiter 13, sprite DMA bus request signal ISPB from graphic processor 3 to first bus arbiter 13, and sprite DMA read permission from first bus arbiter 13 to graphic processor 3 The signal ISPRG receives a read address, a signal indicating a read bus use request, and a read bus use request when the first bus use request factor is “sprite DMA”, and the internal data IDAI [7: 0]. ] Is a signal indicating that fetching is possible.

  Character header address ICHA from the graphic processor 3 to the first bus arbiter 13, character header / bus request signal ICHB from the graphic processor 3 to the first bus arbiter 13, and character header read permission from the first bus arbiter 13 to the graphic processor 3 The signal ICHRG receives the read address when the first bus use request factor is “character header”, the signal indicating the read bus use request, and the read bus use request, and receives the internal data IDAI [7: 0]. ] Is a signal indicating that fetching is possible.

  Character data address ICDA from the graphic processor 3 to the first bus arbiter 13, character data bus request signal ICDB from the graphic processor 3 to the first bus arbiter 13, and character data read permission from the first bus arbiter 13 to the graphic processor 3 The signal ICDRG receives the read address, the signal indicating the read bus use request, and the read bus use request when the first bus use request factor is “character data”, and the internal data IDAI [7: 0]. Is a signal indicating that fetching is possible.

  Bitmap data address IBMA from the graphic processor 3 to the first bus arbiter 13, Bitmap data bus request signal IBMB from the graphic processor 3 to the first bus arbiter 13, and Bitmap data from the first bus arbiter 13 to the graphic processor 3 The read permission signal IBMRG receives the read address, the signal indicating the read bus use request, and the read bus use request when the first bus use request factor is “bitmap data”, and receives the internal data IDAI. [7: 0] is a signal indicating that fetching is possible.

  Pixel plotter address IPPA from the pixel plotter 5 to the first bus arbiter 13, pixel plotter write data IPPW from the pixel plotter 5 to the first bus arbiter 13, and pixel plotter bus request signal IPPB from the pixel plotter 5 to the first bus arbiter 13. The pixel plotter / write request signal IPPWR from the pixel plotter 5 to the first bus arbiter 13, the pixel plotter / write acceptance signal IPPWG from the first bus arbiter 13 to the pixel plotter 5, and the pixel plotter from the first bus arbiter 13 to the pixel plotter 5. The read permission signal IPPRG includes a read address or a write address, a write target data, a read or write bus when the first bus use request factor is “pixel plotter”, respectively. A signal indicating a request for use, a signal indicating that the bus use request is a write request, a signal indicating that a write bus use request is accepted, and a read bus use request are accepted, and the internal data IDAI [7: 0] is a signal indicating that fetching is possible.

  Wave data address IWAA from the sound processor 7 to the first bus arbiter 13, wave data bus request signal IWAB from the sound processor 7 to the first bus arbiter 13, and wave data read permission from the first bus arbiter 13 to the sound processor 7 The signal IWARG receives the read address when the first bus use request factor is “wave data”, the signal indicating the read bus use request, and the read bus use request, and receives the internal data IDAI [7: 0]. ] Is a signal indicating that fetching is possible.

  Envelope data address IEVA from the sound processor 7 to the first bus arbiter 13, envelope data / write data IEVW from the sound processor 7 to the first bus arbiter 13, and envelope data bus request signal IEVB from the sound processor 7 to the first bus arbiter 13 The envelope data / write request signal IEVWR from the sound processor 7 to the first bus arbiter 13, the envelope data / write acceptance signal IEVWG from the first bus arbiter 13 to the sound processor 7, and the envelope data from the first bus arbiter 13 to the sound processor 7 The read permission signal IEVRG is the read address or write address when the first bus use request factor is “envelope data”, and the data to be written. , A signal indicating a read or write bus use request, a signal indicating that the bus use request is a write request, a signal indicating that a write bus use request has been accepted, a read bus use request being accepted, and an internal A signal indicating that data IDAI [7: 0] can be fetched.

  DMA destination address IDDA from the DMA controller 9 to the first bus arbiter 13, DMA destination write data IDDW from the DMA controller 9 to the first bus arbiter 13, and a DMA destination bus from the DMA controller 9 to the first bus arbiter 13 The request signal IDDB and the DMA destination / write acceptance signal IDDWG from the first bus arbiter 13 to the DMA controller 9 are the write address, the data to be written when the first bus use request factor is “DMA destination”, respectively. A signal indicating a write bus use request, and a signal indicating that a write bus use request has been accepted.

  Here, the address signals IIFA, IDAA, FBGA, SBGA, ISPA, ICHA, ICDA, IBMA, IPPA, IWAA, IEVA and IDDA are each 15-bit signals. The write data IDAW, IPPW, IEVW and IDDW are 8-bit signals, respectively.

  The first bus arbiter 13 outputs the first bus address IAD, the internal write enable signal IRW, and the internal data IDAO after arbitration to the first bus 31.

  The first bus address IAD is an address signal (15 bits) output to an address bus 311 (see FIG. 18 described later) of the first bus 31. The internal write enable signal IRW is a write enable signal output to the control bus 313 (see FIG. 8) of the first bus 31. When the internal write enable signal IRW is “1”, it indicates a write enable, and when it is “0”, it indicates a read enable. The internal data IDAO is data (8 bits) output to the data bus 312 (see FIG. 8) of the first bus 31.

  16 includes data FBD0 (described later) from the first bus arbiter 13 and other functional blocks (for example, the graphic processor 3, the pixel plotter 5, the sound processor 7, the DMA controller 9, and the second bus arbiter 14). And data FBD1 to FBDn (n is an integer) from the main memory 17).

  Similarly, the address decoder 38 shown in FIG. 16 decodes the first bus address IAD output from the first bus arbiter 13 and outputs a selection signal for selecting one of the data FBD0 to FBDn to the multiplexer 40. The multiplexer 40 selects any one of the input data FBD0 to FBDn according to this selection signal, and outputs it as the internal data IDAI.

  FIG. 17 is a block diagram showing an internal configuration of the first bus arbiter 13 of FIG. As shown in FIG. 17, the first bus arbiter 13 includes an address decoder 317, a zeroth slot priority register 300 to a fifteenth slot priority register 315, multiplexers 319 and 321, a read permission / write acceptance signal generation circuit 327, a slot counter. 323, an OR circuit 324, a priority decoder 325, multiplexers 329, 331, 333, 335, and registers 337, 339, 341, 343.

  When the 0th slot priority order register 300 to the 15th slot priority order register 315 are collectively expressed, they are expressed as a priority order register IPRO.

  Any one of the priority order information numbers 0 to 3 in FIG. 10 is set in each of the 0th slot priority order register 300 to the 15th slot priority order register 315. For example, the 0th slot priority order register 300 to the 15th slot priority order register 315 have priority order information number 0, priority order information number 3, priority order information number 1, priority order information number 3, and priority order information number, respectively. 0, priority order information number 3, priority order information number 2, priority order information number 3, priority order information number 0, priority order information number 3, priority order information number 2, priority order information number 3, priority order information number 0, Priority information number 3, priority information number 2, and priority information number 3 are set. The priority information numbers 0 to 3 are encoded in 2 bits. Accordingly, each of the 0th slot priority register 300 to the 15th slot priority register 315 is a 2-bit register.

  The CPU 1 can arbitrarily set a combination of priority information numbers 0 to 3 for one round in 16 slots by setting values in the 0th slot priority register 300 to the 15th slot priority register 315. The CPU 1 can also read the values set in the 0th slot priority order register 300 to the 15th slot priority order register 315.

  The address decoder 317 decodes the first bus address IAD generated as a result of the bus arbitration. As a result, the first bus address IAD indicates one of the 0th slot priority order register 300 to the 15th slot priority order register 315. When the internal write enable signal IRW indicates write enable, a selection signal is output to the priority order register IPRO indicated by the first bus address IAD.

  The priority register IPRO to which the selection signal is input from the address decoder 317 holds the priority information number given as the internal data IDAO.

  The first bus address IAD in this case is the data access address IDAA output by the CPU 1 and selected by the multiplexer 331 described later. The internal write enable signal IRW in this case is a data access / write request signal IDAWR output by the CPU 1 and selected by a multiplexer 335 described later. The internal data IDAO in this case is the data access / write data IDAW output by the CPU 1 selected by the multiplexer 333 described later.

  On the other hand, the address decoder 317 decodes the first bus address IAD generated as a result of the bus arbitration, so that the first bus address IAD is one of the 0th slot priority order register 300 to the 15th slot priority order register 315. When the internal write enable signal IRW indicates read enable, a selection signal for selecting the priority register IPRO indicated by the first bus address IAD is output to the multiplexer 319. The multiplexer 319 outputs the encoded priority information number held in the priority register IPRO indicated by the selection signal to the multiplexer 40 in FIG. 16 as data FBD0.

  The first bus address IAD in this case is the data access address IDAA output by the CPU 1 and selected by the multiplexer 331 described later. The internal write enable signal IRW in this case is a data access / write request signal IDAWR output by the CPU 1 and selected by a multiplexer 335 described later.

  As described above, the CPU 1 can write a value to the 0th slot priority order register 300 to the 15th slot priority order register 315 via the first bus 31 or read the value.

  The multiplexer 321 selects one of the 0th slot priority order register 300 to the 15th slot priority order register 315 in accordance with the selection signal ISSEL from the slot counter 323, and the priority stored in the selected priority order register IPRO. The rank information number is output to the priority decoder 325.

  The priority fetcher 325 receives an instruction fetch bus request signal IIFB and a data access bus request signal IDAB from the CPU 1, and receives a first background array data bus request signal FBGB and a second background array from the graphic processor 3. A data bus request signal SBGB, a sprite DMA bus request signal ISPB, a character header bus request signal ICHB, a character data bus request signal ICDB, and a bitmap data bus request signal IBMB are input. A plotter bus request signal IPPB is input, and a wave data bus request signal IWAB and an envelope data bus request signal IEVB are input from the sound processor 7 and the DMA controller 9 , DMA destination bus request signal IDDB is input.

  The priority decoder 325 also receives an instruction fetch / read permission signal IIFRG, a data access / read permission signal IDARG, a data access / write permission signal IDAWG, a first background array data, from the read permission / write acceptance signal generation circuit 327. Read permission signal FBGRG, second background array data / read permission signal SBGRG, sprite DMA / read permission signal ISPRG, character header / read permission signal ICHRG, character data / read permission signal ICDRG, bitmap data / read permission signal IBMRG, Pixel plotter / read permission signal IPPRG, pixel plotter / write permission signal IPPWG, wave data / read permission signal IWARG, envelope data / read permission Signal IEVRG, envelope data write acceptance signal IEVWG, and a DMA destination write acceptance signal IDDWG inputted.

  Here, the bus request signals IIFB, IDAB, FPBG, SBGB, ISPB, ICHB, ICDB, IBMB, IPPB, IWAB, IEVB, and IDDB are collectively expressed as a first bus use request signal FBURQ.

  The priority decoder 325 decodes the priority information number currently input from the multiplexer 321. Then, the priority decoder 325, among the first bus use request factors corresponding to the asserted first bus use request signal FBURQ, in accordance with the priority order information set corresponding to the decoded priority order information number, The first bus use request factor having the highest priority is selected except for the first bus use request factor using the. Here, the first bus use request factor currently using the first bus 31 can be known from the state of the first bus use permission signal FAGR input from the read permission / write acceptance signal generation circuit 327.

  The first bus use permission signal FAGR includes an instruction fetch / read permission signal IIFRG, a data access / read permission signal IDARG, a data access / write acceptance signal IDAWG, a first background array data / read permission signal FBGRG, and a second back. Ground array data / read permission signal SBGRG, sprite DMA / read permission signal ISPRG, character header / read permission signal ICHRG, character data / read permission signal ICDRG, bitmap data / read permission signal IBMRG, pixel plotter / read permission signal IPPRG, Pixel plotter / write acceptance signal IPPWG, wave data / read permission signal IWARG, envelope data / read permission signal IEVRG, envelope data / write acceptance Nos IEVWG, and inclusive the notation DMA destination write acceptance signal IDDWG.

  Further, the priority decoder 325 generates a bus master select signal IBMSL [3: 0] based on the selected first bus use request factor, and outputs it to the multiplexers 329, 331, 333, and 335. That is, the priority decoder 325 determines the current first bus 31 among the first bus use request factors corresponding to the asserted first bus use request signal FBURQ in accordance with the priority order information corresponding to the decoded priority order information number. The bus master select signal IBMSL [3: 0] is set to a value indicating the first bus use request factor having the highest priority except for the used first bus use request factor.

  The OR circuit 324 receives a first bus use permission signal FAGR (IIFRG, IDARG, IDAWG, FBGRG, SBGRG, ISPRG, ICHRG, ICDRG, IBMRG, IPPRG, IPPWG, IWARG, IEVRG from the read permission / write acceptance signal generation circuit 327. , IEVWG, IDDWG).

  Each time the signal from the OR circuit 324 transitions from “0 (false)” to “1 (true)”, the slot counter 323 increments the value of the selection signal ISSEL [3: 0] and sends it to the multiplexer 321. The priority information numbers stored in the zeroth slot priority register 300 to the fifteenth slot priority register 315 are sequentially and cyclically selected. This is because the end of one bus cycle of the bus master given the bus use permission is obtained from the logical sum of the fifteen first bus use permission signals FAGR.

  Twelve inputs of each of the multiplexers 329, 331, 333 and 335 are twelve first bus use request factors “instruction fetch”, “data access”, “first background array data”, “second background array data”. "," Sprite DMA "," Character header "," Character data "," Bitmap data "," Pixel plotter "," Wave data "," Envelope data ", and" DMA destination ".

  The 12 inputs of the multiplexer 329 include a code 0b000000000001 indicating the first bus use request factor “instruction fetch”, a code 0b000000000010 indicating the first bus use request factor “data access”, and the first bus use request factor “first background”. Code 0b000000000000100 indicating "array data", code 0b000000001000 indicating the first bus use request factor "second background array data", code 0b00000100000000 indicating the first bus use request factor "sprite DMA", first bus use request factor "character" Code 0b000000100000 indicating header ", code 0b000001000000 indicating first bus use request factor" character data ", first bus use request factor" bit " Code 0b0000010000000 indicating the "bus data", code 0b0001000000 indicating the first bus use request factor "pixel plotter", code 0b001000000000000 indicating the first bus use request factor "wave data", and code indicating the first bus use request factor "envelope data" 0b01000000000000 and a code 0b100000000000000 indicating the first bus use request factor “DMA destination” are input.

  The multiplexer 329 selects the code corresponding to the first bus use request factor indicated by the bus master select signal IBMSL input from the priority decoder 325 (giving use permission of the first bus 31), and outputs it to the register 337.

  The register 337 holds the code input from the multiplexer 329 and outputs it to the read permission / write acceptance signal generation circuit 327.

  The read permission / write acceptance signal generation circuit 327 generates the first bus use permission signal FAGR based on the code output from the register 337. Specifically, it is as follows.

  When the code output from the register 337 is 0b000000000001, the read permission / write acceptance signal generation circuit 327 asserts the instruction fetch / read permission signal IIFRG. When the code output from the register 337 is 0b000000000010 and the data access / write request signal IDAWR is negated, the read permission / write acceptance signal generation circuit 327 asserts the data access / read permission signal IDARG. . The read permission / write acceptance signal generation circuit 327 asserts the data access / write acceptance signal IDAWG when the code output from the register 337 is 0b000000000010 and the data access / write request signal IDAWR is asserted. .

  When the code output from the register 337 is 0b000000000000, the read permission / write acceptance signal generation circuit 327 asserts the first background array data / read permission signal FBGRG. When the code output from the register 337 is 0b000000001000, the read permission / write acceptance signal generation circuit 327 asserts the second background array data / read permission signal SBGRG. When the code output from the register 337 is 0b000001010000, the read permission / write acceptance signal generation circuit 327 asserts the sprite DMA / read permission signal ISPRG.

  When the code output from the register 337 is 0b00000010000000, the read permission / write acceptance signal generation circuit 327 asserts the character header / read permission signal ICHRG. When the code output from the register 337 is 0b000001000000, the read permission / write acceptance signal generation circuit 327 asserts the character data / read permission signal ICDRG. When the code output from the register 337 is 0b000010000000, the read permission / write acceptance signal generation circuit 327 asserts the bitmap data / read permission signal IBMRG.

  The read permission / write acceptance signal generation circuit 327 asserts the pixel plotter read permission signal IPPRG when the code output from the register 337 is 0b000100000000 and the pixel plotter write request signal IPPWR is negated. . The read permission / write acceptance signal generation circuit 327 asserts the pixel plotter write acceptance signal IPPWG when the code output from the register 337 is 0b000100000000 and the pixel plotter write request signal IPPWR is asserted. .

  When the code output from the register 337 is 0b001000000000000, the read permission / write acceptance signal generation circuit 327 asserts the wave data read permission signal IWARG. When the code output from the register 337 is 0b010000000000000 and the envelope data write request signal IEVWR is negated, the read permission / write acceptance signal generation circuit 327 asserts the envelope data read permission signal IEVRG. . The read permission / write acceptance signal generation circuit 327 asserts the envelope data write acceptance signal IEVWG when the code output from the register 337 is 0b010000000000000 and the envelope data write request signal IEVWR is asserted. .

  The read permission / write acceptance signal generation circuit 327 asserts the DMA destination write acceptance signal IDDWG when the code output from the register 337 is 0b100000000000000.

  The 12 inputs of the multiplexer 331 include an instruction fetch address IIFA, a data access address IDAA, a first background array data address FBGA, a second background array data address SBGA, a sprite DMA address ISPA, a character header, Address ICHA, character data address ICDA, bitmap data address IBMA, pixel plotter address IPPA, wave data address IWAA, envelope data address IEVA, and DMA destination address IDDA are input.

  The multiplexer 331 outputs to the register 339 an address signal corresponding to the first bus use request factor (giving use permission of the first bus 31) indicated by the bus master select signal IBMSL among these 12 input address signals.

  The register 339 holds the address signal input from the multiplexer 331 and outputs it as the first bus address IAD [14: 0].

  The 12 inputs of the multiplexer 333 correspond to “0” corresponding to the first bus use request factor “instruction fetch”, data access / write data IDAW, and first bus use request factor “first background array data”. “0”, “0” corresponding to the first bus use request factor “second background array data”, “0” corresponding to the first bus use request factor “sprite DMA”, first bus use request factor “character” “0” corresponding to the “header”, “0” corresponding to the first bus use request factor “character data”, “0” corresponding to the first bus use request factor “bitmap data”, pixel plotter / write data IPPW , “0” corresponding to the first bus use request factor “wave data”, envelope data / write data IEVW, and DMA destination Deployment write data IDDW is input.

  In this case, “0” input means that there is no write request. This is because the first bus use request factors “instruction fetch”, “first background array data”, “second background array data”, “character header”, “character data”, “bitmap data”, “wave data” This is because no writing is performed.

  The multiplexer 333 outputs the input write data corresponding to the first bus use request factor indicated by the bus master select signal IBMSL (giving use permission of the first bus 31) among the 12 input write data to the register 341.

  The register 341 holds the write data input from the multiplexer 333 and outputs it as internal data IDAO [7: 0].

  The 12 inputs of the multiplexer 335 correspond to “0” corresponding to the first bus use request factor “instruction fetch”, the data access / write request signal IDAWR, and the first bus use request factor “first background array data”. “0” corresponding to the first bus use request factor “second background array data”, “0” corresponding to the first bus use request factor “sprite DMA”, and the first bus use request factor “ “0” corresponding to the “character header”, “0” corresponding to the first bus use request factor “character data”, “0” corresponding to the first bus use request factor “bitmap data”, pixel plotter / write request Signal IPPWR, “0” corresponding to first bus use request factor “wave data”, envelope data write request signal IEVWR, and first Corresponding to the use request factor "DMA destination" and "1" is input.

  In this case, “0” input means that no write request is made. This is because the first bus use request factors “instruction fetch”, “first background array data”, “second background array data”, “character header”, “character data”, “bitmap data”, “wave data” This is because no writing is performed. Further, “1” input means that a read request is not performed. This is because only the write is performed in the first bus request factor “DMA destination”.

  The multiplexer 335 outputs the input signal corresponding to the first bus use request factor (giving use permission of the first bus 31) indicated by the bus master select signal IBMSL among the 12 input signals to the register 343.

  The register 343 holds the signal input from the multiplexer 335 and outputs it as the internal write enable signal IRW.

  Next, the second bus arbiter 14 of FIG. 1 will be described in more detail.

  FIG. 18 is an explanatory diagram of input / output signals for the second bus arbiter 14 of FIG. As shown in FIG. 18, the CPU 1 controls the second bus arbiter 14 via the address bus 311, the data bus 312, and the control bus 313.

  Instruction fetch address EIFA from CPU 1 to second bus arbiter 14, instruction fetch size signal EIFS from CPU 1 to second bus arbiter 14, instruction fetch bus request signal EIFB from CPU 1 to second bus arbiter 14, from second bus arbiter 14 The instruction fetch / lower byte read permission signal EIFLR to the CPU 1 and the instruction fetch / upper byte read permission signal EIFUR from the second bus arbiter 14 to the CPU 1 are read when the second bus use request factor is “instruction fetch”. An address, a signal indicating the amount of data to be requested (a signal indicating how many bytes are requested to be read), a signal indicating a read bus use request, and a read bus use request are received, and the lower order of the external data input EDAI Byte ([7: 0]) can be fetched Signal indicating that it, and, with the lead of the bus use request is accepted, the high byte of the external data input EDAI ([15: 8]) is a signal, indicating that it is possible to fetch.

  Address EDAA from CPU1 to second bus arbiter 14, data access / write data EDAA from CPU1 to second bus arbiter 14, data access / bus request signal EDAB from CPU1 to second bus arbiter 14, CPU1 to second bus arbiter 14 Data access / write request signal EDAWR, data access / write acceptance signal EDAWG from second bus arbiter 14 to CPU 1, data access / lower byte read permission signal EDALR from second bus arbiter 14 to CPU 1, and second bus arbiter 14 to CPU 1 The data access / upper byte read permission signal EDAUR is read address or write address, data to be written, read or write when the second bus use request factor is “data access”, respectively. Signal indicating that the bus use request is received, a signal indicating that the bus use request is a write request, a signal indicating that the write bus use request is accepted, and a read bus use request is accepted, and the external data input EDAI A signal indicating that the lower byte ([7: 0]) can be fetched and a read bus use request are accepted, and the upper byte ([15: 8]) of the external data input EDAI can be fetched. It is a signal indicating that.

  Character header address ECHA from graphic processor 3 to second bus arbiter 14, character header size signal ECHS from graphic processor 3 to second bus arbiter 14, character header bus request signal ECHB from graphic processor 3 to second bus arbiter 14 The character header / lower byte read permission signal ECHLR from the second bus arbiter 14 to the graphic processor 3 and the character header / upper byte read permission signal ECHUR from the second bus arbiter 14 to the graphic processor 3 are the second bus use request, respectively. Indicates the read address when the factor is "character header", a signal indicating the amount of requested data transfer (a signal indicating how many bytes are requested to read), and a read bus use request No., a read bus use request is accepted, a signal indicating that the lower byte ([7: 0]) of the external data input EDAI can be fetched, and a read bus use request is accepted, and the external data This is a signal indicating that the upper byte ([15: 8]) of the input EDAI can be fetched.

  Character data address ECDA from the graphic processor 3 to the second bus arbiter 14, character data size signal ECDS from the graphic processor 3 to the second bus arbiter 14, character data bus request signal ECDB from the graphic processor 3 to the second bus arbiter 14 The character data / lower byte read permission signal ECDLR from the second bus arbiter 14 to the graphic processor 3 and the character data / upper byte read permission signal ECDUR from the second bus arbiter 14 to the graphic processor 3 are respectively requested to use the second bus. Indicates the read address when the factor is "character data", a signal indicating the transfer amount of the requested data (a signal indicating how many bytes are requested to read), and a read bus use request No., a read bus use request is accepted, a signal indicating that the lower byte ([7: 0]) of the external data input EDAI can be fetched, and a read bus use request is accepted, and the external data This is a signal indicating that the upper byte ([15: 8]) of the input EDAI can be fetched.

  Bitmap data address EBMA from the graphic processor 3 to the second bus arbiter 14, Bitmap data bus request signal EBMB from the graphic processor 3 to the second bus arbiter 14, Bitmap data from the second bus arbiter 14 to the graphic processor 3 The lower byte read permission signal EBMLR and the bit map data from the second bus arbiter 14 to the graphic processor 3 and the upper byte read permission signal EBMUR are read addresses when the second bus use request factor is “bit map data”, respectively. A signal indicating a read bus use request, a signal indicating that a read bus use request is accepted and the lower byte ([7: 0]) of the external data input EDAI can be fetched, and a read bus use request But Only attached, the high byte of the external data input EDAI ([15: 8]) is a signal, indicating that it is possible to fetch.

  Pixel plotter address EPPA from the pixel plotter 5 to the second bus arbiter 14, pixel plotter light data EPPW from the pixel plotter 5 to the second bus arbiter 14, pixel plotter size signal EPPS from the pixel plotter 5 to the second bus arbiter 14, Pixel plotter bus request signal EPPB from the pixel plotter 5 to the second bus arbiter 14, pixel plotter write request signal EPPWR from the pixel plotter 5 to the second bus arbiter 14, and pixel plotter write from the second bus arbiter 14 to the pixel plotter 5 An acceptance signal EPPWG, a pixel plotter / lower byte read permission signal EPPLR from the second bus arbiter 14 to the pixel plotter 5, and a pixel from the second bus arbiter 14 to the CPU 1 The rotator / upper byte read permission signal EPPUR is a signal indicating the read address or write address when the second bus use request factor is “pixel plotter”, the data to be written, and the transfer amount of the requested data (how many bytes Signal indicating whether a read or write request is requested), a signal indicating a read or write bus use request, a signal indicating that the bus use request is a write request, a signal indicating that a write bus use request has been accepted, A signal indicating that the read bus use request is accepted and the lower byte ([7: 0]) of the external data input EDAI can be fetched, and the read bus use request is accepted and the external data input EDAI is received. Is a signal indicating that the upper byte ([15: 8]) can be fetched.

  Wave data address EWAA from the sound processor 7 to the second bus arbiter 14, wave data bus request signal EWAB from the sound processor 7 to the second bus arbiter 14, wave data / lower byte read from the second bus arbiter 14 to the sound processor 7 The enable signal EWALR and the wave data / upper byte read enable signal EWAUR from the second bus arbiter 14 to the sound processor 7 are read address and read bus use request when the second bus use request factor is “wave data”, respectively. And a signal indicating that the lower byte ([7: 0]) of the external data input EDAI can be fetched, and a request to use the read bus, External data input EDA The upper byte ([15: 8]) is a signal, indicating that it is possible to fetch.

  Envelope data address EEVA from the sound processor 7 to the second bus arbiter 14, Envelope data bus request signal EEVB from the sound processor 7 to the second bus arbiter 14, Envelope data and lower byte read from the second bus arbiter 14 to the sound processor 7 The permission signal EEVLR and the envelope data / upper byte read permission signal EEVUR from the second bus arbiter 14 to the sound processor 7 are the read address and the read bus use request when the second bus use request factor is “envelope data”, respectively. And a signal indicating that the lower byte ([7: 0]) of the external data input EDAI can be fetched, and a request to use the read bus, Part data input EDAI high byte ([15: 8]) is a signal, indicating that it is possible to fetch.

  DMA source address EDSA from the DMA controller 9 to the second bus arbiter 14, DMA source size signal EDSS from the DMA controller 9 to the second bus arbiter 14, DMA source bus request signal EDSB from the DMA controller 9 to the second bus arbiter 14 The DMA source / lower byte read permission signal EDSLR from the second bus arbiter 14 to the DMA controller 9 and the DMA source / upper byte read permission signal EDSUR from the second bus arbiter 14 to the DMA controller 9 are respectively requested to use the second bus. When the cause is “DMA source”, the read address, the signal indicating the transfer amount of the requested data (the signal indicating how many bytes are requested), the signal indicating the read bus use request, and the read bus use request are Accepted, A signal indicating that the lower byte ([7: 0]) of the partial data input EDAI can be fetched and a read bus use request are accepted, and the upper byte ([15: 8]) of the external data input EDAI is received. Is a signal indicating that fetching is possible.

  Here, the address signals EIFA, EDAA, ECHA, ECDA, EBMA, EPPA, EWAA, EEVA, and EDSA are 27-bit signals, respectively. The write data EDAW and EPPW are 16-bit signals, respectively. However, valid data of the write data EDAW is the lower 8 bits of 16 bits.

  FIG. 19 is an illustration of a request size for each second bus use request factor in the present embodiment. As shown in FIG. 19, when the second bus use request factor is “instruction fetch”, the CPU 1 uses the instruction fetch size signal EIFS to select one of 1, 2, 3, or 4 bytes as the data transfer size. Can be requested (variable).

  Therefore, the CPU 1 can dynamically set the data transfer size in accordance with the size of the instruction to be fetched by the instruction fetch size signal EIFS.

  When the second bus use request factor is “data access”, the data transfer size is fixed at 1 byte. When the second bus use request factor is “character header”, the graphic processor 3 can request 0 bytes as the data transfer size by the character header size signal ECHS (that is, data transfer is not performed).

  When the second bus use request factor is “character data”, the graphic processor 3 uses the character data size signal ECDS to select one of 1, 2, 3,..., 15 or 16 bytes as the data transfer size. Can be requested (variable).

  Various sizes of characters are prepared, such as 8 × 8 pixels, 8 × 16 pixels, 16 × 8 pixels, 16 × 16 pixels, and the like. In addition, various modes are prepared such that the data amount per pixel is 1, 2, 3,..., 7 or 8 bits. Therefore, the graphic processor 3 can dynamically set the data transfer size in accordance with the character size and the number of bits per pixel by the character data size signal ECDS.

  When the second bus use request factor is “bitmap data”, the data transfer size is fixed at 8 bytes.

  When the second bus use request factor is “pixel plotter”, the pixel plotter 5 can request either 1 or 2 bytes as a data transfer size (variable) by the pixel plotter size signal EPPS.

  For example, when the pixel plotter 5 sets the normal data transfer size to 2 bytes according to the pixel plotter size signal EPPS, the access starts from the position indicated by the byte address whose LSB (least significant bit) is “1”. The size indicated by the pixel plotter size signal EPPS at that time is 1 byte. This is because the lower byte read / write is useless during such access.

  When the second bus use request factor is “wave data”, the data transfer size is fixed to 1 byte. When the second bus use request factor is “envelope data”, the size of data transfer is fixed at 1 byte.

  When the second bus use request factor is “DMA source”, the DMA controller 9 can request 1, 2, 3, or 4 bytes as the data transfer size by the DMA source size signal EDSS (variable). ).

  Therefore, the DMA controller 9 can dynamically set the data transfer size in accordance with the size of the DMA transfer source data to be transferred by the DMA source size signal EDSS.

  Returning to FIG. 18, the second bus arbiter 14 sends to the second bus 33 the second bus address EAD, the second bus address output enable signal EADOE, the external data EDAO, the external data output enable signal EDAOE, the external read enable signal ERDE, An external write enable signal EWRE, a lower byte enable signal LWBE, an upper byte enable signal UPBE, a first area select signal ASSEL1, and a second area select signal ASSEL2 are output.

  The second bus address EAD is an address signal (27 bits) output to the address bus (not shown) of the second bus 33.

  The external data EDAO is data (16 bits) output to the data bus (not shown) of the second bus 33. The external data output enable signal EDAOE is a signal for controlling a 3-state buffer (not shown) for connecting the data bus of the second bus 33 to the data bus of the external bus 43 and switching the output / Hi-Z (high impedance). is there.

  The external read enable signal ERDE is a read enable signal output to the control bus (not shown) of the second bus 33. The external write enable signal EWRE is a write enable signal output to the control bus of the second bus 33.

  The lower byte enable signal LWBE is an enable signal for the lower byte of the data bus of the second bus 33. The upper byte enable signal UPBE is an enable signal for the upper byte of the data bus of the second bus 33.

  The first area select signal ASSEL 1 is a signal for selecting the second bus first area in the logical address space of the processor 100. The second area select signal ASSEL2 is a signal for selecting the second bus second area in the logical address space of the processor 100. The signal for selecting the second bus 0th area (0th area select signal ASSEL0) is substituted by the second bus address EAD [22].

  The second bus address output enable signal EADOE includes the address bus of the second bus 33, the control bus (ERDE and EWRE), the lower byte enable signal LWBE, the upper byte enable signal UPBE, the first area select signal ASSEL1, and the second area select. This is a signal for controlling a 3-state buffer (not shown) for connecting the signal ASSEL2 to the external bus 43 and switching the output / Hi-Z (high impedance).

  FIG. 20 is a block diagram showing an internal configuration of the second bus arbiter 14 of FIG. As shown in FIG. 20, the second bus arbiter 14 includes a first bus interface circuit 140, a multiplexer 141, an OR circuit 210, a priority decoder 142, multiplexers 143 to 146, registers 230 to 233, a slot counter 147, an OR circuit 148, an address. Decoder 149, byte enable signal generation circuit 150, multiplexers 151-153, decoder 154, state machine 155, external bus release request register 156, 0th area bus width register 160, first area bus width register 161, second area bus width Register 162, 0th area random access cycle number register 170, 1st area random access cycle number register 171, 2nd area random access cycle number register 172, 0th area page access cycle Register number register 180, first area page access cycle number register 181, second area page access cycle number register 182, zeroth area page size register 190, first area page size register 191, second area page size register 192, and 0th slot priority order register 200 to 7th slot priority order register 207 are included.

  The first bus interface circuit 140 is an interface for connecting the first bus 31 to each of the control registers 156, 160 to 162, 170 to 172, 180 to 182, 190 to 192, and 200 to 207.

  Here, when the control registers 156, 160 to 162, 170 to 172, 180 to 182, 190 to 192, and 200 to 207 are collectively expressed, they are expressed as a control register CR.

  The CPU 1 can write a value to the control register CR or read a value via the first bus interface circuit 140. Specifically, the CPU 1 designates read by the internal write enable signal IRW, and reads the data of the control register CR in the second bus arbiter 15 designated by the first bus address IAD as the internal data IDAI. it can. Further, the CPU 1 can write data by the internal write enable signal IRW and write the data given as the internal data IDAO to the control register CR in the second bus arbiter 15 specified by the first bus address IAD. .

  The value of the external bus release request register 156 is input to the state machine 155. When “1” is set in the external bus release request register 156 by the CPU 1, the state machine 155 sets the address bus, data bus, and control bus (not shown) of the external bus 43 to high impedance. For example, when another device shares the external bus 43 of the processor 100 and there is an external bus use request from another device, the external bus release request register 156 is set to “1”.

  Information indicating the bus width of the data bus when accessing the second bus 0th area is set in the 0th area bus width register 160. Information indicating the bus width of the data bus when accessing the second bus first area is set in the first area bus width register 161. Information indicating the bus width of the data bus when accessing the second bus second area is set in the second area bus width register 162. In the present embodiment, information indicating a bus width of 8 bits or 16 bits can be set in each of the 0th area bus width register 160, the first area bus width register 161, and the second area bus width register 162.

  In the 0th area random access cycle number register 170, information indicating the access cycle number (clock cycle number) indicating the bus cycle period length when the second bus 0th area is randomly accessed is set. The first area random access cycle number register 171 is set with information indicating the access cycle number (clock cycle number) indicating the bus cycle period length when the second bus first area is randomly accessed. The second area random access cycle number register 172 is set with information indicating the access cycle number (clock cycle number) indicating the bus cycle period length when the second bus second area is randomly accessed. Here, the bus cycle period length (period length of one bus cycle) is defined by the number of cycles of the internal clock signal ICLK.

  In the present embodiment, each of the 0th area random access cycle number register 170, the first area random access cycle number register 171 and the second area random access cycle number register 172 includes 2 to 8 cycles of the internal ICLK clock signal. Can be set.

  In the 0th area page access cycle number register 180, information indicating the access cycle number (clock cycle number) indicating the bus cycle period length when accessing the second bus 0th area in the page mode is set. The first area page access cycle number register 181 is set with information indicating the access cycle number (clock cycle number) indicating the bus cycle period length when accessing the second bus first area in the page mode. The second area page access cycle number register 182 is set with information indicating the access cycle number (clock cycle number) indicating the bus cycle period length when accessing the second bus second area in the page mode. Here, the bus cycle period length (period length of one bus cycle) is defined by the number of cycles of the internal clock signal ICLK.

  In the present embodiment, each of the 0th area page access cycle number register 180, the first area page access cycle number register 181 and the second area page access cycle number register 182 includes 1 to 4 cycles of the internal ICLK clock signal. Can be set.

  In the 0th area page size register 190, information indicating the page size when the second bus 0th area is accessed in the page mode is set. The first area page size register 191 is set with information indicating the page size when accessing the second bus first area in the page mode. The second area page size register 192 is set with information indicating the page size when accessing the second bus second area in the page mode. In the present embodiment, information indicating 0, 4, 8, or 16 bytes can be set in each of the 0th area page size register 190, the first area page size register 191 and the second area page size register 192.

  The CPU 1 can set the values of the control registers 160 to 162, 170 to 172, 180 to 182 and 190 to 192 according to the specifications of the external memories 45 to 47. Further, the CPU 1 can set values independently for the control registers 160 to 162, can set values independently for the control registers 170 to 172, and can set values to the control registers 180 to 182. Values can be set independently, and values can be set independently for the control registers 190-192.

  Any one of the priority order information numbers 0 to 3 in FIG. 14 is set in each of the 0th slot priority order register 200 to the seventh slot priority order register 207. For example, the 0th slot priority order register 200 to the 7th slot priority order register 207 include priority order information number 1, priority order information number 3, priority order information number 1, priority order information number 2, and priority order information number, respectively. 1, priority order information number 3, priority order information number 1, and priority order information number 0 are set. The priority information numbers 0 to 3 are encoded in 2 bits. Accordingly, each of the 0th slot priority order register 200 to the seventh slot priority order register 207 is a 2-bit register.

  The CPU 1 can arbitrarily set a combination of priority information numbers 0 to 3 for one round in eight slots by setting values in the zeroth slot priority register 200 to the seventh slot priority register 207.

  The multiplexer 141 selects one of the 0th slot priority register 200 to the seventh slot priority register 207 in accordance with the selection signal ESSEL from the slot counter 147, and the priority stored in the selected priority register. The information number is output to the priority decoder 142.

  An instruction fetch bus request signal EIFB and a data access bus request signal EDAB are input from the CPU 1 to the priority decoder 142 and the OR circuit 210, and a character header bus request signal ECHB and a character data bus request are received from the graphic processor 3. A signal ECDB and a bitmap data bus request signal EBMB are input, a pixel plotter bus request signal EPPB is input from the pixel plotter 5, and a wave data bus request signal EWAB and an envelope data bus request are input from the sound processor 7. A signal EEVB is input, and a DMA source bus request signal EDSB is input from the DMA controller 9.

  The priority decoder 142 also receives an instruction fetch / read permission signal EIFRG, a data access / read permission signal EDARG, a data access / write acceptance signal EDAWG, a character header / read permission signal ECHRG, and a character data / read permission from the state machine 155. Signal ECDRG, Bitmap data read permission signal EBMRG, Pixel plotter read permission signal EPPRG, Pixel plotter write permission signal EPPWG, Wave data read permission signal EWARG, Envelope data read permission signal EEVRG, and DMA source read permission A signal EDSRG is input.

  Here, when the bus request signals EIFB, EDAB, ECHB, ECDB, EBMB, EPPB, EWAB, EEVB, and EDSB are comprehensively expressed, they are expressed as a second bus use request signal SBURQ.

  The priority decoder 142 decodes the priority information number currently input from the multiplexer 141, and in accordance with the priority information set indicated by the priority information number, from the bus master that issues the second bus use request signal SBURQ, The bus master having the highest priority (giving permission to use the second bus 33) is selected from among the second bus use request factors that are currently using the second bus 33. Specifically, it is as follows.

  The priority decoder 142 currently uses the second bus 33 among the second bus use request factors corresponding to the asserted second bus use request signal SBURQ in accordance with the priority information set corresponding to the decoded priority information number. The second bus use request factor having the highest priority is selected except for the second bus use request factor. Here, the second bus use request factor currently using the second bus can be known from the state of the second bus use permission signal SAGR sent from the state machine 155.

  The second bus use permission signal SAGR includes an instruction fetch / read permission signal EIFRG, a data access / read permission signal EDARG, a data access / write acceptance signal EDAWG, a character header / read permission signal ECHRG, and a character data / read permission signal ECDRG. , Bit map data read permission signal EBMRG, pixel plotter read permission signal EPPRG, pixel plotter write permission signal EPPWG, wave data read permission signal EWARG, envelope data read permission signal EEVRG, and DMA source read permission signal EDSRG Is a comprehensive notation.

  Further, the priority decoder 142 generates a bus master select signal EBMSL [8: 0] based on the selected second bus use request factor, and outputs it to the state machine 155 and the multiplexers 143 to 146. Each bit of the bus master select signal EBMSL [8: 0] corresponds to nine second bus use request factors. The priority decoder 142 sets the bit corresponding to the selected second bus use request factor (giving the use permission of the second bus 33) to “1” and the other bits to “0”. That is, the priority decoder 142 is currently out of the second bus use request factors corresponding to the asserted second bus use request signal SBURQ according to the priority information set corresponding to the decoded priority information number. The bit corresponding to the second bus use request factor having the highest priority is set to “1” except for the second bus use request factor using “1”.

  The eleventh bus use permission signal SAGR (EIFRG, EDARG, EDAWG, ECHRG, ECDRG, EBDRG, EPRRG, EPPWG, EWARG, EEVRG, EDSRG) is input to the OR circuit 148 from the state machine 155.

  The slot counter 147 increments the value of the selection signal ESSEL [2: 0] every time the signal from the OR circuit 148 transitions from “0 (false)” to “1 (true)”, and sends it to the multiplexer 141. The priority order information numbers stored in the 0th slot priority order register 200 to the seventh slot priority order register 207 are sequentially and cyclically selected. This is because the end of one or consecutive bus cycles of the bus master to which the bus use permission is given is obtained from the logical sum of the eleventh second bus use permission signals SAGR.

  Nine second bus use request signals SBURQ are input to the OR circuit 210, and when one or more of the second bus use request signals SBURQ is “1”, the second bus use request signal SBR is asserted. .

  Nine inputs of each of the multiplexers 143 to 146 are nine second bus use request factors “instruction fetch”, “data access”, “character header”, “character data”, “bitmap data”, “pixel plotter”. , “Wave data”, “envelope data”, and “DMA source”.

  Nine inputs of the multiplexer 143 include an instruction fetch address IFA, a data access address EDAA, a character header address ECHA, a character data address ECDA, a bitmap data address EBMA, a pixel plotter address EPPA, and a wave data address. EWAA, envelope data address EEVA, and DMA source address EDSA are input.

  Of these nine input address signals, the multiplexer 143 outputs to the register 230 an address signal corresponding to the second bus use request factor indicated by the bus master select signal EBMSL (giving permission to use the second bus 33).

  The register 230 holds the input address signal and outputs it as a unified address CADR [26: 0]. In this case, the unified address CADR [26: 1] is outputted to the state machine 155 and the unified address CADR [0] is outputted to the byte enable signal generation circuit 150. The unified address CADR [22:21] is also output to the address decoder 149.

  The address decoder 149 decodes the unified address CADR [22:21] to generate a unified first area select signal CASEL1 and a unified second area select signal CASEL2, and sends them to the multiplexers 151 to 153, the decoder 154, and the state machine 155. Output. This point will be described in detail with reference to FIG.

  As shown in the lower part of FIG. 7, when the address A22 (unified address CADR [22]) is “0”, it indicates the second bus 0th area, and the address A22 (unified address CADR [22]) is “1”. When address A21 (unified address CADR [21]) is "0", it indicates the second bus first area, address A22 (unified address CADR [22]) is "1" and address A21 (unified address CADR [ 21]) is “1”, it indicates the second area of the second bus.

  Therefore, the address decoder 149 decodes the unified address CADR [22:21], and which area is selected from the second bus 0th area, the second bus 1st area, and the second bus 2nd area. Can be determined.

  When the unified address CADR [22:21] indicates the second bus 0th area, the address decoder 149 negates both the unified first area select signal CASEL1 and the unified second area select signal CASEL2. When the second bus first area is indicated, the unified first area select signal CASEL1 is asserted, the unified second area select signal CASEL2 is negated, and when the second bus second area is indicated, the unified first area select signal CASEL1 is asserted. The one area select signal CASEL1 is negated, and the unified second area select signal CASEL2 is asserted.

  Returning to FIG. 20, the multiplexer 151 selects one of the three bus width registers 160 to 162 in accordance with the unified first area select signal CASEL1 and the unified second area select signal CASEL2, and the selected bus width register. The value is output to the state machine 155 as a unified bus width signal CBW.

  That is, the multiplexer 151 converts the value of the bus width register corresponding to the area indicated by the unified address signal CADR among the second bus 0th area, the second bus 1st area, and the second bus 2nd area to the unified bus width. The signal is CBW.

  The multiplexer 152 selects one of the three random access cycle number registers 170 to 172 according to the unified first area select signal CASEL1 and the unified second area select signal CASEL2, and sets the value of the selected random access cycle number register. And output to the state machine 155 as a unified random access cycle number signal CRCY.

  That is, the multiplexer 152 unifies the value of the random access cycle number register corresponding to the area indicated by the unified address signal CADR among the second bus 0th area, the second bus 1st area, and the second bus 2nd area. It is assumed that the random access cycle number signal CRCY.

  The multiplexer 153 selects one of the three page access cycle number registers 180 to 182 according to the unified first area select signal CASEL1 and the unified second area select signal CASEL2, and sets the value of the selected page access cycle number register. And output to the state machine 155 as a unified page access cycle number signal CPCY.

  That is, the multiplexer 153 unifies the value of the page access cycle number register corresponding to the area indicated by the unified address signal CADR among the second bus 0th area, the second bus 1st area, and the second bus 2nd area. The page access cycle number signal CPCY is used.

  The decoder 154 selects one of the three page size registers 190 to 192 according to the unified first region select signal CASEL1 and the unified second region select signal CASEL2, and decodes the value of the selected page size register.

  That is, the decoder 154 decodes the value of the page register corresponding to the area indicated by the unified address signal CADR among the second bus 0th area, the second bus 1st area, and the second bus 2nd area.

  Then, the decoder 154 outputs the decoding result to the state machine 155 as a unified page boundary signal CPB. Each of the page size registers 190 to 192 is 2 bits, thereby representing page sizes 0, 4, 8, and 16 bytes. The decoder 154 decodes these two bits and generates a unified page boundary signal CPB [3: 0] indicating a mask of the second bus address EAD [3: 0].

  Nine inputs of the multiplexer 144 are an instruction fetch size signal EIFS, “1” as a data access size signal EDAS, a character header size signal ECHS, a character data size signal ECDS, and a bitmap data size signal EBMS. "8", pixel plotter size signal EPPS, "1" as wave data size signal EWAS, "1" as envelope data size signal EEVS, and DMA source size signal EDSS.

  As described above, “1” is input as a fixed value as the data access size signal EDAS, the wave data size signal EWAS, and the envelope data size signal EEVS. This is because, as can be seen from FIG. 19, in the second bus use request factor corresponding to these, the size of data transfer that can be requested is fixed at 1 byte. Note that “1” input to the multiplexer 144 means that the requested data transfer size is 1 byte. Further, “8” is input as a fixed value as the bitmap data size signal EBMS (see FIG. 19).

  The multiplexer 144 outputs to the register 231 a size signal corresponding to the second bus use request factor indicated by the bus master select signal EBMSL (giving use permission of the second bus 33) among the nine input size signals.

  The register 231 holds the input size signal and outputs it to the state machine 155 as a unified size signal CSZ.

  The nine inputs of the multiplexer 145 include “0” corresponding to the second bus use request factor “instruction fetch”, “0” corresponding to the data access / write data EDAW, the second bus use request factor “character header”, “0” corresponding to the second bus use request factor “character data”, “0” corresponding to the second bus use request factor “bitmap data”, pixel plotter / write data EPPW, second bus use request factor “wave” “0” corresponding to “data”, “0” corresponding to the second bus use request factor “envelope data”, and “0” corresponding to the second bus use request factor “DMA source” are input.

  In this case, “0” input means that there is no write data. This is because the second bus use request factors “instruction fetch”, “character header”, “character data”, “bitmap data”, “wave data”, “envelope data”, and “DMA source” do not perform writing. It is.

  The multiplexer 145 outputs, to the register 232, input data corresponding to the second bus use request factor indicated by the bus master select signal EBMSL (giving use permission of the second bus 33) among the nine input write data.

  The register 232 holds the input write data and outputs it to the state machine 155 as unified write data CWD.

  Nine inputs of the multiplexer 146 are “0” corresponding to the second bus use request factor “instruction fetch”, “0” corresponding to the data access / write request signal EDAWR and the second bus use request factor “character header”. “0” corresponding to the second bus use request factor “character data”, “0” corresponding to the second bus use request factor “bitmap data”, the pixel plotter / write request signal EPPWR, the second bus use request factor “0” corresponding to “wave data”, “0” corresponding to the second bus use request factor “envelope data”, and “0” corresponding to the second bus use request factor “DMA source” are input.

  In this case, “0” input means that there is no write request. This is because the second bus use request factors “instruction fetch”, “character header”, “character data”, “bitmap data”, “wave data”, “envelope data”, and “DMA source” do not perform writing. It is.

  The multiplexer 145 outputs, to the register 233, an input signal corresponding to the second bus use request factor indicated by the bus master select signal EBMSL (giving use permission of the second bus 33) among the nine input signals.

  The register 233 holds the input signal and outputs it to the state machine 155 as a unified write request signal CWRQ.

  The byte enable signal generation circuit 150 generates a unified lower byte enable signal CLWBE and a unified upper byte enable signal CUPBE based on the unified address CADR [0], the unified bus width signal CBW, and the unified write request signal CWRQ. Output to machine 155. Specifically, it is as follows.

  First, the case where the unified write request signal CWRQ is “0” (in the case of reading) will be described. When the unified bus width signal CBW indicates a data bus width of 16 bits, the byte enable signal generation circuit 150 generates the unified lower byte enable signal CLWBE and the unified upper byte enable signal CUPBE regardless of the unified address CADR [0]. Assert both.

  On the other hand, when the unified bus width signal CBW indicates the data bus width of 8 bits, the byte enable signal generation circuit 150 asserts the unified lower byte enable signal CLWBE when the unified address CADR [0] is “0”. The unified upper byte enable signal CUPBE is negated. When the unified address CADR [0] is “1”, the unified lower byte enable signal CLWBE is negated and the unified upper byte enable signal CUPBE is asserted.

  As described above, the reading is performed in units of 16 bits in the area where the bus width is set to 16 bits, and is performed in units of 8 bits in the area where the bus width is set to 8 bits.

  Next, the case where the unified write request signal CWRQ is “1” (in the case of writing) will be described. The byte enable signal generation circuit 150 asserts the unified lower byte enable signal CLWBE and outputs the unified upper byte enable signal CUPBE when the unified address CADR [0] is “0” regardless of the value of the unified bus width signal CBW. When the unified address CADR [0] is “1”, the unified lower byte enable signal CLWBE is negated and the unified upper byte enable signal CUPBE is asserted.

  As described above, in both the area where the bus width is set to 16 bits and the area where the bus width is set to 8 bits, writing is always performed in units of 8 bits.

  The state machine 155 divides access to the second bus 33 into a plurality of states (states) IDLE, FREE, WRITE, READ, and STEAL, and outputs a second bus address EAD, a second bus address output enable signal EADOE, and an external data output EDAO, external data output enable signal EDAOE, external read enable signal ERDE, external write enable signal EWRE, lower byte enable signal LWBE, upper byte enable signal UPBE, first area select signal ASSEL1, and second area select signal ASSEL2, and Instruction fetch / upper byte read enable signal EIFUR, instruction fetch / lower byte read enable signal EIFLR, data access / lower byte read enable signal EDALR, data access / upper byte read Permission signal EDAUR, data access / write acceptance signal EDAWG, character header / lower byte read permission signal ECHLR, character header / upper byte read permission signal ECHUR, character data / lower byte read permission signal ECDLR, character data / upper byte read permission signal ECDUR, bitmap data / lower byte read enable signal EBMLR, bitmap data / upper byte read enable signal EBMUR, pixel plotter / lower byte read enable signal EPPLR, pixel plotter / upper byte read enable signal EPPUR, pixel plotter / write accept signal EPPWG, wave data / lower byte read enable signal EWALR, wave data / upper byte read enable signal EWAUR, envelope data Lower byte read permission signal EEVLR, envelope data / upper byte read permission signal EEVUR, DMA source / lower byte read permission signal EDSLLR, DMA source / upper byte read permission signal EDSUR, instruction fetch / read permission signal EIFRG, data access / read permission Signal EDARG, character header / read permission signal ECHRG, character data / read permission signal ECDRG, bitmap data / read permission signal EBMRG, pixel plotter / read permission signal EPPRG, wave data / read permission signal EWARG, envelope data / read permission signal EEVRG and DMA source / read permission signal EDSRG are controlled.

  FIG. 21 is an explanatory diagram of state transitions in the state machine 155 of FIG. As shown in FIG. 21, the IDLE state ST0 is a free state where there is no use request for the second bus 33. In the FREE state ST1, the state machine 155 responds to the release request of the external bus 43 from the CPU 1 ("1" is set in the external bus release request register 156), the second bus address EAD, the external data output EDAO, the external read The enable signal ERDE, the external write enable signal EWRE, the lower byte enable signal LWBE, the upper byte enable signal UPBE, the first area select signal ASSEL1, and the second area select signal ASSEL2 are set to Hi-Z (high impedance).

  The WRITE state ST2 is a write cycle. Multiple bytes may be written continuously.

  The READ state ST3 is a read cycle. There may be a case where multiple bytes are continuously read. However, when a read with a constant number of bytes is requested and there is a read request from the sound processor 7, the state shifts to the STEAL state ST4 in order to interrupt the read access from the sound processor 7.

  The STEAL state ST4 is a state for interrupt access during read access by another bus master because the bus use request from the sound processor 7 has a high degree of urgency.

  The state transition will be described with reference to the drawing. In the figure, “∧” represents a logical product, “∨” represents a logical sum, “<” and “≧” represent an inequality sign, and “=” represents an equal sign.

  In the present embodiment, when the conditional expression in the figure is satisfied, the state transitions to a state corresponding to the satisfied conditional expression at the next rise of the internal clock signal ICLK.

  First, the state transition from the IDLE state ST0 will be described.

  When the value of the external bus release request register 156 becomes “1”, the state machine 155 moves to the FREE state ST1.

  Further, the state machine 155 determines that the value of the external bus release request register 156 is “0”, the second bus use request signal SBR is “1”, and the unified write request signal CWRQ is “1”. , Transition to the WRITE state ST2.

  Further, the state machine 155 determines that the value of the external bus release request register 156 is “0”, the second bus use request signal SBR is “1”, and the unified write request signal CWRQ is “0”. , Transition to the READ state ST3. If the second bus use request signal SBR is “1” and the unified write request signal CWRQ is “0”, it means a read request.

  Further, when the value of the external bus release request register 156 is “0” and the second bus use request signal SBR is “0”, the state machine 155 shifts to the same IDLE state ST0.

  Next, the state transition from the FREE state ST1 will be described.

  When the cycle count CYC is “1” and the value of the external bus release request register 156 is “0”, the state machine 155 moves to the IDLE state ST0.

  Here, the cycle counter is a 3-bit counter. The initial value of the cycle count CYC in the FREE state ST1 is “0”, that is, “0b000”, and is decremented every cycle of the internal clock ICLK. The initial value “0b000” of the cycle count CYC means 8 cycles of the internal clock ICLK.

  Next, state transition from the WRITE state ST2 will be described.

  In the state machine 155, the cycle count CYC is “1”, the byte count BYC is less than “2”, the value of the external bus release request register 156 is “0”, and the second bus use request signal SBR is “0”. When it becomes, it shifts to the IDLE state ST0.

  Here, the initial value of the cycle count CYC in the WRITE state ST2 is the random access cycle number indicated by the unified random access cycle number signal CRCY. The initial value of the byte count BYC in the WRITE state ST2 is the size indicated by the unified size signal CSZ (see FIG. 19), and is decremented every time one byte is written.

  The state machine 155 goes to the FREE state ST1 when the cycle count CYC is “1”, the byte count BYC is less than “2”, and the value of the external bus release request register 156 is “1”. Transition.

  Further, the state machine 155 determines that the cycle count CYC is “1”, the byte count BYC is less than “2”, the value of the external bus release request register 156 is “0”, and the second bus use request signal SBR. Is “1”, and the unified write request signal CWRQ is “1”, the process proceeds to the same WRITE state ST2.

  Further, the state machine 155 determines that the cycle count CYC is “1”, the byte count BYC is less than “2”, the value of the external bus release request register 156 is “0”, and the second bus use request signal SBR. Is “1” and the unified write request signal CWRQ becomes “0”, the state shifts to the READ state ST3.

  Next, state transition from the READ state ST3 will be described.

  In the state machine 155, the cycle count CYC is “1”, the condition 1 in FIG. 21 is “false”, the value of the external bus release request register 156 is “0”, and the second bus use request signal SBR is When it becomes “0”, the state shifts to the IDLE state ST0.

  Here, the initial value of the cycle count CYC in the READ state ST3 is the random access cycle number indicated by the unified random access cycle number signal CRCY or the page access cycle number indicated by the unified page access cycle number signal CPCY.

  Condition 1 is that the second bus width signal SBW is “1” and the second bus address EAD [0] is “0” and the byte count BYC is “3” or more, or the second bus width signal SBW is “1” and When the second bus address EAD [0] is “1” and the byte count BYC is “2” or more, or the second bus width signal SBW is “0” and the byte count BYC is “2” or more. This is a condition to become “true”.

  When the second bus width signal SBW is “0”, it means that the requested bus width is 8 bits, and when it is “1”, it means that the requested bus width is 16. The initial value of the byte count BYC in the READ state ST3 is the size indicated by the unified size signal CSZ (see FIG. 19), and is decremented every time one byte is read. When the second bus address EAD [0] is “0”, the lower byte of 16-bit data is indicated, and when the second bus address EAD [0] is “1”, the upper byte of 16-bit data is indicated.

  Therefore, if condition 1 is “true”, when the requested bus width is 16 bits, the current second bus address EAD [0] indicates the lower byte, and the remaining read data is 3 bytes or more. Therefore, when all the remaining read data cannot be read in one bus cycle, or when the requested bus width is 16 bits, the current second bus address EAD [0] indicates the upper byte, and the remaining Since the read data is 2 bytes or more, all the remaining read data cannot be read in one bus cycle, or when the requested bus width is 8 bits, the remaining read data is 2 bytes or more. Therefore, it means that all the remaining read data cannot be read in one bus cycle.

  Conversely, if the condition 1 is “false”, when the requested bus width is 16 bits, the current second bus address EAD [0] indicates the lower byte, and the remaining read data is 2 bytes or less. Therefore, when all the remaining read data can be read in one bus cycle, or when the requested bus width is 16 bits, the current second bus address EAD [0] indicates the upper byte, and the remaining Since the read data is 1 byte, all the remaining read data can be read in one bus cycle, or when the requested bus width is 8 bits, the remaining read data is 1 byte. This means that all remaining read data can be read in one bus cycle.

  The state machine 155 shifts to the FREE state ST1 when the cycle count CYC is “1”, the condition 1 is “false”, and the value of the external bus release request register 156 is “1”. .

  Further, the state machine 155 indicates that the cycle count CYC is “1”, the condition 1 is “false”, the value of the external bus release request register 156 is “0”, and the second bus use request signal SBR is “0”. 1 "and when the unified write request signal CWRQ becomes" 1 ", the state shifts to the WRITE state ST2.

  Further, the state machine 155 indicates that the cycle count CYC is “1”, the condition 1 is “false”, the value of the external bus release request register 156 is “0”, and the second bus use request signal SBR is “ 1 ”and when the unified write request signal CWRQ becomes“ 0 ”, the process proceeds to the same READ state ST3.

  Furthermore, when the cycle count CYC is “1”, the condition 1 is “true”, and the condition 2 shown in FIG. 21 is “true”, the state machine 155 shifts to the STEAL state ST4. .

  Here, the condition 2 is a condition that becomes “true” when the wave data bus request signal EWAB is “1” or the envelope data bus request signal EEVB is “1”.

  Therefore, even when a bus master other than the sound processor 7 is in read access, when the cycle count CYC is “1”, the sound processor 7 issues the wave data bus request signal EWAB or the envelope data bus request signal EEVB. Then, the state shifts to the STEAL state ST4 and the read access of the sound processor 7 is interrupted. However, since the transition to the STEAL state ST4 is that the condition 1 is “true”, all the remaining read data cannot be read in one bus cycle. In other words, since the condition 1 is “false”, when all the remaining read data can be read in one bus cycle, the READ state ST3 is maintained to finish the read access of the bus master.

  Next, state transition from the STEAL state ST4 will be described.

  When the cycle count CYC becomes “1”, the state machine 155 proceeds to the READ state ST3.

  Now, the state transition of FIG. 21 will be described in detail based on the description of the state machine 155 by HDL (hardware description language). In this case, the following is assumed. Similarly to the above, the logic is reflected at the next rising edge of the internal clock signal ICLK. Basically, it is described in positive logic. However, the unified lower byte enable signal CLWBE, the unified upper byte enable signal CUPBE, the upper byte enable signal UPBE, and the lower byte enable signal LWBE are negative logic. In addition, “=” means an equal sign in a conditional statement, and means assignment otherwise.

  In the following description, the write acceptance signal WRAC, the write data holding value WDSV, the random access cycle number holding value RACSV, the second bus address holding value EADSV, the first area select holding value FSSV, the second area select holding value SSSV, The second bus width signal SBW, the second bus width holding value SBWSV, the read permission signal REGR, the read permission holding value REGRSV, the page access cycle number holding value PACSV, the lower byte read permission signal LWRG, and the upper byte read permission signal UPRG are: Since it is an internal signal of the state machine 155, it is not shown in FIG.

  [IDLE state ST0]

  The state machine 155 includes the second bus address output enable signal EADOE = 1, the external data output enable signal EDAOE = 0 (that is, the data bus of the second bus 33 is set to Hi-Z), and the external write enable signal EWRE = 0. , And the external read enable signal ERDE = 0.

  If the external bus release request register 156 = 1, the later-described FREE common logic is executed. Otherwise, if the second bus use request signal SBR = 1, the later-described ACCESS common logic is executed. In this case, IDLE common logic described later is executed.

  [FREE state ST1]

(1) <When cycle count CYC ≠ 1>

  The state machine 155 decrements the cycle count CYC by one.

(2) <When cycle count CYC ≠ 1, that is, when cycle count CYC = 1>

  The state machine 155 sets the second bus address output enable signal EADOE = 0.

  If the external bus release request register 156 = 0, the state machine 155 sets the second bus address output enable EADOE = 1 and the state to the IDLE state ST0.

  [WRITE state ST2]

  (1) <When cycle count CYC ≠ 1>

  (1-1) The state machine 155 sets the write acceptance signal WRAC [8: 0] = 0b000000000000, the external write enable signal EWRE = 1, and the external data output enable signal EDAOE = 1. Here, the reason why the write acceptance signal WRAC [8: 0] is negated is that data writing to the external memories 45 to 47 is not completed because the bus cycle is in progress.

  (1-2) If the second bus address EAD [0] = 1, the state machine 155 causes the external data EDAO [15: 8] = write data holding value WDSV [15: 8], external data EDAO [7 : 0] = write data holding value WDSV [15: 8]. Since writing is performed in units of bytes, the external memories 45 to 47 are written when the data bus width is 16 bits and the external data EDAO [15: 8], and when the data bus width is 8 bits. Is external data EDAO [7: 0].

  On the other hand, when the second bus address EAD [0] = 1 is not set, that is, when the second bus address EAD [0] = 0, the state machine 155 causes the external data EDAO [15: 0] = write data holding value WDSV [ 15: 0]. Since writing is performed in units of bytes, the external data EDAO [7: 0] is written to the external memories 45 to 47.

  (1-3) The state machine 155 decrements the cycle count CYC by 1.

  (2) <When cycle count CYC ≠ 1, that is, when cycle count CYC = 1 and byte count BYC ≧ 2>

  The state machine 155 includes a write acceptance signal WRAC [8: 0] = 0b000000000000, an external write enable signal EWRE = 0, an external data output enable signal EDAOE = 0, a cycle count CYC = a random access cycle number holding value RACSV, and a second bus address. EAD [26: 0] = second bus address EAD [26: 0] +1, and upper byte enable signal UPBE = a value obtained by logically inverting the second bus address EAD [0]. Also, the byte count BYC is decremented by one. Here, the reason why the write acceptance signal WRAC [8: 0] is negated is that data to be written remains.

  (3) <When the cycle count CYC ≠ 1, that is, when the cycle count CYC = 1, and when the byte count ≧ 2, that is, when the byte count = 1.

  The state machine 155 sets the external write enable signal EWRE = 0 and the external data output enable signal EDAOE = 0. If the external bus release request register 156 = 1, the later-described FREE common logic is executed. Otherwise, if the second bus use request signal SBR = 1, the later-described ACCESS common logic is executed. In this case, IDLE common logic described later is executed.

  [READ state ST3]

  (1) The state machine 155 sets the external write enable signal EWRE = 0 and the external data output enable signal EDAOE = 0.

  (2) <When cycle count CYC ≠ 1>

  The state machine 155 decrements the cycle count CYC by 1, and sets the external read enable signal ERDE = 1.

  (3) <When cycle count CYC ≠ 1 is not true, that is, when cycle count CYC = 1 and Condition 1 in FIG. 21 is “true”>

  (3-1) <When Condition 2 in FIG. 21 is “True”>

  (3-1-1) The state machine 155 sets the external read enable signal ERDE = 0.

  (3-1-2) If the second bus width signal SBW = 1, the second bus address EAD [0] = 0, and the byte count BYC ≧ 3, the state machine 155 decrements the byte count BYC by two. Then, the second bus address hold value EADSV [26: 0] = the second bus address EAD [26: 0] +2. On the other hand, in other cases, when the byte count BYC ≧ 2, the state machine 155 decrements the byte count BYC by 1, and the second bus address hold value EADSV [26: 0] = second bus address. Let EAD [26: 0] +1.

  (3-1-3) The state machine 155 includes the second bus address EAD [26: 1] = the unified address CADR [26: 1], the second bus address EAD [0] = the unified lower byte enable signal CLWBE, the first Area select signal ASSEL1 = unified first area select signal CASEL1, second area select signal ASSEL2 = unified second area select signal CASEL2, second bus width holding value SBWSV = second bus width signal SBW, second bus width signal SBW = Unified bus width signal CBW, upper byte enable signal UPBE = unified upper byte enable signal CUPBE, cycle count CYC = unified random access cycle number signal CRCY, read permission holding value REGRSV = read permission signal REGR, read permission signal REGR = bus master select signal EBMS , The state and STEAL state ST4.

  (3-2) <When Condition 2 in FIG. 21 is “False”>

  (3-2-1) The state machine 155 sets the first area select signal ASSEL1 = first area select hold value FSSV and the second area select signal ASSEL2 = second area select hold value SSSV.

  (3-2-2) If the second bus width signal SBW = 1, the second bus address EAD [0] = 0, and the byte count BYC ≧ 3, the state machine 155 decrements the byte count BYC by two. The second bus address EAD [26: 0] = the second bus address EAD [26: 0] +2. On the other hand, if the byte count BYC ≧ 2, the state machine 155 decrements the byte count BYC by one, and the second bus address EAD [26: 0] = second bus address EAD [ 26: 0] +1.

  (3-2-3) If the second bus width signal SBW = 1, the state machine 155 sets the upper byte enable signal UPBE = 0, otherwise, that is, the second bus width signal SBW. In the case of = 0, the state machine 155 assumes that the upper byte enable signal UPBE = the value obtained by logically inverting the second bus address EAD [0].

  (3-2-4) <When second bus width signal SBW = 1>

  If the logical sum of each bit of the second bus address EAD [3: 1] and each bit of the unified page boundary signal CPB [3: 1] is not “0b111”, the state machine 155 Count CYC = unified page access cycle number signal CPCY and external read enable signal ERDE = 1. On the other hand, when the logical sum of each bit of the second bus address EAD [3: 1] and each bit of the unified page boundary signal CPB [3: 1] is “0b111”, the state machine 155 Cycle count CYC = random access cycle number holding value RACSV, external read enable signal ERDE = 0. These points will be described in detail.

  In this embodiment, for example, the decoder 154 sets the page boundary signal CPB to “0b1111” when the page size is 0 bytes, sets the page boundary signal CPB to “0b1100” when the page size is 4 bytes, and sets the page boundary signal CPB to 8 bytes when the page size is 8 bytes. CPB is set to “0b1000”, and the page boundary signal CPB is set to “0b0000” for 16 bytes.

  Here, the second bus width signal SBW = 1 means that the data bus width of the second bus 33 is 16 bits, that is, one word of the external memories 45 to 47 is composed of 16 bits. In this case, when the second bus address EAD changes to indicate the next word, the second bus address EAD [0] remains “0” and does not change, and the second bus address EAD [26: 1]. The value of is incremented.

  Considering this, the case where the page boundary signal CPB [3: 0] is “0b1100” (indicating 4 bytes) will be described as an example. In this case, since the page size is 4 bytes, the range of “0b000” and “0b001” of the second bus address EAD [3: 1] is within the same page. That is, when one page is 4 bytes, the second bus address EAD [1] changes from “0b0” to “0b1” in the same page.

  Accordingly, in the last word of the 4-byte page, the second bus address EAD [1] is “0b1”. Therefore, the logical sum of each bit of the page boundary signal CPB [3: 1] (0b110) and each bit of the second bus address EAD [3: 1] (0b ** 1) indicating the last word of the page. Is always “0b111”. In this way, it is determined whether or not the word indicated by the second bus address EAD is the last word of the page. Note that “*” is an arbitrary value.

  (3-2-5) <When second bus width signal SBW = 0>

  If the logical sum of each bit of the second bus address EAD [3: 0] and each bit of the unified page boundary signal CPB [3: 0] is not “0b1111”, the state machine 155 Count CYC = unified page access cycle number signal CPCY and external read enable signal ERDE = 1. On the other hand, when the logical sum of each bit of the second bus address EAD [3: 0] and each bit of the unified page boundary signal CPB [3: 0] is “0b1111”, the state machine 155 Cycle count CYC = random access cycle number holding value RACSV, external read enable signal ERDE = 0. These points will be described in detail.

  The second bus width signal SBW = 0 is when the data bus width of the second bus 33 is 8 bits, that is, one word of the external memories 45 to 47 is configured with 8 bits. In this case, when the second bus address EAD changes to point to the next word, the value of the second bus address EAD [26: 0] is incremented.

  Based on this, the case where the page boundary signal CPB is “0b1100” (indicating 4 bytes) will be described as an example. In this case, since the page size is 4 bytes, the range of “0b0000”, “0b0001”, “0b0010”, “0b0011” of the second bus address EAD [3: 0] is within the same page. That is, when one page is 4 bytes, the second bus address EAD [1: 0] changes from “0b00” → “0b01” → “0b10” → “0b11” in the same page.

  Accordingly, the second bus address EAD [1: 0] is “0b11” in the last word of the 4-byte page. Therefore, the logical sum of each bit of the page boundary signal CPB [3: 0] (0b1100) and each bit of the second bus address EAD [3: 0] (0b ** 11) indicating the last word of the page Is always “0b1111”. In this way, it is determined whether or not the word indicated by the second bus address EAD is the last word of the page. Note that “*” is an arbitrary value.

  (4) <In the READ state ST3, when the cycle count CYC is not 1, that is, when the cycle count CYC = 1 and the condition 1 in FIG. 21 is “false”>

  The state machine 155 sets the external read enable ERDE = 0. If the external bus release request register 156 = 1, the later-described FREE common logic is executed. Otherwise, if the second bus use request signal SBR = 1, the later-described ACCESS common logic is executed. In this case, IDLE common logic described later is executed.

  [STEAL state ST4]

  (1) <When cycle count CYC ≠ 1>

  The state machine 155 sets the external read enable signal ERDE = 1 and decrements the cycle count CYC by one.

  (2) <When the cycle count CYC ≠ 1, that is, when the cycle count CYC = 1>

  (2-1) The state machine 155 determines that the external read enable signal ERDE = 0, the second bus address EAD [26: 0] = the second bus address hold value EADSV [26: 0], and the first area select signal ASSEL1 = first It is assumed that one area select hold value FSSV, second area select signal ASSEL2 = second area select hold value SSSV, and second bus width signal SBW = second bus width hold value SBWSV.

  (2-2) If the second bus width holding value SBWSV = 1, the state machine 155 sets the upper byte enable signal UPBE = 0, otherwise (that is, if the second bus holding value SBWSV = 0). ), A value obtained by inverting the second bus address hold value EADSV [0] is substituted for the upper byte enable signal UPBE.

  (2-3) The state machine 155 determines that the cycle count CYC = random access cycle count holding value RACSV [2: 0], the read permission signal REGR [8: 0] = read permission holding value REGRSV [8: 0] The READ state ST3 is assumed.

  [IDLE common logic]

  The state machine 155 sets the read permission signal REGR [8: 0] = 0 and sets the state to the IDLE state ST0.

  [FREE common logic]

  The state machine 155 has a second bus address EAD [26: 0] = 0x4000000, an upper byte enable signal UPBE = 1, a first area select signal ASSEL1 = 0, a second area select signal ASSEL2 = 0, a cycle count CYC = 0, The state is a FREE state ST1.

  Here, “0x4000000” is an address that is not used in both read and write accesses. The cycle count CYC “0” indicates that one bus cycle is set to 8 clock cycles. The lower byte enable signal LWBE behaves the same as the second bus address EAD [0].

  [ACCESS common logic]

  (1) The state machine 155 determines that the second bus width signal SBW = the unified bus width signal CBW, the second bus address EAD [26: 1] = the unified address CADR [26: 1], and the second bus address EAD [0] = Unified lower byte enable signal CLWBE, upper byte enable signal UPBE = unified upper byte enable signal CUPBE, first area select signal ASSEL1 = unified first area select signal CASEL1, first area select hold value FSSV = unified first area select signal CASEL1 , Second area select signal ASSEL2 = unified second area select signal CASEL2, second area select hold value SSSV = unified second area select signal CASEL2, cycle count CYC = unified random access cycle number signal CRCY, random access cycle number Lifting value RACSV = unified random access cycle number signal CRCY, page access cycle number value PACSV = unified page access cycle number signal CPCY, and byte count BYC = unified size signal CSZ, to.

  (2) <When unified write request signal CWRQ = 1>

  The state machine 155 has a write acceptance signal WRAC [8: 0] = bus master select signal EBMSL [8: 0], a read permission signal REGR [8: 0] = 0b000000, and a write data holding value WDSV [15: 0] = unified write. The data CWD [15: 0] and the state are set to the WRITE state ST2.

  (3) <When unified write request signal CWRQ = 1, that is, when unified write request signal CWRQ = 0>

  The state machine 155 sets the read permission signal REGR [8: 0] = bus master select signal EBMSL [8: 0] and the state to the READ state ST3.

  [Read permission signal generation logic]

  (1) <When cycle counter CYC = 1>

  (1-1) <When Second Bus Width Signal SBW = 1 (means 16-bit Data Bus Width)>

  The state machine 155 has a lower byte read permission signal LWRG [8: 0] = read permission signal REGR [8: 0] and an upper byte read permission signal UPRG [8: 0] = read permission signal REGR [8: 0]. , And.

  (1-2) <When Second Bus Width Signal SBW = 1, That is, When Second Bus Width Signal SBW = 0 (means 8-bit Data Bus Width)>

  When the second bus address EAD [0] = 0, the state machine 155 causes the lower byte read permission signal LWRG [8: 0] = read permission signal REGR [8: 0] and the upper byte read permission signal UPRG [8]. : 0] = 0b000000000000.

  When the second bus address EAD [0] = 0 is not set, that is, when the second bus address EAD [0] = 1, the state machine 155 determines that the lower byte read permission signal LWRG [8: 0] = 0b000000000000 Byte read permission signal UPRG [8: 0] = read permission signal REGR [8: 0].

  (2) <When other than cycle counter CYC = 1>

  The state machine 155 sets the lower byte read permission signal LWRG [8: 0] = 0b000000000000 and the upper byte read permission signal UPRG [8: 0] = 0b000000000000.

  (3) The state machine 155 sends the read permission signals REGR [0] to REGR [8] to the wave data / read permission signal EWARG, the envelope data / read permission signal EEVRG, and the bitmap data / read permission signal EBMRG, respectively. , Character data / read permission signal ECDRG, character header / read permission signal ECHRG, pixel plotter / read permission signal EPPRG, DMA source / read permission signal EDSRG, data access / read permission signal EDARG, and instruction fetch / read permission signal EIFRG To do.

  (4) The state machine 155 sends the lower byte read permission signals LWRG [0] to LWRG [8] to the wave data / lower byte read permission signal EWALR, envelope data / lower byte read permission signal EEVLR, and bitmap, respectively. Data / lower byte read enable signal EBMLR, character data / lower byte read enable signal ECDLR, character header / lower byte read enable signal ECHLR, pixel plotter / lower byte read enable signal EPPLR, DMA source / lower byte read enable signal EDSLLR, data The access / lower byte read permission signal EDALR and the instruction fetch / lower byte read permission signal EIFLR are used.

  (5) The state machine 155 sends the upper byte read permission signals UPRG [0] to UPRG [8] to the wave data / upper byte read permission signal EWAUR, envelope data / upper byte read permission signal EEVUR, and bitmap, respectively. Data / upper byte read enable signal EBMUR, character data / upper byte read enable signal ECDUR, character header / upper byte read enable signal ECHUR, pixel plotter / upper byte read enable signal EPPUR, DMA source / upper byte read enable signal EDSUR, data The access / upper byte read permission signal EDAUR and the instruction fetch / upper byte read permission signal EIFUR are used.

  [Write acceptance signal generation logic]

  In the state machine 155, the write acceptance signal WRAC [5] is the pixel plotter / write acceptance signal EPPWG, and the write acceptance WRAC [7] is the data access / write acceptance signal EDAWG.

  As described above, in the present embodiment, the CPU 1, the graphic processor 3, the sound processor 7, and the DMA controller 9 of the current generation processor 100 are the CPU 501, the graphic processor 503, and the sound of the previous generation processor 500, respectively. It has the same functions as the processor 507 and the DMA controller 509. However, the graphic processor 3 has a newly added function in addition to the function of the graphic processor 503.

  Therefore, in the current generation processor 100, the CPU 1, the graphic processor 3, the sound processor 7, and the DMA controller 9 are referred to as a common bus master group. In the current generation processor 100, a group obtained by adding the pixel plotter 5 to the common bus master group is referred to as a current generation bus master group. In the previous generation processor 500, the CPU 501, the graphic processor 503, the sound processor 507, and the DMA controller 509 are referred to as a common bus master group.

  In the priority information set of the second bus arbiter 14 of the current generation processor 100, when a plurality of second bus use request factors are included in one bus master, priority is given consecutively to the plurality of second bus use request factors. A rank is assigned. This will be described using the priority information set corresponding to the priority information number 0 in FIG. 14 as an example. For example, the graphic processor 3 includes three second bus use request factors, that is, a character header HDR, character data CHR, and bitmap data BMP, which have a third priority, a fourth priority, respectively. Consecutive priorities are assigned such as a priority order and a fifth priority order. For this reason, the priority information set of the second bus arbiter 14 is assigned a priority for each bus master from software (compatible software) that can be executed in the previous generation processor 500 that does not make a bus use request for each bus use request factor. Looks like it was decided.

  Moreover, the priority among the bus masters of the common bus master group in the priority information set of the second bus arbiter 14 is the same as the priority between the corresponding bus masters in the priority information set of the second bus arbiter 514 of the previous generation processor 500. is there. This will be described by taking the priority information set corresponding to priority information number 0 in FIG. 12 and the priority information set corresponding to priority information number 0 in FIG. 14 as examples. As shown in FIG. 14, if attention is paid to the common bus master group and the second bus use request factor is ignored, that is, if attention is paid only to the bus master, the sound processor 7, graphic processor 3, It becomes the DMA controller 9 and the CPU 1. On the other hand, as shown in FIG. 12, the sound processor 507, graphic processor 503, DMA controller 509, and CPU 501 are in descending order of priority. As can be seen from the above, in the common bus master group, the priority order of the bus masters is the same between the second bus arbiter 14 and the second bus arbiter 514.

  The same can be said for the relationship between the priority information of the first bus arbiter 12 of the current generation processor 100 and the priority information of the first bus arbiter 512 of the previous generation processor 500.

  As a result, even when the bus master of the current generation processor 100 makes a bus use request for each bus use request factor, the software that can be executed in the previous generation processor 500 (that is, compatible software) can be executed normally. Backwards compatibility for bus arbitration is maintained.

  In the previous generation processor 500, the access cycle number for accessing the second bus first area in the logical address space and the access cycle number for accessing the second bus second area have a common value. Can only be set. That is, as shown in FIG. 13, a register for setting the number of access cycles is common to the second bus first area and the second bus second area.

  On the other hand, in the current generation processor 100, the number of access cycles for accessing the second bus first area in the logical address space and the number of access cycles for accessing the second bus second area can be set separately. . That is, as shown in FIG. 15, a register 171 for setting the number of random access cycles for the second bus first area and a register 172 for setting the number of random access cycles for the second bus second area are provided independently. (See FIG. 20).

  However, when the compatible software executed by the current generation processor 100 performs an operation of rewriting the contents of the virtual first and second area access cycle number registers shown in FIG. 15, that is, the current generation processor 100. The compatible software executed in accordance with the above is for the address where the virtual first and second area access cycle number registers are arranged (the same address as the address of the first and second area access cycle number registers of the previous generation processor 500). When the write operation is performed, the contents of both the first area random access cycle number register 171 and the second area random access cycle number register 172 of the current generation processor 100 are the virtual first and second area access cycles. Number register contents (ie, previous generation processor 500 Rewritten to be the same as the first and the contents of the second region access cycle number register).

  As a result, from the viewpoint of the number of access cycles (that is, access speed), the address area is not divided into a plurality of areas for the previous generation processor 500, but is divided into a plurality of areas for the current generation processor 100. Even in such a case, software that can be executed in the previous generation processor 500 (that is, compatible software) can be normally executed, and backward compatibility with respect to the access speed to the address area is maintained.

  Further, the previous generation processor 500 does not have a function of accessing the memories 545 to 547 connected to the external bus 543 in the page mode. On the other hand, the current generation processor 100 has a function of accessing the memories 45 to 47 connected to the external bus 43 in the page mode.

  However, when the compatible software executed by the current generation processor 100 performs an operation of rewriting the contents of the virtual 0th area access cycle number register shown in FIG. 15, that is, executed by the current generation processor 100. When the compatible software performs a write operation on the address where the virtual 0th area access cycle number register is arranged (address where the 0th area access cycle number register is arranged in the previous generation processor 500), The contents of the 0th area random access cycle number register 170 of the current generation processor 100 are the contents of the virtual 0th area access cycle number register (that is, the contents of the 0th area access cycle number register of the previous generation processor 500). It can be rewritten to be the same and 1 Over size di is the zeroth region page size register 190 to indicate "0" is set, not performed accessed in the page mode.

  As a result, even when the previous generation processor 500 does not support the page mode, software that can be executed by the previous generation processor 500 (that is, compatible software) can be executed normally, and the access mode to the address area can be controlled. Backwards compatibility is maintained.

  Furthermore, in the present embodiment, when the compatible software executed by the current generation processor 100 performs an operation of rewriting the contents of the virtual first and second area access cycle number registers shown in FIG. When the compatible software executed by the current generation processor 100 performs a write operation on the address where the virtual first and second area access cycle number registers are arranged, the first software of the current generation processor 100 The contents of both the area random access cycle number register 171 and the second area random access cycle number register 172 are rewritten to be the same as the contents of the virtual first and second area access cycle number registers, and one page The first area page size register 191 so that the size indicates “0”. Is set beauty second region page size register 192, the access in the page mode is not performed.

  As a result, from the viewpoint of the number of access cycles (that is, access speed), the address area is not divided into a plurality of areas for the previous generation processor 500, but is divided into a plurality of areas for the current generation processor 100. Even when the previous generation processor 500 does not support the page mode, software that can be executed by the previous generation processor 500 (that is, compatible software) is executed normally. The backward compatibility with respect to the access speed and the access mode to the address area is maintained.

  Furthermore, in the present embodiment, the logical address space of the previous generation processor 500 is indicated by address information of P (P is an integer of 1 or more) bits (24 bits in the example of FIG. 6). On the other hand, the logical address space of the current generation processor 100 is indicated by address information of Q (Q is an integer greater than or equal to 2 greater than P) bits (27 bits in the example of FIG. 7). The logical address space of the current-generation processor 100 is the first address space (the logical address space of the previous-generation processor 500 and the first address space in which the upper (QP) bits of the Q-bit address information indicate “0”. And the second address space including all other spaces.

  Therefore, when the compatible software created for the previous generation processor 500 is executed by the current generation processor 100, the upper (QP) bit of the Q bit address information is simply set to “0” and output. The current generation processor 100 can access the same first address space as the logical address space of the previous generation processor 500 and can easily maintain compatibility with the address space.

  Further, the graphic processor 3 of the current generation processor 100 having the same function as that of the graphic processor 503 of the previous generation processor 500 has not only the first address space but also the second address space that the graphic processor 503 cannot access. It has an additional function that can be accessed (that is, three added addressing modes), and the accessible address area can be expanded while maintaining backward compatibility with the processor 500 of the previous generation.

  Further, the current generation processor 100 is provided with a pixel plotter 5 having a new function compared to the previous generation processor 500 so that both the first address space and the second address space can be accessed. However, since the previous generation processor 500 is not provided with a bus master having the same function as that of the pixel plotter 5, it does not affect the maintenance of backward compatibility with the previous generation processor 500. Thus, in the current generation processor 100, a bus master having a new function can be added while maintaining backward compatibility.

  Now, according to the present embodiment, the function of the second bus arbiter 14 of the current generation processor 100 provides the following effects.

  Since the second bus arbiter 14 provides the number of bus cycles corresponding to the size requested by the bus master (see FIG. 19), the bus master can read / write data continuously. While giving the bus master the advantage that bus cycles can be acquired in this way, the arbitration operation is always performed in units of the number of bus cycles according to the size requested by the bus master, increasing the bus usage efficiency. And the latency of the response to the bus use request from the bus master can be made as small as possible.

  In addition, since the bus master issues size signals EIFS, ECHS, ECDS, EPPS, EDSS indicating the size of data to be read or written, it is possible to issue a size signal indicating a size sufficient for data transfer. The state machine 155 can set an optimal number of bus cycles. Therefore, in this case, it is possible to further improve the bus use efficiency and further shorten the latency of the response to the bus use request.

  Further, the state machine 155 gives a bus use permission for N bus cycles represented by the following equation (hereinafter referred to as an optimum bus cycle number calculation equation) to the bus master selected by the priority decoder 142.

  N = ((A + B-1) / W)-(A / W) +1

  However, “A” is address information issued when the bus master issues a bus use request, and is address information indicating the first byte to be read or written by a byte address. This “A” corresponds to the unified address CADR in FIG.

  “B” is size information of data read or written by the bus master, and is represented by the number of bytes. This “B” corresponds to the unified size signal CSZ in FIG. Thus, in this embodiment, the bus master requests the size of data to be read or written by the number of bytes.

  “W” indicates the number of bytes of the data bus width of the area indicated by the address information A. This “W” corresponds to the number of bytes of the data bus indicated by the unified bus width signal CBW in FIG. That is, if the unified bus width signal CBW is “0”, the bus width of the data bus is 1 byte (= 8 bits), and if the unified bus width signal CBW is “1”, the bus width of the data bus is 2 bytes (= 16 bits).

  The address information A indicates how many bytes from the 0th byte the starting end of the data to be read / written is. Therefore, (A + B-1) indicates the number of bytes from the 0th byte to the end of the data to be read / written.

  Since the number of bytes W of the data bus width of the area indicated by the address information A indicates the number of bytes constituting one word of the connected external memories 45 to 47, ((A + B-1) / W) is read / write The number of words from the 0th word corresponds to the end of the data to be read, and (A / W) represents the number of words from the 0th word to the start of the data to be read / written. Therefore, in other words, N indicates the number of words of data to be read / written. Therefore, assuming that one word of data is transferred in one bus cycle, it can be easily understood that N indicates the number of bus cycles required for data transfer.

  Further, the CPU 1 sets values in the 0th area bus width register 160, the first area bus width register 161, and the second area bus width register 162, thereby reducing the number of bytes W of the data bus width to the area (second area). It can be set for each bus 0th area, second bus 1st area, second bus 2nd area (see FIG. 7).

  Then, the address decoder 149 has the address information A issued by the bus master selected by the priority decoder 142, that is, the unified address CADR, in three areas (second bus 0th area, second bus first area, second bus second). The multiplexer 151 selects one of the three data bus widths according to the determination result, and supplies it to the state machine 155 as a unified bus width CBW.

  The state machine 155 calculates N from the optimum bus cycle number calculation formula based on the number of bytes W of the data bus indicated by the unified bus width CBW.

  Therefore, even when the address space is divided into a plurality of areas and each area has a different data bus width, the state machine 155 is necessary and sufficient in accordance with the data bus width of the area to be accessed. Any number of bus cycles can be provided to the bus master.

  Further, when the bus master other than the sound processor 7 uses the second bus 33, the state machine 155 receives a bus use request (wave data bus request EWAB or envelope data bus request EEVB) from the sound processor 7. If there is, the bus master of the bus master using the second bus 33 is interrupted on the condition that the number of remaining bus cycles is equal to or greater than a predetermined value, and the bus use permission is given to the sound processor 7.

  Therefore, it is possible to perform rapid processing of a bus master having a high degree of urgency such as the sound processor 7 while giving the bus master the advantage of continuously acquiring bus cycles. Details are as follows. Giving the bus master permission to use successive bus cycles has the effect of increasing the data throughput of the entire bus, but the latency from when the bus master issues a bus use request until the bus use is granted increases. If there is an urgent bus master that must complete within a predetermined time from the bus use request to obtaining the bus use permission, such an increase in latency may cause a problem in the operation of the system. . Therefore, if there is a bus use request from a bus master with a high degree of urgency and the number of remaining bus cycles of the bus master that is currently using the bus exceeds a predetermined value, the bus use of the bus master with a high degree of urgency should be interrupted. Thus, it is possible to avoid the disadvantage of increased latency while increasing throughput.

  Thus, since the bus use request of the sound processor 7 is prioritized, it is possible to prevent the discontinuity in the output of the audio signal AU.

  Further, the first bus arbiter 13 performs arbitration for each first bus use request factor (see FIG. 10), and the second bus arbiter 14 performs arbitration for each second bus use request factor (see FIG. 14). Therefore, the following effects are produced.

  If the bus master has multiple bus use request factors and the bus arbiter only performs arbitration for each bus master, a circuit for arbitrating bus use requests is required in each bus master, increasing the overall circuit scale To do. Further, depending on the circuit configuration, a time overhead for arbitrating the bus use request factor occurs. When the bus arbiter (the first bus arbiter 13 and the second bus arbiter 14) performs arbitration for each bus use request factor as in the present embodiment, such a disadvantage does not occur.

  Further, the plurality of bus masters can issue size signals EIFS, ECDS, EPPS, EDSS indicating different sizes for each second bus use request factor (see FIG. 19). The same applies to the first bus use request factor.

  In this way, a size signal indicating a different size according to the required data size can be issued for each bus use request factor, reducing unnecessary data access and further improving the bus use efficiency and bus use request. It is possible to shorten the latency of response to.

  Further, a plurality of priority information sets (16 priority registers 300 to 315 holding any of the priority information numbers 0 to 3 in FIG. 10 for the first bus arbiter 13, and FIG. 14 for the second bus arbiter 14 are shown in FIG. By sequentially and cyclically selecting the eight priority registers 200 to 207 that hold any one of the priority information numbers 0 to 3, the distribution ratio of the bus cycles to the bus master can be controlled.

  Furthermore, since the CPU 1 can set one bus cycle period by writing a value to the registers 170 to 172 and 180 to 182, each area (second bus 0th area, second bus first area, second bus first) The period length of the bus cycle with respect to (2 areas) can be optimized according to the speed of the external memories 45 to 47 connected to the second bus 33. In addition, by dynamically changing the length of one bus cycle period by the CPU 1, it is possible to expect an effect of saving power consumption according to the operation mode.

  In this way, since the CPU 1 can dynamically set the random access cycle number and the page access cycle number, the number of clock cycles indicating one bus cycle period is set to the external memory 45 to the second bus 33. 47 random access speeds and page access speeds in page mode access can be optimized.

  Furthermore, when the number of bus cycles given to the bus master that has obtained the bus use permission is “1”, the state machine 155 adopts the unified random access cycle number CRCY as the bus cycle.

  Here, the case where the bus cycle number given to the bus master is “1” is a case where N calculated by the optimum bus cycle number calculation formula is 1, for example, the bus width indicated by the unified bus width signal CBW is 2 bytes. In the case where the size indicated by the unified size signal CSZ is 2 bytes, or when the bus width indicated by the unified bus width signal CBW is 1 byte, the size indicated by the unified size signal CSZ is 1 byte, etc. is there.

  On the other hand, the state machine 155 adopts the uniform random access cycle number CRCY as the bus cycle in the first bus cycle when the number of bus cycles given to the bus master that has obtained the bus use permission is “2” or more. In other bus cycles, if the second bus address EAD points to the same page as the second bus address EAD of the immediately preceding bus cycle, the uniform page access cycle number CPCY is adopted, and the second bus address EAD is the immediately preceding bus. If the page is different from the second bus address EAD of the cycle, the unified random access cycle number CRCY is adopted.

  Here, the case where the bus cycle number given to the bus master is “2” or more is a case where N calculated by the optimum bus cycle number calculation formula is 2 or more. For example, the bus width indicated by the unified bus width signal CBW is In the case of 2 bytes, when the size indicated by the unified size signal CSZ is 4 bytes, or when the bus width indicated by the unified bus width signal CBW is 1 byte, when the size indicated by the unified size signal CSZ is 2 bytes, Etc.

  As described above, when the external memories 45 to 47 having the page mode access function are connected to the second bus 33, the bus cycle period length (the number of clocks per bus cycle) can be optimized.

  Further, the CPU 1 can dynamically set the page size by setting values in the registers 190 to 192. For this reason, it can be matched with the page size of the external memories 45 to 47 to be connected.

  Further, the address space of the second bus 33 is divided into three areas (see FIG. 7), and the number of bytes W of the data bus width, the number of random access cycles, the number of page access cycles, and the page size are registered in registers 160 to 162. , 170 to 172, 180 to 182, and 190 to 192, the values can be set for each of the three areas. Then, the address decoder 149 has the address information A issued by the bus master selected by the priority decoder 142, that is, the unified address CADR, in three areas (second bus 0th area, second bus first area, second bus second). The multiplexers 151 to 153 and the decoder 154 select one of the three areas according to the determination result, and the unified bus width signal CBW, the unified random access cycle number signal CRCY, The unified page access cycle number signal CPCY and the unified page boundary signal CPB are supplied to the state machine 155.

  The state machine 155 calculates N from the optimum bus cycle number calculation formula based on the number of bytes W of the data bus indicated by the unified bus width CBW.

  Therefore, when the address space is divided into a plurality of areas and external memories 45 to 47 having different random access speed, page access speed, page size and data bus width are connected to each area, the second bus arbiter 14 is For each arbitration operation, the bus cycle period length and the number of bus cycles given to the bus master are optimized by switching the number of random access cycles, page access cycles, page size, and data bus width based on the setting of the area to be accessed. It becomes.

  The present invention is not limited to the above-described embodiment, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

  (1) In the above, in the current generation processor 100, bus arbitration is performed for each bus use request factor. However, in the current generation processor 100, as in the previous generation processor 500, bus arbitration can be performed for each bus master.

  In this case, the priority among the bus masters of the common bus master group in the priority information set of the first bus arbiter 13 of the current generation processor 100 is set as the priority of the common bus master group in the priority information set of the first bus arbiter 513 of the previous generation processor 500. Same priority as bus masters. Similarly, the priority among the bus masters of the common bus master group in the priority information set of the second bus arbiter 14 of the current generation processor 100 is set to the priority of the common bus master group in the priority information set of the second bus arbiter 514 of the previous generation processor 500. Same priority as bus masters.

  As a result, software that can be executed in both the current generation processor 100 in which a new bus master (pixel plotter 5 in the above example) is added to the bus master included in the previous generation processor 500 and the previous generation processor 500 ( That is, compatible software) can be executed normally, and backward compatibility with respect to bus arbitration is maintained.

  (2) When the compatible software executed by the current generation processor 100 performs an operation of rewriting the contents of the virtual 0th area access cycle number register shown in FIG. 15, that is, executed by the current generation processor 100 When the compatible software performs a write operation to the address where the virtual 0th area access cycle number register is arranged, the 0th area random access cycle number register 170 and the 0th area of the processor 100 of the current generation The contents of both page access cycle number registers 180 can be rewritten to be the same as the contents of the virtual 0th area access cycle number register.

  Similarly, when the compatible software executed by the current generation processor 100 performs an operation of rewriting the contents of the virtual first and second area access cycle number registers shown in FIG. 15, that is, the current generation processor. When the compatible software executed by 100 performs a write operation on the address where the virtual first and second area access cycle number registers are arranged, the first area random access cycle number of the processor 100 of the current generation The contents of both the register 171 and the second area random access cycle number register 172 and the contents of both the first area page access cycle number register 181 and the second area page access cycle number register 182 are displayed in the virtual first and second areas. Same as the contents of the area access cycle number register It can also be rewritten to. However, in this case, the range of values that can be set in the random access cycle number register needs to be the same as the range of values that can be set in the page access cycle number register.

  As a result, since the random access mode and the page mode are substantially the same mode, even if the previous generation processor 500 supports only the random mode, software that can be executed in the previous generation processor 500 (that is, , Compatible software) can be executed normally, and the backward compatibility for the access mode to the address area is maintained.

  (3) In the above, in the address space of the current generation processor 100, the virtual 0th area access cycle number register and the virtual 1st and 2nd area access cycle number registers are the corresponding registers of the previous generation processor 500. It is mapped to an address. However, it is possible to map the registers of the current generation processor 100 to the address space without using such virtual registers.

  FIG. 22 shows a list of hardware control registers provided in the second bus arbiter 14 of FIG. 1 and mapped to an address different from the address shown in FIG. 15 in the logical address space of the processor 100 of the current generation. FIG. As shown in FIG. 22, the address assigned to the 0th area random access cycle number register of the current generation processor 100 is the same as the address assigned to the 0th area access cycle number register of the processor 500 of the previous generation. . Similarly, the address assigned to the first area random access cycle number register of the current generation processor 100 is the same as the address assigned to the first and second area access cycle number registers of the previous generation processor 500.

  Thus, when software that can be executed in the previous generation processor 500 (that is, compatible software) is executed on the current generation processor 100 and an instruction for accessing the 0th area access cycle number register is executed, the current generation The 0th area random access cycle number register of the processor 100 is accessed. Since the 0th area random access cycle number register of the current generation processor 100 functions as the 0th area access cycle number register of the previous generation processor 500 in the execution of the compatible software, there is no problem in maintaining compatibility. When the compatible software is executed on the current generation processor 100 and executes an instruction to access the first and second area access cycle number registers, the first area random access cycle number register of the current generation processor 100 is Accessed. Here, in the current generation processor 100, when an instruction to rewrite the first and second area access cycle number registers is executed, not only the first area random access cycle number register but also the second area random access cycle number register Must be rewritten.

Therefore, the current generation processor 100 needs to change the processing performed when this instruction is executed depending on whether the currently executed software is compatible software or incompatible software. If the compatible software is being executed, the current generation processor 100 executes the instruction to rewrite the first area random access cycle number register (that is, the instruction to rewrite the first and second area access cycle number registers). The two-region random access cycle number register is also rewritten and synchronized with the first region random access cycle number register. If incompatible software is being executed, the current generation processor 100 rewrites only the first area random access cycle number register when executing an instruction to rewrite the first area random access cycle number register. In one implementation, the current generation processor 100 has two execution modes, a compatible mode indicating that compatible software is being executed and an incompatible mode indicating that incompatible software is being executed. Is the initial mode. The incompatible software executes an instruction to switch to the incompatible mode in the startup routine.

  Alternatively, the switching function between the compatible mode and the incompatible mode can be implemented by using a control register.

  The foregoing description of the embodiments has been presented for purposes of illustration. It is not intended to limit the invention to the precise form described, and variations on the above teachings are possible. The embodiments have been chosen to most clearly explain the principles of the invention, thereby enabling those skilled in the art to make practical application thereof and invent in various variations and forms directed to the intended specific use. Can be used most effectively.

The foregoing and other features and objects of the invention and the manner in which they are accomplished will become more apparent and the invention itself will best be understood by reference to the following description of a preferred embodiment using the accompanying drawings. You can understand.
FIG. 1 is a block diagram showing an overall configuration of a current generation processor 100 as a data processing apparatus according to an embodiment of the present invention. FIG. 2A is an explanatory diagram of an 8-bit character number mode implemented in the current generation processor 100 shown in FIG. FIG. 2B is an explanatory diagram of a 16-bit character number mode implemented in the current generation processor 100 shown in FIG. FIG. 2C is an explanatory diagram of the aligned 16-bit pointer mode implemented in the current generation processor 100 shown in FIG. FIG. 3A is an explanatory diagram of the 16-bit address pointer mode implemented in the current generation processor 100 shown in FIG. FIG. 3B is an explanatory diagram of the 24-bit address pointer mode implemented in the current generation processor 100 shown in FIG. FIG. 4A is an explanatory diagram of the 16-bit extended character number mode implemented in the current generation processor 100 shown in FIG. FIG. 4B is an explanatory diagram of a 16-bit extended address pointer mode implemented in the current generation processor 100 shown in FIG. FIG. 4C is an explanatory diagram of a 24-bit pointer mode with alignment implemented in the current generation processor 100 shown in FIG. FIG. 5 is a block diagram showing the overall configuration of the previous generation processor 500 as the data processing apparatus according to the embodiment of the present invention. FIG. 6 is an explanatory diagram of the logical address space of the previous generation processor shown in FIG. FIG. 7 is an explanatory diagram of the logical address space of the current generation processor shown in FIG. FIG. 8 is a view for showing an example of a priority table included in the first bus arbiter 513 of FIG. FIG. 9 is a diagram showing a list of hardware control registers provided in the first bus arbiter 513 of FIG. FIG. 10 is a view for showing an example of a priority table included in the first bus arbiter 13 of FIG. FIG. 11 is a diagram showing a list of hardware control registers included in the first bus arbiter 13 of FIG. FIG. 12 is a view for showing an example of a priority table included in the second bus arbiter 514 of FIG. FIG. 13 is a diagram showing a list of hardware control registers included in the second bus arbiter 514 of FIG. FIG. 14 is a view showing an example of a priority table that the second bus arbiter 14 of FIG. 1 has. FIG. 15 is a diagram showing a list of hardware control registers provided in the second bus arbiter 14 of FIG. FIG. 16 is an explanatory diagram of input / output signals for the first bus arbiter 13 of FIG. FIG. 17 is a block diagram showing an internal configuration of the first bus arbiter 13 of FIG. FIG. 18 is an explanatory diagram of input / output signals for the second bus arbiter 14 of FIG. FIG. 19 is a view showing an example of a request size for each second bus use request factor implemented in the current generation processor 100 shown in FIG. FIG. 20 is a block diagram showing an internal configuration of the second bus arbiter 14 of FIG. FIG. 21 is an explanatory diagram of state transitions in the state machine 155 of FIG. FIG. 22 shows a list of hardware control registers provided in the second bus arbiter 14 of FIG. 1 and mapped to an address different from the address shown in FIG. 15 in the logical address space of the processor 100 of the current generation. FIG.

Claims (10)

A first bus master group composed of a predetermined number (two or more) of bus masters and a first bus that performs bus arbitration according to first priority information that defines priorities among the bus masters included in the first bus master group A data processing apparatus capable of executing any of software that can be executed by another predetermined data processing apparatus including arbitration means and software that cannot be executed by the predetermined other data processing apparatus,
A second bus master group including bus masters respectively corresponding to the bus masters of the first bus master group, and further adding one or more bus masters;
Second bus arbitration means for performing bus arbitration in accordance with second priority information that defines priorities among the bus masters included in the second bus master group;
The data processing device, wherein a priority order among the bus masters corresponding to the bus masters of the first bus master group in the second priority order information is the same as the first priority order information. A first bus master group composed of a predetermined number (two or more) of bus masters and a first bus that performs bus arbitration according to first priority information that defines priorities among the bus masters included in the first bus master group A data processing apparatus capable of executing any of software that can be executed by another predetermined data processing apparatus including arbitration means and software that cannot be executed by the predetermined other data processing apparatus,
A second bus master group including a bus master that corresponds to each of the bus masters included in the first bus master group and that requests bus use for each bus use request factor that exists for each bus master; and
Second bus arbitration means for performing bus arbitration according to second priority information that defines priorities among bus use request factors of all bus masters included in the second bus master group;
In the second priority information, when a plurality of bus use request factors are included in one bus master, consecutive priorities are assigned to the plurality of bus use request factors,
The data processing device, wherein the priority between the bus masters in the second priority information is the same as the priority between the corresponding bus masters in the first priority information. Software that can be executed by a predetermined other data processing apparatus including a first bus cycle period length information storage unit that determines a bus cycle period length when accessing a predetermined address area, and the predetermined other data processing apparatus A data processing device capable of executing any software that cannot be executed,
The predetermined address area as an access target by the data processing device is divided into a plurality of areas,
The data processing apparatus includes a plurality of second bus cycle period length information storage units that respectively correspond to the plurality of areas and determine a bus cycle period length when accessing the corresponding area.
When the software executed by the data processing apparatus and executable by the predetermined other data processing apparatus performs an operation of rewriting the contents of the first bus cycle period length information storage means, A data processing apparatus, wherein the content of the second bus cycle period length information storage means is rewritten so as to be equivalent to the content of the first bus cycle period length information storage means. Software that can be executed by a predetermined other data processing apparatus including a first bus cycle period length information storage unit that determines a bus cycle period length when accessing a predetermined address area, and the predetermined other data processing apparatus A data processing device capable of executing any software that cannot be executed,
Second bus cycle period length information storage means for determining a bus cycle period length when accessing the predetermined address area in the first access mode;
A third bus cycle period length information storing means for determining a bus cycle period length when accessing the predetermined address area in the second access mode,
When the software that can be executed by the predetermined other data processing apparatus executed by the data processing apparatus performs an operation of rewriting the contents of the first bus cycle period length information storage unit, the second Data processing in which the contents of the bus cycle period length information storage means and the contents of the third bus cycle period length information storage means are rewritten to be equivalent to the contents of the first bus cycle period length information storage means apparatus. Software that can be executed by a predetermined other data processing apparatus including a first bus cycle period length information storage unit that determines a bus cycle period length when accessing a predetermined address area, and the predetermined other data processing apparatus A data processing device capable of executing any software that cannot be executed,
Second bus cycle period length information storage means for determining a bus cycle period length when accessing the predetermined address area in a random access mode;
Third bus cycle period length information storage means for determining a bus cycle period length when accessing the predetermined address area in the page mode;
Page size information storage means for determining the size of one page in the page mode,
When the software that can be executed by the predetermined other data processing apparatus executed by the data processing apparatus performs an operation of rewriting the contents of the first bus cycle period length information storage unit, the second The bus cycle period length information storage means is rewritten so that the contents of the first bus cycle period length information storage means are equivalent to the contents of the first bus cycle period length information storage means, and the size of one page indicated by the page size information storage means is the page. A data processing device that can be rewritten to a value that invalidates the mode. Software that can be executed by a predetermined other data processing apparatus including a first bus cycle period length information storage unit that determines a bus cycle period length when accessing a predetermined address area, and the predetermined other data processing apparatus A data processing device capable of executing any software that cannot be executed,
The predetermined address area as an access target by the data processing device is divided into a plurality of areas,
The data processing device includes:
A plurality of second bus cycle period length information storage means that respectively correspond to the plurality of areas and determine a bus cycle period length when accessing the corresponding areas in a random access mode;
A plurality of third bus cycle period length information storage means that respectively correspond to the plurality of areas and determine a bus cycle period length when accessing the corresponding area in a page mode;
A plurality of page size information storage means that respectively correspond to the plurality of areas and determine the size of one page in the page mode,
When the software executed by the data processing apparatus and executable by the predetermined other data processing apparatus performs an operation of rewriting the contents of the first bus cycle period length information storage means, The contents of the second bus cycle period length information storage means are rewritten so as to be equivalent to the contents of the first bus cycle period length information storage means, and one page indicated by all the page size information storage means A data processing apparatus, wherein the size is rewritten to a value that invalidates the page mode. The logical address space is indicated by P (P is an integer of 1 or more) bits of address information, and software that can be executed by another predetermined data processing device including a first bus master and a second bus master, and the predetermined A data processing apparatus capable of executing any of the software that cannot be executed by another data processing apparatus,
The logical address space of the data processing apparatus is indicated by Q (Q is an integer greater than or equal to 2) bits, and the upper (QP) bits of the Q bit address information are “0”. Divided into a first address space shown and a second address space including all other spaces,
The data processing device includes:
A third bus master having the same function as the first bus master and capable of accessing only the first address space;
A fourth bus master having the same function as the second bus master and having an additional function capable of accessing both the first address space and the second address space;
Data processing comprising: a fifth bus master having a function different from that of the first bus master and the second bus master and having a function of accessing both the first address space and the second address space apparatus. A compatible processor that can run software that can run on previous generation processors,
A plurality of compatible bus masters compatible with each of the previous generation bus masters of the previous generation processor;
A compatible bus arbitrating means for arbitrating a request for bus use issued by the compatible bus master,
In any software that can be executed by the previous generation processor, the bus use request issued by the compatible bus master during the execution of the software in the compatible processor is executed by the execution of the software in the previous generation processor. A compatible processor that accepts a bus use request issued by the bus master in the same priority order. A processor having an arithmetic logic circuit for processing data and a physical control register for controlling a data processing operation;
A virtual register is defined by mapping this virtual register to an address in the processor's address space;
In the software configuration executable by the processor, the instruction to write a value to the virtual register address has a certain function,
The physical control register is mapped to an address in the processor address space, the physical control register address is different from the virtual register address, and the physical control register has a function equivalent to the certain function. In the hardware of the processor,
A processor wherein, when the instruction to write a value to an address of the virtual register is executed, a corresponding value is written to the physical control register. A compatible processor that can run software that can run on previous generation processors,
In the compatible processor, the bus use request is issued based on a plurality of factors, and is accepted based on a priority order among the plurality of factors.
Even in the previous generation processor, a bus use request issued by the previous generation processor is issued based on a plurality of factors, and is accepted based on a priority order among the plurality of factors. These multiple factors of the previous generation processor are a substantial subset of the multiple factors of the compatible processor with respect to bus usage requirements during execution of the software,
A compatible processor in which the priorities within the subset of factors of the compatible processor are the same as the priorities among the factors in the previous generation processor.