JP2001209609A - Microcomputer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer(MC) system capable of conducting the parallel processing of data transfer control between an MC and the external and arithmetic processing in the MC in parallel. SOLUTION: The MC is provided with a data transfer device 4 such as a DMAC for controlling data transfer on the external bus of the MC. The data transfer on the external bus by the device 4 and instruction execution using an internal bus by a data processor such as a CPU can be conducted in parallel. Namely the MC has a bus control means 12 for conducting bus right arbitration for a bus right request and bus control. The bus control means 12 can conduct the parallel processing of access operation only in the MC by using 1st inner buses IDB, IAB connected to a data processor and access operation in an external address space through the bus interface means by using the data transfer device 4 connected to a 2nd inner bus EXAB.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer system using a microcomputer having a data transfer device, and more particularly to a technique effective when applied to a microcomputer system for controlling a printer, a digital still camera, or the like. .

[0002]

2. Description of the Related Art As an example of a microcomputer, a central processing unit (CP) is described in "LSI Handbook" P540 and P541 issued by Ohmsha on November 30, 1984.
U), functional blocks such as a ROM (read only memory) for holding programs, a RAM (random access memory) for holding data, and an input / output circuit for inputting / outputting data are provided on a single semiconductor substrate. Are described.

[0003] As a microcomputer, a direct memory access controller (DMAC) is incorporated.
There are some which can transfer data independently of the PU. JP-A-5-307516 is an example of a document describing such a microcomputer.

Further, some microcomputers have an external bus right releasing function of releasing a bus right to the outside, and can operate an internal bus such as a ROM read by the CPU even while the external bus right is released. There is something. If a DMAC is connected to the external bus of such a microcomputer, the operation of the internal bus such as a ROM read by the CPU, the data transfer on the external bus by the external DMAC,
Can be performed in parallel. Japanese Patent Application Laid-Open No. Hei. 24-24854 discloses an example of a document in which the operation of the internal bus of the CPU and the operation of the external bus of the DMAC are performed in parallel. As an example of a document in which two DMACs operate in parallel, there is JP-A-1-187682.

[0005]

SUMMARY OF THE INVENTION The present inventor has proposed the above-mentioned DMA.
C built-in microcomputer and system using it,
Further, a system in which a DMAC is connected to the outside of the microcomputer having the external bus release function has been studied.

First, in a microcomputer with a built-in DMAC, the DMAC can be started by an interrupt request and can perform a repeat mode, a block transfer mode, and the like. In systems such as printers, D
The microcomputer with a built-in MAC is suitable for controlling a plurality of stepping motors, controlling print data of a printer, and storing received data in a memory.
C can have multiple data transfer channels.

However, the transfer control of the DMAC is based on the CP
Although independent of the operation of U, since the bus is shared, the bus cycle necessary for data transfer stops the operation of the CPU. For example, RAM by built-in DMAC
When data is transferred from the I / O circuit to the input / output circuit, if the access of the RAM is set to 2 states and the access of the input / output circuit is set to 3 states and one dead cycle state is included, the data transfer requires 6 states. During this period, the CPU cannot use the bus. Although not particularly limited, here, data processing LS such as a microcomputer
One cycle of the reference clock of I is defined as one state.

On the other hand, in a system in which a DMAC is connected to the outside of the microcomputer having the external bus release function, the operation of the internal bus such as the ROM read of the CPU and the data on the external bus by the external DMAC are controlled. The transfer can be performed in parallel.

However, when releasing the bus right, the external bus release must recognize an acknowledgment signal and a request signal with the outside at the time of transfer of the bus right, and at least an extra operation time is required for that. . In addition, in order to prevent the microcomputer and the bus of the external DMAC from colliding with each other, a time occurs in which both the buses do not use the bus, and overhead irrelevant to the actual operation is likely to occur. If overhead occurs before and after data transfer every time, it cannot be ignored compared to the actual data transfer time. Further, if a general-purpose DMAC is used for the DMAC outside the microcomputer, a function not to be used is generated, and it cannot be said that it is advantageous in terms of cost-effectiveness. That being said, D suitable for each system
If the MAC is individually developed, a microcomputer and another LSI must be newly developed, which is disadvantageous in terms of manufacturing cost and the like.

In a system such as a printer, for example, during printing, a stepping motor for driving the printer must be driven, and data processing unique to the system, such as processing of print data, must be performed. . It is also necessary to perform data reception asynchronously with the operation state of the printer. As other systems, digital devices such as digital video, DVD (Digital Video Disk), and digital TV need to perform signal processing such as decoding of digital signals and encoding of analog signals such as audio / video. In digital devices, it is necessary to input and output digital signals. Further, it may be necessary to drive a motor for driving a medium for recording a digital signal such as a tape or a disk. In order to increase the speed, performance, and accuracy of printers, digital videos, DVDs, digital TVs, and the like, it is necessary to improve the processing capability of microcomputers.

As described above, the present inventor has incorporated a data transfer device such as a DMAC into a microcomputer,
Then, I found the importance of the viewpoint of improving the total performance of the processing by the microcomputer.

In view of this, the present inventor has provided a data transfer device such as a direct memory access controller for controlling data transfer on an external bus of a microcomputer. Application for an invention relating to a microcomputer employing a bus control means for enabling data transfer on an external bus and instruction execution using an internal bus by a data processing device such as a CPU in parallel (Japanese Patent Application No. 11-36949). )did. The data transfer device is intended to be used exclusively for data transfer control outside the microcomputer.
Further, in the dual address transfer by the data transfer device, the data read from the external source address is temporarily held by a latch circuit such as an input / output port which constitutes a bus interface unit with the outside. Thereby, in data transfer between the external source location and the external destination location, the data can be transferred from the source location to the destination location without leading the transfer data to the data transfer device inside the microcomputer. . This allows
This eliminates the need for a data bus for guiding the data being transferred to the data transfer device, thereby contributing to a reduction in the physical scale of the microcomputer.

The present inventor further proposes that in data transfer on the external data bus, prior to actual data transfer,
A case in which transfer control information indicating data transfer contents such as a packet command is transferred has been studied. The transfer control information may include information necessary for transfer control such as the number of words to be transferred.

In view of this, the present inventor has proposed a microcomputer provided with a buffer device for transferring such transfer control information to a data processing device of the microcomputer, in addition to the data transfer device and the bus control means provided in the microcomputer. Application for invention related to computer (Japanese Patent Application No. 11-23)
9514).

Such transfer control information is immediately analyzed by a data processing device such as a CPU, and it is necessary to set data transfer in the data transfer device or the like in accordance with the specified data transfer contents. For this reason, it is not advisable to store the transfer control information together with the data in an external RAM (buffer memory). When the external memory reads from the CPU, the internal memory and internal I / O
Compared with the O-register and the like, the access is not fast and the bus width of the external bus cannot always be maximized with respect to the bus width of the CPU. In addition, when data transfer is being performed on another data transfer channel of the data transfer device, data transfer on the external bus competes, and the processing speed for transfer control information may be reduced. Further, it is not preferable from the viewpoint of memory management that data and transfer control information are mixed. Even when the CPU attempts to read the transfer control information, special processing is required for confirmation, such as at which address the transfer control information exists or by referring to the address register of the data transfer device.

An object of the present invention is to provide a microcomputer system capable of improving the total performance of data processing by a microcomputer including a data transfer device such as a DMAC.

Another object of the present invention is to enable transfer control information such as packet command analyzed by a data processing device or the like to indicate data transfer contents to the data processing device efficiently. It is another object of the present invention to provide a microcomputer capable of minimizing an increase in circuit scale for that purpose, and a microcomputer system using such a microcomputer.

Still another object of the present invention is to minimize an increase in physical and logical scales and to perform parallel processing of data transfer control on an external bus of a microcomputer and CPU operations such as internal bus access by a built-in CPU. It is to provide a microcomputer system that can be enabled.

Another object of the present invention is to control data transfer between a microcomputer and the outside and to perform arithmetic processing inside the microcomputer in parallel,
Further, it is an object of the present invention to provide a microcomputer system which has a small processing overhead and can minimize an increase in physical scale.

Another object of the present invention is to mount a microcomputer capable of processing data transfer between a device equipped with a microcomputer and another device and arithmetic processing inside the device in parallel. To provide equipment.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0022]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[1] A data transfer device (4) such as a direct memory access controller for controlling data transfer on an external bus of a microcomputer is provided. In the microcomputer, the data transfer on the external bus by the data transfer device and the instruction execution on the internal bus by the data processing device such as a CPU can be operated in parallel, thereby improving the processing performance of the microcomputer. Can be improved. In other words, data transfer on the external bus can be performed without lowering the processing performance of the CPU. More specifically, the microcomputer further has a bus control means (12) for performing bus right arbitration and bus control for a bus right request, wherein the bus control means includes a first internal bus (IDB, IDB, I
AB), the operation of accessing only the inside of the microcomputer and the operation of accessing the external address space via the bus interface means by the data transfer device connected to the second internal bus (EXAB) can be performed in parallel. is there.

Since the data transfer on the external bus by the data transfer device and the instruction execution using the internal bus by the data processing device such as a CPU can operate in parallel, the processing performance of the microcomputer can be improved. Data transfer on an external bus can be performed without lowering the processing performance of the data processing device.

The bus control means may be constituted by an internal bus controller and an external bus controller. The external bus controller divides the address space so that bus specifications such as a memory type, a bus width, and the number of access states can be set, and at least a request for an external bus right by a bus master such as a data processing device such as a CPU is made. The present invention can be configured to arbitrate between an external bus request from the data transfer device and a bus right request from outside the microcomputer. Thereby, first, control of internal access by the data processing device using the first internal bus in parallel with external bus access by the data transfer device, and second, control of the first internal bus by the data processing device. The arbitration control between the used external bus access and the external bus access by the first data transfer device can be easily realized by individual logic, simplifying the control logic or control method, and suppressing the increase in the control logic scale. Can be easily balanced.

At this time, if the address or the like output from the data transfer device is supplied to the bus interface means via a dedicated signal line such as a second internal bus (EXAB),
The state transition control operation of the data transfer device can be simplified,
It can contribute to the reduction of the logical scale.

Further, the external bus controller arbitrates the external bus request including the external bus request from the outside of the microcomputer together with the external bus request by the data transfer device built in the microcomputer.
It is possible to reduce the overhead when transferring the right of the external bus between the data processing device and the data transfer device, and further improve the processing performance.

A storage means (5) such as a ROM for storing a program of a data processing device such as a CPU is provided by a CPU.
It can be made selectable in an operation mode or the like so as not to include the vector of the data processing device as described above. As a result, the entire processing program can be stored in an external ROM, and a program that requires high-speed processing can be stored in a built-in ROM, so that usability such as flexibility in changing the program can be improved.

The activation factors and the transfer mode of the data transfer device can be limited to only the functions necessary for data transfer on the external bus. Thereby, the physical scale can be reduced.

In the dual address transfer, the data read from the source address is temporarily held by a latch circuit (72L) such as an input / output port constituting the bus interface means (72), so that the data is stored in the bus. The data bus leading to the data transfer device becomes unnecessary, and the physical scale can be reduced.

If the data transfer device also supports single address transfer, the bus cycle required for transfer can be shortened and the processing performance can be further improved.

[0032] The data transfer device can have a plurality of data transfer channels. At this time, an external data transfer activation request signal can be assigned to each channel. Thereby, usability of data transfer control in the microcomputer system is improved, and processing performance can be improved.

In addition to a data processing device such as a CPU and the data transfer device, a general-purpose DMA which can support data transfer control inside and outside the microcomputer connected to an internal bus for a conventional microcomputer
A second data transfer device (3) such as C can also be incorporated. As a result, data transfer specialized for data transfer control on the external data bus is compared with a case where a necessary number of data transfer channels are secured by a general-purpose DMAC for DMA transfer control inside and outside the microcomputer. Since the device has a configuration specialized for data transfer control relating to an external bus, an increase in logical scale can be minimized even if the device has a necessary number of data transfer channels as a whole.

When the bus control means also enables refresh control of a DRAM or the like, the refresh timer may perform bus arbitration as an external bus request source.

By configuring the second data transfer device connected to the first internal bus and the data transfer device specialized for data transfer control on the external bus as an integrated module, limited data transfer is possible. The transfer channels can be used interchangeably.

[2] In the microcomputer, a plurality of buffer register means (EXDiDRm) are provided in the bus interface means (72) used for external access by the data transfer device. The data transfer device includes a memory designating unit (40,
41, 72C), in addition to the memory designating means, a buffer designating means (48) capable of designating the buffer register means, and a mode designating means capable of designating an operation mode of data transfer. The transfer control means performs data transfer control based on the state of the means and the buffer designating means.

The mode designating means determines whether one of a data transfer source and a destination is designated by the buffer designating means or both locations are designated by the memory designating means. A first information field is provided.

In data transfer on an external bus, the buffer register means can be used as one of the source and destination address locations. In specifying the buffer register means, means for specifying another memory device such as an address or an acknowledge signal, that is, without using the memory specifying means, for example, by using a buffer specifying means such as a transfer count register, a plurality of buffer register means are used. Specifies the required buffer register means from. The buffer register means performs input / output with an external bus during data transfer of the data transfer device. A data processing device (2) such as a CPU can read / write the buffer register means via an internal bus.

According to the above, when transfer control information such as a packet command is transferred on an external bus prior to actual data transfer, the transfer control information is
The buffer register means can be used. The buffer register means can be specified without depending on an address or an acknowledge signal, does not require a bus cycle,
Data transfer such as reception of transfer control information can be speeded up. A data processing device such as a CPU can read the data via an internal bus without using an external bus, and can speed up the process of reading the transfer control information. Since information can be stored in a predetermined buffer register by the buffer designating means, there is no need for a data processing device such as a CPU to determine the location address of a packet command or the like. With these, processing such as analysis of transfer control information by the data processing device can be accelerated,
According to the analysis result, the data processing device can streamline the process of resetting the data transfer control conditions for the data transfer device, for example, the process of determining the number of data transfer words and changing the location of the destination data from the buffer register to the memory. Switching to the data transfer operation reflecting the transfer control information can be streamlined.

The transfer count register (48) may be used as the buffer designating means. For example, in that case,
When the first information field selects that the one location is specified by the buffer specifying means, all or a part of the transfer count register is also used for specifying the buffer register means. When the first information field selects that both of the locations are designated by the memory designating means, the transfer count register is assigned an original function of counting the number of transfer data.

The original function of the transfer count register, that is, counting of the number of transfer data, is realized through arithmetic operation means which inputs the value of the transfer count register and returns an operation result to the transfer count register. This arithmetic operation means is also used for an operation for incrementing a value of an address register as a memory designating means.

When the first information field selects that the one location is designated by the buffer designating means (MD2 = 1),
A second information field (MD1) for determining whether designation of the other location for performing data transfer with the buffer register means is used in dual addressing mode or single addressing mode;
A third information field (MD0) for determining whether to use the buffer register means as a source location or a destination location
And may further include

The mode designating means further comprises a fourth information field (RPE) and a fifth information field (RPB0).
To RPB2). They enable an operation that facilitates repetitive sequential designation of a source location and a destination location.

In the fourth information field, when the first information field selects that the one location is designated by the buffer designating means, a part of the area (TCRL) of the transfer count register is assigned to the fourth information field. When the value returned from the arithmetic operation means reaches a predetermined value in a partial area of the transfer count register, the value of the remaining area (TCRH) of the transfer count register is used as a buffer designating means. This is an area for storing information for instructing the transfer control means (45) to transfer to an area. By specifying this operation, data transfer control can be continuously performed while repeatedly specifying a plurality of buffer register means in a predetermined order, and control for that can be simplified. That is, the number of times the data processing means sets the transfer conditions for the data transfer device can be greatly reduced, and the burden on the data processing device can be reduced.

[0045] The fifth information field is used for storing the information input from the address register to the arithmetic operation means when the first information field has selected to specify both of the locations by the memory specifying means. An information area for instructing the transfer control means to perform an arithmetic operation on condition that the logical value of a bit higher than the predetermined bit position is fixed, and to return the operation result to the address register. When the operation is specified by the fifth information area, the value of the address specifying means such as the address register is repeatedly updated in order, so that the buffer memory such as the external RAM can be used as a ring buffer. In particular, the iterative address updating operation for use as the ring buffer is such that when the address information of the addressing means is incremented / decremented by the arithmetic operation means, bits higher than a predetermined bit are not changed, in other words, Carry / borrow propagation is suppressed at the bit boundary. Therefore, the function as a ring buffer can be realized with a minimum physical scale. Even if the start address and end address of the ring buffer cannot be completely arbitrarily specified, there is no major inconvenience when a large-capacity memory such as an external RAM is used for the ring buffer. Since the repetitive operation can be performed in the above-described format, a load such as an interrupt process for a data processing device such as a CPU can be reduced.

[3] A data processing system or a microcomputer system to which the microcomputer including the data transfer device and the bus control means is applied,
An external bus is connected to the bus interface means of the microcomputer, and a RAM is connected to the external bus.

Further, a data communication circuit connected to the external bus may be provided. The data communication circuit supplies an external data transfer activation request signal to the data transfer device of the microcomputer. When the bus right is approved by the bus control means, the data transfer device instructs the data communication circuit to perform the transfer by using an external data transfer approval signal or a predetermined address and a read signal or a write signal.

In the microcomputer system, when the first information field has selected to specify both of the locations by the memory specifying means, the data transfer device may connect the data communication circuit with the RAM. The data transfer between them can be controlled in a single addressing mode. At this time, transfer is instructed to the data communication circuit by the external data transfer acknowledge signal, and access is instructed to the RAM by an access address signal.

[0049] In the microcomputer system, the data transfer device may be configured to control the data communication circuit and the buffer register means when the first information field selects the one location by the buffer designating means. Can be controlled in a single addressing mode. At this time, the data transfer apparatus instructs the data communication circuit to transfer transfer control information such as a packet command by the external data transfer acknowledgment signal as a source location of the data transfer, and The designation of the buffer register means is given by the buffer designation means.

The data processing device changes the transfer condition of the data transfer device according to the result of reading and analyzing control information such as a packet command transferred to the buffer register means. The data transfer device whose transfer condition has been changed is selected by the first information field to specify both of the locations by the memory specifying means, and the data communication circuit and the RAM
The data transfer to and from the data communication circuit can be controlled in a single addressing mode. The external data transfer acknowledge signal instructs the data communication circuit to transfer data information following the packet command. Give the specified access address.

Thus, when transfer control information such as a packet command is transferred prior to the actual transfer of data information, the transfer control information is not stored in the external RAM (buffer memory) but is stored in the buffer register means of the microcomputer. A data processing device such as a CPU can immediately proceed to the analysis of the transfer control information without activating an external bus cycle, and can follow the data transfer contents indicated by the transfer control information. The data transfer can be quickly set in a data transfer device or the like, and transfer to data information can be started. Since only the net data is stored in the external RAM, the processing of such data can be facilitated.

As a transfer protocol based on the data transfer information, for example, IEEE1394 or USB (Universal)
sal Serial Bus).

It is also possible to form the microcomputer system as a whole or on a single semiconductor chip excluding the external RAM and to integrate the semiconductor.

[0054]

FIG. 1 is a block diagram showing an example of a microcomputer according to the present invention. The microcomputer 1 shown in FIG.
The semiconductor integrated circuit is formed on a single semiconductor substrate (one chip).

The microcomputer 1 includes a central processing unit (CPU) 2, a DMA controller (DMAC) 3 as a second data transfer device capable of controlling data transfer to and from the microcomputer, and an external device to the microcomputer. External bus DMAC as first data transfer device specialized for data transfer control on bus
(EXDMAC) 4, read only memory (ROM)
5, random access memory (RAM) 6, timer 7,
Pulse output circuit 8, serial communication interface (SCI) 9, A / D converter (A / D) 10,
Interrupt controller 11, bus controller 12 as a bus control means, clock oscillator (CPG) 13, input / output port (IOP (A)) 21 to input / output port (IO
P (F)) 26 and input / output port (IOP (1)) 3
1 to functional blocks (also referred to as modules) of input / output ports (IOP (5)) 35.

The main part of the operation is the CPU 2, which mainly operates by reading instructions from the ROM 5. Although not particularly shown, the CPU 2 fetches an instruction, decodes the fetched instruction to generate a control signal for each unit, and performs an address operation, a data operation, and the like according to a control signal from the instruction control unit. And an operation execution unit for executing the instruction.

The DMAC 3 is connected to the CPU 2 and the bus IAB,
The IDB can be shared, and data transfer control can be performed instead of the CPU 2. DMAC3 is a microcomputer 1
For both inside and outside of, instead of CPU2,
This is a circuit module capable of performing data transfer control.

The EXDMAC 4 exclusively controls data transfer on an external bus, and can control data transfer to the outside in parallel with the operation of the CPU 2 or DMAC 3 on the internal bus. This EXDMAC4 is
Only data transfer control to the outside of the microcomputer 1 is enabled. That is, the EXDMAC 4 enables data transfer control between memories provided outside the microcomputer 1 in the dual addressing mode,
Further, control of data transfer between an external memory of the microcomputer 1 and an external input / output circuit of the microcomputer 1 is enabled in a single addressing mode or a dual addressing mode. Whether to use the single addressing mode or the dual addressing mode depends on whether the external input / output circuit is enabled to input / output by an acknowledge signal.

The details of the EXDMAC 4 will be described later.
Here, the outline will be described. The CPU 2 sets the data transfer control conditions for the EXDMAC 4 via the bus controller 12 and the buses PDB and PAB. EXD
The MAC 4 is exclusively arbitrated with an external access request from a bus master module such as the CPU 2 or the DMAC 3 to acquire an external bus right. An address signal for external data transfer control by the EXDMAC 4 can be output from the IOP (A) 21 to the IOP (C) 23 to the outside via the bus EXAB. At this time, in the data transfer in the dual addressing mode by the EXDMAC 4, the transfer data is not taken into the EXDMAC 4,
It is temporarily stored in a latch circuit inside P (D) 24 and IOP (E) 25. Also, IOP
(D) 24 and IOP (E) 25 are provided with buffer registers.
Can be specified as either a source or a destination location when controlling data transfer on an external bus.

The functional blocks of the microcomputer 1 will be described in more detail. The microcomputer 1
Are interconnected by an internal bus. The internal bus has a control bus (not shown) in addition to the address bus and the data bus. The control bus includes a bus right request signal, a bus acknowledge signal,
It includes a bus command, an external bus command, a ready signal, an external bus ready signal, a read signal / write signal, a bus size signal, and a system clock. IAB, PAB,
EXAB is an internal address bus, and IDB and PDB are internal data buses. These buses are connected to a bus controller 12. The internal buses IAB and IDB are connected to the CPU 2, the DMAC 3, the ROM 5, the RAM 6, and the bus controller 12, and further have an internal address bus IA.
B is IOP (A) 21 to IO for external address output
The internal data bus IDB is connected to the IOP (D) 24 and the IOP (E) for inputting / outputting external data.
25.

The internal buses PAB and PDB include a bus controller 12, an EXDMAC 4, a timer 7, a pulse output circuit 8, an SCI 9, an A / D converter 10, an interrupt controller 11, IOP (A) 21 to IOP (F) 26, It is connected to IOP (1) 31 to IOP (5) 35.

The internal address bus EXAB is EXDMA
C4 and bus controller 12, IOP (A) 21 to IO
Connect to P (C) 23.

The bus controller 12 refers to an address signal to determine an access destination and select an operation according to the bus specifications. Therefore, the bus controller 12
It is only necessary to input upper address bits for determining the area from the address bus. Address output for external data transfer control by the EXDMAC 4 is performed via an address bus EXAB.

The bus controller 12 has an internal bus controller 120, an external bus controller 121, a refresh timer 122 and the like. The address output to the outside of the microcomputer 1 is IOP (A) 21 to
This is performed via the IOP (C) 23. Data input / output to / from the microcomputer 1 is performed by IOP (D) 24, IOP
This is performed via OP (E) 25.

The CPU 2 and the DMAC 3 can use the internal bus as internal bus masters. The internal bus arbiter (internal bus arbitration circuit) of the internal bus controller 120 included in the bus controller 12 according to each bus right request signal. Arbitrates for bus rights. Also,
The external controller includes an external bus access signal included in the bus controller 12 according to an external bus access signal from the CPU 2 or the DMAC 3, an EXDMAC 4, a bus right release request from the outside of the microcomputer, and a refresh request from the refresh timer 122. An external bus arbiter (external bus arbitration circuit) of the bus controller 121 arbitrates.

ROM 5, RAM 6, timer 7, pulse output circuit 8, SCI 9, A / D converter 10, IOP
(A) 21 to IOP (F) 26 and IOP (1) 31
The IOP (5) 35, each functional block of the interrupt controller 11, and the EXDMAC 4 are read / written by the CPU 2 or the DMAC 3 as internal bus slaves. The case where the EXDMAC 4 is accessed as a bus slave is a case where data transfer conditions and the like are set by the CPU 2 or the like.

The interrupt controller 11 has a timer 7,
An interrupt signal output from the SCI 9, the A / D converter 10, and the input / output port is input, an interrupt request signal is output to the CPU 2, and a start request signal is output to the DMAC 3. Also, DM
A clear signal output from AC3 is input, and an interrupt clear signal is output. These interrupt signals and the like are not shown.

The input / output ports 21-26, 31-36
Are also used for input / output of external bus signals and input / output signals of input / output circuits. The IOP (A) 21 to IOP
(C) 23 is an address bus output, IOP (D) 24, I
OP (E) 25 is a data bus input / output, IOP (F) 26
Is also used as a bus control signal input / output. The external address bus and the external data bus are respectively connected to buses IAB, ID via buffer circuits included in these input / output ports.
B, EXAB. The buses PAB and PDB are used to read / write the register of the input / output port, and have no direct relation to the external bus. The bus control signal output includes an address strobe, a high / low data strobe, a read strobe, a write strobe, a bus acknowledge signal, and the like. The bus control input signal includes a wait signal, a bus request (bus right release request) signal, and the like. These input / output signals are not shown. The extension of the external bus is selected depending on the operation mode and the like, and the functions of these input / output ports are also selected.

The IOP (1) 31 is a timer input / output,
IOP (2) 32 outputs a pulse, and IOP (3) 33 outputs S
CI input / output, IOP (4) 34 is analog input, IOP
(5) 35 is also used for input / output of transfer request signals EXDREQ0 to EXDREQ3 and transfer acknowledge signals EXDACK0 to EXDACK3 for EXDMAC4 and DMAC3. EXDMAC 4, DMAC 3, Timer 7, SCI 9, Pulse output 8, A / D converter 10 and I
Input / output signals to / from the OP (1) 31 to the IOP (5) 35 and internal interrupt request signals are not shown.

In addition, power supply terminals Vcc and Vss, analog power supply terminals AVcc and AVss, reset input RE
S, standby input STBY, interrupt input NMI, clock input EXTAL, XTAL, operation mode input MD
There are input terminals such as 0, MD1, and MD2.

FIG. 2 exemplifies an address map of a predetermined operation mode of the microcomputer 1. The address space is not particularly limited, but is 16 Mbytes,
An address is assigned for each byte.

Each functional block has a unique address in the address space of the CPU 2 irrespective of the bus to be connected. The I / O (data input / output means) includes the timer 7, DMAC 3, EXDMAC 4, pulse output circuit 8, SCI 9, A / D converter 10, IOP (A) 21 to
IOP (F) 26, IOP (1) 31 to IOP (5) 3
5, and respective internal I / O registers of the interrupt controller.

Although the ROM 5 is not particularly limited,
32 kbytes, and addresses H'200000 to H '
207FFF, RAM 6 is 1 kbyte, and addresses H'FFF800 to H'FFFBFF
And the I / O is at address H'FFFE00
~ H'FFFFFF. In addition,
H 'indicates a hexadecimal number.

The I / O includes a data register (also referred to as a buffer register) EXDiD which is an example of a buffer register used for data transfer by the EXDMAC 4.
Rm is included. i indicates the channel number of the data transfer channel, and m indicates the register number. Actually, these data registers EXDiDRm are arranged at different addresses from each other, and as described later, EXDiDRm
Read / write is enabled in an arbitrary order by a selection signal output from the DMAC 4 or the CPU 2. This data register EXDiDRm stores EXDMA
In the data transfer control on the external bus by C4, it can be specified as one of the source and destination locations.

The other address areas are external address spaces. Since the vector of the CPU 2 exists at the head of the address space, it is necessary to externally connect a ROM for storing the program including this part.

A ROM for storing programs, a DRAM for data, and other circuits (ASIC) are connected to the external address space as needed. The external address space is divided into eight areas 0 to 7 in units of 2 MB, bus specifications can be set, and an area selection signal can be output. Different memories can be easily connected to each area. In areas 2 to 5, an address multiplex for accessing the DRAM and a DRAM interface capable of executing the high-speed page mode can be selected. Such bus control is described in “H8S / 2655 Series Hardware Manual” issued by Hitachi, Ltd. in March 1995.

The built-in ROM 5 can easily access the external ROM at high speed. As long as the contents of the internal ROM 5 are read out by the internal CPU 2 or DMAC 3,
It is not output to the outside. R as internal function module
The bus controller 12 responds to the access of the address mapped to the OM5 by the data input / output IOP (D).
This is because the IOP (EOP) 24 and the IOP (E) 25 are kept inoperable.

When the built-in ROM 5 is a mask ROM, a change in the contents means a change in the entire microcomputer 1 and is difficult to change. on the other hand,
When the built-in ROM 5 is an electrically writable ROM such as a flash memory, the cost tends to increase undesirably, for example, the manufacturing process becomes complicated. On the other hand, external ROM
Is difficult to access at a high speed, but the contents are changed only in the external ROM, and the external ROM is a general-purpose one, so that it is often inexpensive. If the program is changed, the size of the program changes, so that the CPU vector often changes. According to the address map of FIG. 2, a program that requires high-speed processing and is unlikely to need to be changed or a program whose contents are not desired to be known to a third party are stored in the built-in ROM 5,
By storing the entire processing including the CPU vector in the external ROM, it is possible to improve processing performance, improve usability, reduce costs, and the like.

If the address of the built-in ROM 5 can be changed to the area 0 so as to include the CPU vector depending on the operation mode, a microcomputer system can be constructed without the need for an external program storage ROM. .

FIG. 3 shows the bus structure of the microcomputer 1 in more detail. Bus controller 1
2 includes an internal bus controller (I-BSC) 120, an external bus controller (EX-BSC) 121, and a refresh timer 122. The I / O 70 has a timer 7, a pulse output circuit 8, an SCI 9, an A / D
Converter 10, IOP (A) 21 to IOP (F) 26, I
OP (1) 31 to IOP (5) 35, and internal I / O registers in each of the interrupt controllers 11 are included. The memory 71 means the ROM 5 and the RAM 6. CPG1
Functional blocks or circuit modules not connected to the bus, such as 3, are not shown.

The external bus buffer circuit (BUF) 72
The IOP (A) 21 to IOP (F) 26, IOP
(5) An address buffer and a data buffer included in 35. The respective IOP (D) 24, IOP
(E) 25 is provided with a latch circuit for the data bus. This latch circuit is represented by a circuit block indicated by reference numeral 72L. In addition, an external bus buffer circuit (BU)
F) 72 is provided with a data register EXDiDRm as a buffer register.

The internal buses IDB and IAB are connected to the CPU 2
And a bus directly connected to the DMAC3. RAM6
The memory 71 is also connected to the buses IDB and IAB for high-speed access to internal memories such as the ROM and the ROM 5. Access to the memory 71 is performed in one state.

The internal buses PAB and PDB have the I bus
A register of a functional block represented by / O70 is connected. By separating the buses IAB and IDB from the buses PAB and PDB, the load (capacitive load) of the buses IAB and IDB mainly used is reduced by the program read of the CPU 2 and the speed is increased. By maintaining the state of the buses PAB and PDB, power consumption can be reduced. The CPU 2 and the DMAC 3, which are other internal bus masters, use the buses PAB, PDB
When accessing a register of a functional block represented by the I / O 70 connected to the I / O 70, the buses IAB, IAB
This is performed via the DB and the bus controller 12. Said I
Access to the register of the functional block represented by / O70 is performed in two states.

The CPU 2 or DMAC 3 is connected to the external bus EA
When accessing an external memory (not shown) connected to the BUS or EDBUS, the access is performed via the buses IAB and IDB and the external bus buffer (BUF) 72.

The CPU 2 and the DMAC 3 exclusively use the buses IAB and IDB. For this, CPU
2 and the DMAC 3 output a bus right request signal, and the arbitration circuit 120A of the internal bus controller 120 determines this and gives the bus right to either the CPU 2 or the DMAC 3. The CPU 2 or the DMAC 3 confirms that the bus right has been granted, outputs an address signal to the bus IAB, and outputs a bus command to a control bus (not shown). The bus command is, for example, a control code for instructing read, write, access data size (byte, word, longword) and the like.

The internal bus controller 120 controls the bus IA
After confirming the contents of B, if the access is to the memory 71, access control using the buses IAB and IDB is performed. Further, the internal bus controller 120 has an internal I / O
For access to register 70, buses PAB and PD
B controls the register access of the I / O 70.

The external buses EDBUS and EABUS are controlled by the external bus controller 121. The external bus controller 121 also performs address multiplex control and the like when an external DRAM is connected, for example. The bus masters that can use the external bus are CPU2, DMAC3, E
An XDMAC 4, a refresh timer 122, and an external bus master not shown. The arbitration circuit 121A performs arbitration of the bus right for them. CPU2 and DM
The internal bus master such as the AC3 once arbitrates the bus right in the internal bus controller 120, and when the bus right is given, the internal bus controller 120 sends the external bus right to the external bus controller 121 by the external bus right request signal EXBREQ1. Request. In other words, as long as the internal bus masters CPU2 and DMAC3 are using the internal bus, no external bus request is issued from the internal bus master for external access. Therefore, even when the internal bus is being used by the internal bus masters CPU2 and DMAC3, the external bus controller 121 performs the refresh operation by the refresh timer 122 and the EXDMA
The transfer on the external bus by C4 or the external bus right release request from outside the microcomputer 1 can be processed in parallel. Note that the external bus controller 121
When granting the bus right in response to the bus right request by the bus right request signal EXBREQ1, the external bus right acknowledge signal E
XBACK1 is returned to the internal bus controller 120.

The refresh timer 122 generates a refresh request to the external bus controller 121 by a refresh request signal RFREQ at regular intervals.
This refresh request is also one of the external bus right requests. When the refresh timer 122 acquires the external bus right, the external bus controller 121 performs, for example, CAS-before-RAS refresh control as refresh control of the DRAM.

When the external bus request is issued to the external bus controller 121 by the external bus request signal EXBREQ3 from the outside of the microcomputer 1, the external bus controller 1
Reference numeral 21 sets the external address output, external data input / output, and external access control signal input / output of the IOP (A) 21 to IOP (F) 26 to a high impedance state, and enables the external bus master to use the external bus. , Activates the external bus right acknowledge signal EXBACK3, and notifies this to the external bus right request source.

The EXDMAC 4 is connected to the buses PAB and PDB, and is read / written by an internal bus master such as the CPU 2 or the DMAC 3 for initial setting of transfer control conditions and the like. EXDMAC 4 is a DMA transfer request signal EXDREQi (i = 0-3) provided from the outside.
Thus, the DMA transfer control operation is started.

When a DMA transfer request is issued in this way,
The EXDMAC 4 requests the external bus controller 121 for an external bus right by using an external bus right request signal EXBREQ2. When the external bus controller 121 grants the bus right to the external bus request, the bus controller 1
Reference numeral 21 denotes an external bus acknowledge signal E to the EXDMAC 4.
Assert XBACK2. The EXDMAC 4 outputs a bus command BCMD to the external bus controller 121, and further issues an external access address signal via the address bus EXAB. External bus controller 121
Performs bus control for data transfer control on the external bus via the bus buffer 72 in accordance with the bus command BCMD and the address signal from the EXDMAC 4.

The external bus buffers of IOP (D) 24 to IOP (E) 25 include the latch circuit 72L.
During the dual address transfer control of the EXDMAC 4, the transfer data is temporarily held in accordance with an instruction from the external bus controller 121. Also, IOP (D) 24 to IOP (E)
The external bus buffer 25 has a data acknowledge signal EXDACKi for designating an input / output circuit as an acknowledged device during single address transfer.
(I = 0 to 3) is output to an input / output circuit which is a data transfer destination or a data transfer source. Data acknowledge signal E
XDACKi (i = 0 to 3) is a signal for each data transfer channel of EXDMAC4. The data acknowledge signal EXDACKi (i = 0 to 3) is output to the outside by the external bus controller 121 receiving the bus command BCMD from the EXDMAC 4 and controlling the control signal output circuit 72C with the control signal 73 in accordance with the command. The control signal output circuit 72C outputs the data acknowledge signal E
This is an example of designating means for designating an acknowledged device by XDACKi (i = 0 to 3).

The data register EXDiDRm stores E
In a predetermined data transfer mode on the external bus by the XDMAC 4, it can be designated as either the source or the destination location of the data transfer.

It is to be noted that the EXDMAC 4 and the external bus controller 121 can be configured as a single unit.

FIG. 4 shows an example of an address decode circuit included in internal bus controller 120. The address decode circuit 120D decodes an address signal output from the CPU 2 or the DMAC 3 to the internal bus IAB,
5, RAM 6, I / O, address determination of external space. The signal MSROM is a module select signal of the ROM 5, the MSRAM is a module select signal of the RAM 6,
MSIO is an I / O module select signal, EXTA
Is a module select signal in the external space of the microcomputer 1.

As described above, the ROM 5 can be arranged in either the area 0 or the area 1 shown in FIG. 2 depending on the operation mode of the microcomputer 1. Depending on the operation mode or the designation of the internal I / O register, the signal R
By setting the OME to “0”, the ROM 5 can not be used.

When I / O is selected (MSIO = 1)
When the bus access using the buses PAB and PDB is activated and the external device is selected (EXTA = 1), this signal is supplied to the external bus controller 121 as the external bus right request signal EXBREQ1.

FIG. 5 illustrates a register configuration of the EXDMAC4. The EXDMAC 4 has, for example, four channels and each has a corresponding external request EXDRE.
It is activated by Qi (i = 0 to 3) and performs single address transfer and dual address transfer. FIG. 5 illustrates a register configuration for one channel.

The registers of the EXDMAC 4 include a 24-bit source address register (SAR) 40, a destination address register (DAR) 41, a transfer count register (TCR) 48, and a 16-bit mode register (DTMR) 42. Become.

Further, the EXDMAC 4 stores the 16-byte data registers EXDiDR0 to EXDiDR1.
Use 5. For transfer data of word size,
The data registers EXDiDR0 to EXDiDR15
Are used in combination as two units. For example, EXD
When iDR0 and EXDiDR1 are combined, E
XDiDR1 is higher (bits 15 to 8), ERDiDR
0 is the lower order (bits 7 to 0). These EXDi
DR0 to EXDiDR15 are considered to be included in the external bus buffer circuit (BUF) 72 of FIG.
(D) 24 and IOP (E) 25.

EXDMAC 4 is the data register EXDi
When data transfer control is performed without using DR0 to EXDiDR15, the TCR 48 functions as a register for setting the number of transfer data. TCR48 is EXDM
AC4 is the data register EXDiDR0 to EXDiDR
15 is designated as either the source or the destination, and the data transfer is controlled, the data registers EXDiDR0 to EXDiDR
It also functions as a buffer designating means for designating the number 15. Although the details will be described later, at this time, the TCR 48 stores the upper bits 15 to 8 according to the setting state of the mode register.
(TCRH) and lower bits 7-0 (TCRL) are available independently.

The SAR 40 and the DAR 41 are address registers as 24-bit address designating means, and can designate the entire address space of 16 Mbytes.
When data transfer control is performed by designating the data registers EXDiDR0 to EXDiDR15 to one of the source and destination locations, and when the other location is designated by a memory address, the other location must be designated. The SAR4
0 or DAR41.

The function of each bit of the DTMR 42 is as follows. Bit 15 is an EDTE bit, which permits the operation of the EXDMAC 4 of the channel. When there is a transfer request by EXDREQi in a state where the EDTE bit is set to "1", data transfer control of the channel is enabled.

Bit 14 is a DRQS bit,
Defines the active state of the XDREQi signal. The DRQS
Bits make the input selection. When cleared to "0", low level sensing is selected, and when set to "1", falling edge sensing is selected.

Bit 13 is an EDE flag, which is set to "1" when data transfer of a predetermined number of times by the transfer channel is completed, that is, when the value of TCR 48 becomes 0.

Bit 12 is an EDIE bit, and is a bit for determining whether or not to permit an interrupt. EDI
When both the E bit and the EDE flag are set to “1”, an interrupt is requested to the CPU 2. When the EDE flag is set to "1" while the EDIE bit is set to "1", the EDTE bit is simultaneously cleared to "0", and the operation of the channel is interrupted.
Wait for processing by CPU2.

The EXDMAC 4 can use a memory to be transferred as a ring buffer.
That is, when the ring buffer is used, the transfer destination or transfer source address is automatically restored to the initial value (changes of upper bits beyond a predetermined bit are suppressed). No processing by the CPU 2 is required. If the EDIE bit is cleared to "0", the memory can be used as a ring buffer.

Bit 11 is an RPE bit, which is valid when MD2 = 1, which will be described later, and specifies a repeat operation.
When RPE = 1, bits 7-0 (TCRL) of the transfer count register TCR function as a count register. When bits 7-0 (TCRL) become H'00, the contents of bits 15-8 (TCRH) are changed to bits 7-0 (TCC).
RL). At this time, the EDE bit is “1”
Are not set, and the operation is repeated.

Bits 10 to 8 are RPB2 to RPB0 bits, which are valid when MD2 = 0, which will be described later, and specify the size of the ring buffer, ie, the unit of repeat.
The repeat unit is 64 kB (RPB2 to RPB0 =
B'000), 128 kB (RPB2 to RPB0 = B '
001), 256 kB (RPB2 to RPB0 = B'01
0), 512 kB (RPB2 to RPB0 = B'01
1) 1 MB (RPB2 to RPB0 = B'100), 2
MB (RPB2 to RPB0 = B'101).

When the values of the SAR 40 and the DAR 41 are incremented and updated by the address calculator 43 in accordance with the progress of the data transfer control, the RPB2 to RPB0 bits are transmitted to the address calculator 43 in accordance with the values.
Bits 15, 16, 17, 1 of AR40 and DAR41
The transmission of carry / borrow to bit positions corresponding to bits 8, 19 and 20 is prohibited. When the carry / borrow transmission is prohibited, the value of the prohibited bit does not change, and only the value of the lower bits is automatically and sequentially repeated. Thereby, the EXDMAC 4 can control the data transfer address so as to automatically configure the ring buffer. When RPB2-0 = B'110 or B'111, carry / borrow is permitted and no repeat is performed.

Bits 7 and 6 are SM1 and SM0 bits, and specify whether to increment, decrement, or fix SAR 40 after data transfer. When the SM1 bit is cleared to “0”, the SAR40
Is fixed. When the SM0 bit is cleared to "0" while the SM1 bit is set to "1", the increment is performed, and when the SM0 bit is set to "1", the decrement is performed.

Bits 5 and 4 are DM1 and DM0 bits, and specify whether to increment, decrement, or fix DAR 41 after data transfer. When the DM1 bit is cleared to “0”, DAR41
Is fixed. When the DM0 bit is cleared to "0" while the DM1 bit is set to "1", the increment is performed, and when the DM0 bit is set to "1", the decrement is performed.

Bits 3 to 1 are MD2, MD1, MD0
This bit selects the data transfer mode. When the MD2 bit is set to “1”, EXDMAC data registers (EXDiDR0 to EXDiDR15) are designated as the source or destination location. For example, lower 4 bits of TCR (when SZ = 0)
Or EXDiDR0 to EXDiD according to the contents of the lower left 3 bits (when SZ = 1) shifted left.
R15 is selected.

When the MD0 bit is cleared to "0", the transfer sources are EXDiDR0 to EXDiDR15. When the MD0 bit is set to “1”, the transfer destination is EXDiDR0 to EXDiDR15. In this case, only one data access is performed regardless of the state of the MD1 bit. MD1 bit is set to “0”
, Normal reading or writing is performed. If the MD1 bit is set to "1", reading or writing is performed by the acknowledge signal.

When the RPE bit is set to "1", the TCR is divided into bits 15 to 8 (TCRH) and bits 7 to 0 (TCRL), and the TCRL operates as a transfer counter. When TCRL becomes 0, T
The contents of the CRH are copied to TCRL. Therefore, TC
If the same content is set in RH and TCRL, EXDi
DR0 to EXDiDR15 are used repeatedly.

When the MD2 bit is cleared to "0", the following is performed. When the MD1 bit is cleared to "0", a dual address mode is set. In the dual address mode, one data transfer (two data accesses of read and write) is performed from an address indicated by SAR to an address indicated by DAR by one activation. Thereafter, based on the designation of the SM1, SM0, DM1, and DM0 bits, SAR and DAR operations and TCR decrement are performed.

When the MD1 bit is set to "1", a single address mode is set. In the single address mode, one of a transfer source and a transfer destination is specified by an acknowledge signal.

If the MD0 bit is cleared to "0", the transfer destination is specified by an acknowledge signal, and the SAR specifies the transfer source address.

If the MD0 bit is set to "1", the transfer source is specified by an acknowledge signal, and the SAR specifies the transfer destination address.

Data transfer (two data accesses of read and write) is performed. Thereafter, based on the designation of the SM1 and SM0 bits or the DM1 and DM0 bits, S
AR or DAR operation and TCRT decrement are performed.

Bit 0 is an SZ bit, and selects whether to perform one data transfer in byte size or word size. When the SZ bit is cleared to "0", byte size data transfer is performed, and when it is set to "1", word size data transfer is performed. The word size is 2 bytes.

FIG. 6 is a block diagram of the EXDMAC 4. The control circuit 45 of the EXDMAC 4 receives a start request signal EXDREQi (i = 0 to 3) from outside.
The control circuit 45 of the EXDMAC 4 sends an external bus right request EXBREQ to the external bus controller 121.
2. Generates an external bus command BCMD and outputs an address. The external bus controller 121 outputs an external bus right acknowledge signal EXBACK2 and an external bus ready signal E.
Enter XBRDY. EXDACKi used at the time of single address transfer is specified by the external bus command BCMD or the like as described above. External bus ready signal EXB
The negated state of RDY can be recognized as a request from the external bus controller 121 to insert a wait state into the EXDMAC 4. EX from the external bus controller 121 to the internal bus controller 120
BRDY can also be grasped as a request for weight insertion.

The control circuit 45 outputs, as the EXDiDRm selection signal 45S, the data transfer channel number for which operation has been instructed and the count value of the TCR 48 of the data transfer channel.

Further, for interfacing with the CPU 2 and the DMAC 3 inside the microcomputer 1,
A module select signal, a read signal, and a write signal are input from the internal bus controller 120, and are connected to the address bus PAB and the data bus PDB.

In the dual address mode, the general-purpose DMAC 3 temporarily stores the read data in the DMAC 3 and writes it. In contrast, EXDMAC
4 replaces this function with an input / output port,
(D) 24 and the latch circuit 72L of the IOP (E) 25 have a function of temporarily holding data. As the operation of the microcomputer is accelerated, a pipeline-like operation is required, and the DMAC 3 performs a read / write operation for data transfer in which the DMAC 3 itself has a bus right and a setting of data transfer control conditions for the DMAC 3 by the CPU 2. If the read / write operation is continuous, the DMAC 3 makes it difficult to transition between the operation as the bus master and the operation as the bus slave, the operation cannot be completed within a predetermined state, or an inconvenient operation occurs. The possibilities increase. In this regard, at least with respect to data input / output, the function as a bus master is replaced with an input / output port, and the EXDMAC 4 can essentially avoid the inconvenience. Even during the data transfer control by the EXDMAC 4, the CPU 2 can perform the access operation using the internal bus, so that the CPU 2 can read the register inside the EXDMAC 4 at an arbitrary timing. Therefore, the status of the EXDMAC 4 can be easily monitored from the CPU 2.

The EXDMAC 4 is intended to perform data transfer independent of the CPU 2. At this time, in a dual addressing mode or the like, if the own module intends to temporarily hold read data,
It becomes necessary to provide a dedicated data bus. EXD
Since the MAC4 does not require such a dedicated data bus, the physical scale can be reduced in this respect as well.

According to FIG. 6, the EXDMAC 4 comprises the following circuit blocks. EXDMAC4 is based on the DT
A register for MR42, DAR41, SAR40, and TCR48 is provided for each of four channels, and a control circuit 45 as a transfer control means common to each channel and a data buffer (D
B) 44, an address buffer (AB) 46, and an arithmetic operation circuit (AU) 43. These blocks are
The bus and the B bus are connected by two internal buses.

The control circuit 45 controls the activation request signal EXDRE.
Qi (i = 0 to 3) is detected to start the operation, output the external bus right request EXBREQ2, the external bus command and the address, and output the external bus right acknowledge EXBAC.
K2, while inputting the external bus ready signal EXBRDY,
Performs external bus operation. On the other hand, according to the module select signal, the read signal, the write signal, the lower bits of the address on the address bus PAB, and the value of the data bus PDB,
Performs input / output of internal registers.

The address buffer 46 has a 24-bit structure corresponding to the external address space of 16 Mbytes, receives data from the A bus, holds an address to be read / written, and stores the address in the external address bus. EXAB
To output an address signal.

The data buffer 44 has a 16-bit configuration and is connected to the data bus PDB.
Inputs / outputs data when reading / writing a register inside the DMAC 4. Since the SAR 40 and the DAR 41 have a 24-bit configuration, they are accessed by the CPU 2 in two separate steps. At this time, the EXDMAC 4 performs one read / write operation so as not to perform an inconvenient operation.

The DTMR42, DAR41, and SA
The function of each register of R40 is as described above. Data is input from the B bus and output to the A bus. TCR48
Only, when the RPE bit is set to "1", bits 7-0 function as a counter, and when this bit becomes 0, the contents of bits 15-8 are copied.

The arithmetic operation circuit (AU) 43 performs an increment / decrement process. The input is the A bus and the result is output on the B bus.

In order to read / write data from / to the CPU, another bus connecting the DB and each register may be provided.

FIG. 7 is a state transition diagram of the EXDMAC 4. EXDMAC 4 has three states: state I (idle state), state S (source transfer state), and state D (destination transfer state).

After the reset, the state transits to the state I.
In state I, the activation request signal EXD
REQi (i = 0 to 3) is sampled. When the EDTE bit of any channel is set to 1, the EXDREQi input of that channel is detected. When a plurality of channels are activated, the operation is performed with priority over channel 0.

When EXDREQi is activated, the state transits to State S. In state S, S
The contents of AR 40 are output to EXAB, the contents of SAR 40 are updated according to SM1 and SM0 bits, and an external bus request EXBREQ2 and a bus command are output to external bus controller 121. MD2 = 1, MD
If 0 = 0, EXDiDRm is used instead of SAR. The bus command includes information indicating the single address mode, a latch circuit and a data register EXDiD.
Rm control information is also included.

The external bus controller 121 arbitrates the external bus request and, at a predetermined timing, EXDM
In order to give the AC4 the external bus right, the acknowledge signal EXBACK2 is activated to activate the external bus.
When MD2 = 1 and MD0 = 0, EXDiDR
0 to EXDiDR15, the contents of the specified data registers are output. When the external bus ends, the external bus ready signal EXBRDY is activated. This allows
EXDMAC 4 can end the bus cycle in its state S.

In the state S, MD1 + MD2
= 1, that is, MD2 = 0 and MD1 = 1 (EXDi
Single addressing mode without DRm), M
D2 = 1 and MD1 = 0 (corresponding to the dual addressing mode using EXDiDRm), MD2 = 1 and MD
When 1 = 1 (corresponding to the single addressing mode using EXDiDRm), when the bus acknowledge signal EXBACK2 is active and the external bus ready EXBRDY is detected, the EXDMAC 4 ends the operation and transits to the state I.

In the state S, MD1 + MD2 =
0, that is, MD1 = 0 and MD2 = 0 (EXDiD
Rm is not used in dual addressing mode)
When the acknowledgment signal EXBACK2 is active and the external bus ready signal EXBRDY is detected as active, the state transits to state D. At this time, the data read from the source location in the state S is transferred to the ports IOP (D) 24 and IOP (E) according to the bus command.
25 latch circuits 72L. State D
Then, the contents of the DAR 41 of the channel are output to the address bus EXAB, and the contents of the DA
It updates the contents of R41 and outputs an external bus request EXBREQi and a bus command to the external bus controller 121. The external bus controller 121 activates an external bus.

When the external bus is completed, the external bus ready signal EXBRDY is activated. EXDMAC4 is
When an external bus ready EXBRDY is detected while the bus acknowledge signal EXBACK2 is in an active state, the access cycle ends and the state transits to state I.

In the single address mode, the control circuit 45 gives an instruction to activate the transfer acknowledge signal EXDACKi in the state S bus command. In the case of the dual address mode, in the state S bus command, an instruction not to transfer the bus right after the read and the read data are transmitted to the IOP (D) 24 and the IOP
(E) An instruction to temporarily hold the latch circuit is given. Similarly, input / output of EXDiDRm is also instructed.

FIG. 8 shows the I / O port (input / output circuit)
A schematic configuration of the IOP (D) 24 and the IOP (E) 25 is exemplified. In the figure, the input / output circuits IOP (D) 24, I
The illustration of the address system of OP (E) 25 is omitted.

As a basic function of the I / O port, it has a data direction register DDR, an output data register DR, and an input data register PORT. Also, as a function of the data bus, it performs input / output with the internal data bus IDB. In addition to these, the EXDMAC 4 latch circuit (LTC) 72L and the data register EX
Has DiDRm. Data register EXDiDR
m performs input / output with an external bus terminal (pad) P and input / output with an internal bus PDB. The input / output to / from the external bus (terminal) P is at the time of the data transfer of the EXDMAC4.
Input / output with the DB is at the time of reading / writing by the CPU 2.

The DDR controls the output buffer OTB via the control circuit CONT. The output buffer OTB is
The operation mode is controlled by an external bus control signal and a data direction register DDR. In single-chip mode, the external data bus is not used,
Data direction register DDR as / O port
Controls the input and output. In the extension mode, since the external data bus is used, the output is performed at the time of writing (other than the single address mode) by the external bus control signal regardless of the data direction register DDR.

As data to be output, a data register DR, an internal data bus IDB, a latch circuit 72L, and a buffer register EXDiDRm are selected by a selection circuit SCCT. The selection is controlled by the operation mode, the external bus control signal, and the data direction register DDR. In the single chip mode, since the external data bus is not used, the data register D is used as an I / O port.
R is selected. In the extension mode, the internal data bus IDB is selected when the internal bus master performs an external write.
At the time of writing in the dual address mode of the EXDMAC 4, the latch circuit is selected. During writing from the data register to the external bus by the EXDMAC 4, the buffer register EXDiDRm is selected. The register to be used among the EXDiDRm is specified by the value of a predetermined plurality of bits of the transfer count register output from the EXDMAC 4 and the content of the selection signal 45S including the channel number.

The state of the terminal P is input via the input buffer INB and transmitted as follows. When the internal bus master reads the I / O port, the input data register PO
Output from RT to internal bus PDB. At the time of external reading of the internal bus master, it is output to the input data buffer IDB. When reading in the dual address mode of the EXDMAC 4, the data is input to the latch circuit 72L. EXDMAC4
Can be held in the buffer register EXDiDRm at the time of data input from the external bus.

The external bus control signal is EXDMAC
4 and the external bus controller 121 outputs based on a bus command output from the internal bus controller 120 or the like. When an 8-bit / 16-bit data bus is mixed, an external bus control signal including bus width control is generated. For example, when transferring word-size data from an 8-bit data bus space to a 16-bit data bus space, two data reads are performed continuously, and the data read to the IOP (D) 24 side is transferred in byte units. Then, the data is sequentially input to the latch circuit. At the time of writing, the data of this latch circuit is transferred to IOP (D) 24, IOP
What is necessary is just to control so that the output is collectively output to the OP (E) 25.

FIG. 9 shows an example of a microcomputer system using the microcomputer for controlling a printer.

The printer control system includes a microcomputer 1, a communication circuit 100 such as a Centronics interface, a universal serial bus (USB), IEEE 1394 or an option, a buffer RAM 101 composed of a DRAM, a character generation ROM.
A (CGROM) 102, a program ROM 103, and a print control circuit 104, which are connected via an external bus 105 of the microcomputer 1.

The program ROM 103 stores area 0
The buffer RAM 101 stores the CGROM 1 in area 2.
02 is the communication circuit 100 and the print control circuit 1 in area 6.
04 is assigned to area 7. Buffer RAM
A refresh operation is required as a readable / writable memory for the 101, but a DRAM which is known to be inexpensive is used. In FIG. 9, the buffer R
The address arrangement of the AM 101 is illustrated. According to this example, the buffer RAM 101 has 2 MB
It has a storage capacity of (16 Mbits), of which 1 Mbyte is used as a work area for the CPU 2 and the rest is used as a ring buffer of 512 kB.

In the system shown in FIG.
06, buffer circuit 107, line feed motor 10
8, a carriage return motor 109, which is controlled by the output of the timer 7 of the microcomputer 1 and the output of the pulse output device 8, respectively. Line feed motor 108,
Although not particularly limited, the carriage return motor 109 is a stepping motor.

Although not shown, the SCI 9 of the microcomputer 1 is used for communication with a host device or the like, and the A / D converter 10 inputs sensor information such as the number of sheets.

The EXDMAC 4 receives data by a plurality of communication circuits 100 such as a Centronics interface and a universal serial bus in parallel with the operation of the CPU 2. The microcomputer 1 sends a transfer request signal E
XDREQi is input and the transfer acknowledge signal EXDA
Single address transfer can be performed by CKi. For example, the input strobe signal of the Centronics interface is input to EXDREQ0, dual address transfer is performed on channel 0, the reception signal of the optional interface is input to EXREQ1, and EXDAC is input.
The K1 output is supplied to the option interface to perform single address transfer on channel 1.

Prior to substantial data transfer, transfer information such as a packet command is transferred to the data register (EXDiDRm) of EXDMAC4. The CPU 2 analyzes this information, and if it is sufficient to receive the information continuously from the previous data transfer, for example, the MD2 bit is cleared to “0”, the TCR 48 is set, and the CPU 2 is activated.

When the status of the printer is to be read from the host, the EXD2DR of channel 2 is used.
The CPU 2 can write the status into 0 and 1 as needed, output the status to the communication circuit 100 according to the EXDREQ2 input, and transfer the status from the communication circuit 100 to the host. For example, the CPU 2 sets a status indicating waiting for transfer information to EXD2DR0 and EXD2DR1. When the transfer information of the packet command is received from the host, the busy status is indicated by EXD2DR0, EXD2DR0,
XD2DR1 is set, and the analysis of the transfer information is completed.
When the setting of the DMAC 4 is completed, the status indicating waiting for data reception is set to EXD2DR0 and EXD2DR1. The host may transmit the transfer information and data while checking the status at any time.

An internal DMAC 3 outputs print data,
The pulse data is output to drive the line feed motor 108 and the carriage return motor 109.
Further, the transmission of the SCI 9 and the reception data are performed. Such a method of using DMAC3 is described in the above-mentioned Japanese Patent Application Laid-Open No. 5-307516.

By improving the degree of integration of the semiconductor integrated circuit, part or all of the communication circuit 100 other than the option, the print control circuit 104, and the like can be integrated in a one-chip microcomputer. Furthermore, the buffer RA
General-purpose memories such as M101 can also be integrated in a one-chip microcomputer. Program ROM
It is more convenient to use an individual semiconductor integrated circuit for a device that changes for each microcomputer system, such as an individual printer model, such as 103 and the CGROM 102. Whichever part is mounted on a one-chip microcomputer, the logical configuration of the bus need only be the same as described above.

FIG. 10 shows an example of the operation timing of the bus of the microcomputer system. The figure shows the operation timing when receiving transfer information such as a packet command of 10 bytes (5 times) on channel 0 and performing data reception through setting change by the CPU 2.

Channel 0 transfer count register TCR
(TCR0) is set to H'000005.
For each EXDREQ0, a predetermined address of the Centronics interface is read, and one-word data, here, transfer control data such as a packet command, is stored in the data register EXD0DRm. The order of storing data registers is EXD0DR9 to EXD0DR.
8, EXD0DR7 to EXD0DR6, EXD0DR5
~ EXD0DR4, EXD0DR3 ~ EXD0DR2,
EXD0DR1 to EXD0DR0. When the five data transfers have been completed, the transfer count register TCR becomes 0, the EDE bit is set to "1", and the C
An interrupt is requested to PU2.

Upon receiving the interrupt, CPU 2 sets EXD0
Analyzing the transfer control information stored in DR9-0,
Set the transfer count register (TCR) 48 and set MD2
Necessary settings such as data transfer conditions such as clearing the bit to “0” are performed. SAR 40 of channel 0 (SAR
0) is a predetermined address of the Centronics interface and does not need to be changed. Also, D of channel 0
The AR41 (DAR0) holds the next address of the previous data transfer, and therefore does not need to be changed when storing at consecutive addresses. Thus, after the transfer control condition is reset, the transfer control of the data information following the packet command is performed.

More specifically, this timing chart is representative of two transfer information receptions and one CPU
Of the EXDMAC 4 (re-setting of the transfer control information) and one reception of the data information.

In the internal buses IAB and IDB, most of the program read from the ROM 5 and the data read / write to the RAM 6 of the CPU 2 are performed in one state. In this, the CPU 2 sends the P buses PAB, PD from T8.
Write EXDMAC 4 using B. This write operation is a reset operation of the transfer control condition based on the interrupt.

The DMAC 3 transfers data from the internal I / O register (for example, the SCI reception data register) to the memory (RAM) 6 from T3.

On the other hand, EXDMAC 4 outputs signal EXDRE.
Q0 activates channel 0 at T0, T4 and sends the buffer register EX from the Centronics interface.
D0DRm holds the transfer control information, and is activated at T13 to transfer data information from the Centronics interface to the buffer RAM 101.

That is, the EXDMAC 4 uses the EXDR
In response to the activation of the EQ0, the state transits to the state S at T2, and the external bus request and the external bus command BC are transmitted.
Generates MD and outputs address information to EXAB. The external bus command 121 is read and EX of read data.
An instruction such as writing to D0DRm is given. The external bus controller 121 arbitrates for the external bus right and immediately executes EXDM.
The external bus right is given to AC4 to activate the external bus. Once EXBRDY is deactivated, EXDMAC4
Weight.

When signal EXBRDY is activated, E
XDMAC 4 transitions to state I and returns to the standby state.
Since the MD2 bit is set to “1”, MD1
Even if the bit is cleared to "0" (dual address mode is specified), data access (bus cycle) is completed only once. At T3, the data obtained on the external data bus is transmitted to the external bus controller 121.
(D) 24, IOP (E) 25
Is written to EXD0DRm.

Buffer register EXD0D to be written
Rm is specified by the lower bits of TCR48.
Actually, as described above, EXD0DR9 to EXD0DR
8, EXD0DR7 to EXD0DR6, EXD0DR5
~ EXD0DR4, EXD0DR3 ~ EXD0DR2,
The data is written in the order of EXD0DR1 to EXD0DR0.
In this timing chart, at T3, EXD0DR3 to EXD0
To DR2, at T7 to EXD0DR1 to EXD0DR0,
Please understand that it is written.

At T6, the TCR 48 is decremented. When the TCR 48 becomes 0, the EDE bit is set to "1".
At 7, the CPU 2 is requested to interrupt. In response to this, the CPU 2 performs interrupt exception processing and the like. In the interrupt processing routine, the CPU 2 reads the contents of EXD0DRm and changes the setting of the transfer control condition of the EXDMAC 4, and the like.
Only one write operation to AC4 is shown. EXD
Since 0DRm and EXDMAC4 also use the P bus and can be read / written without using an external bus, data transfer of EXDMAC4 of another channel is not restricted.

After the setting change of the channel 0 of the EXDMAC 4, at T13, the EXDMAC 4 transitions to the state S in response to the activation of the EXDREQ0, and generates an external bus right request and an external bus command BCMD. The address information is output to the bus EXAB. The external bus command BCMD at that time instructs read, transfer of bus right after read, latch of read data, and the like. The external bus controller 121 arbitrates for the external bus right, and immediately,
The external bus right is given to the EXDMAC 4 to activate the external bus. Once the signal EXBRDY is deactivated,
XDMAC 4 is made to wait.

When signal EXBRDY is activated, E
XDMAC 4 transitions to state D, generates an external bus right request and an external bus command BCMD, and outputs address information to bus EXAB. The external bus command BCMD
Indicates write, output of latched data, and the like. The external bus controller 121 activates the external bus, temporarily deactivates the signal EXBRDY, and
The DMAC 4 is made to wait. When the signal EXBRDY becomes active (high level), the EXDMAC 4 transitions to state I and returns to the standby state. MD2 bit is “0”
, The data access is performed twice according to the fact that the MD1 bit is cleared to “0” (dual address mode is designated). The first time is a read from the Centronics interface as in the case of the transfer information read. The second is writing of the received data to the buffer RAM 101.

The external bus controller 121 determines the access to the area of the buffer RAM 101, and sends the external bus control signals to the IOP (A) to IOP (A) to access in four states including the precharge, RAS, and CAS cycles.
OP (F). The immediately preceding access to the buffer RAM 101 and the RAS address are compared, and if within the same page, the high-speed page mode using only the CAS cycle is used.

FIG. 11 shows another example of the bus operation timing in the microcomputer system of FIG. Here, attention is paid to the case where the latch circuit 72L is used.

As described above, most of the internal buses IAB and IDB are used for reading a program from the ROM 5 and reading / writing data to the RAM 6 of the CPU 2.
The CPU 2 reads an internal I / O register (for example, an A / D converter) using the P buses PAB and PDB from T3, and reads an external memory (for example, CGROM) from T12.
Lead. Since the circuits connected to the P buses PAB and PDB have a lower access speed than the RAM 6 and the ROM 5, the bus ready signal BRDY is output from the bus controller 120.
Supplied by

The DMAC 3 transfers the data from the memory to the internal I / O register (for example, from the RAM 6 to the pulse output circuit 8) from T7.

On the other hand, in EXDMAC 4, channel 0 is used for dual address transfer, channel 1 is used for single address transfer, channel 0 is activated at T0, and T7, T14
Starts channel 1. Note that the activation request signal EXD
REQi (i = 0 to 3) are superimposed and displayed, for example, a portion described as ch0 indicates that EXDREQ0 has been activated.

At T0, EXDMAC4 outputs EXDREQ.
In response to the activation of 0, the state transits to the state S, generates an external bus request and an external bus command BCMD, and outputs EXAB. The external bus command BCM
D instructs read and transfer of bus right after read, latch of read data, and the like. External bus controller 12
1 arbitrates for the external bus, and according to signal EXBACK2,
Immediately, the external bus right is given to the EXDMAC 4 to activate the external bus. The external bus controller 121 once
The bus ready signal EXBRDY is set to the inactive state (low level) to cause the EXDMAC 4 to insert a wait cycle.

At the end of T3, the read data is
Stored in 2L. Prior to this, the bus ready signal EXBR output from the external bus controller 121 is output.
When DY is returned to the active state, the EXDMAC 4 ends its memory cycle, transits to state D, generates the next external bus request and external bus command BCMD, and outputs an address to the bus EXAB. The external bus command BCMD instructs write, output of latched data, and the like. The external bus controller 121 activates an external bus. As described above, the external bus controller 121
Once the signal EXBRDY is deactivated, EXDM
Cause AC4 to insert a wait cycle.

When signal EXBRDY is activated, E
XDMAC 4 completes the memory cycle, transits to state I, and returns to the standby state.

At T7, in response to the signal EXDREQ1 being activated, the EXDMAC 4 transitions to state S, generates an external bus request and an external bus command BCMD, and outputs an address signal to the bus EXAB. The external bus command BCMD is read and signal EXDACK.
1 is instructed to the external bus controller 121. The external bus controller 121 arbitrates for the external bus right, and immediately receives the EXDMAC4
To the external bus and start the external bus. As described above, once the signal EXBRDY is deactivated,
Cause the DMAC 4 to insert a wait cycle. The external bus controller 121 determines access to the DRAM area and accesses in four states including a precharge, RAS, and CAS cycle. When the signal EXBRDY is activated, the EXDMAC 4 transitions to state I and returns to the standby state.

Further, at T14, in response to the signal EXDREQ1 being activated, the EXDMAC 4 transitions to the state S, where the external bus request and the external bus command BC are transmitted.
Generates an MD and outputs an address signal to the bus EXAB. The external bus command BCMD instructs a read operation, a signal EXDACK1 output, and the like. At this time, the external bus controller 121 arbitrates the external bus right,
Since the external read is being executed by U2, the external bus right is not given to the EXDMAC 4, and the end of the external read by the CPU 2 is waited. At T17, the external bus right is given to the EXDMAC 4 to activate the external bus. Once as described above, the external bus controller 121 inactivates the bus ready signal EXBRDY and requests the EXDMAC 4 to insert a wait cycle. When the signal EXBRDY is activated, E
XDMAC 4 transitions to state I and returns to the standby state.

In DTMR1, DTIE = 0, RPB2
ＲＰRPB0 = B′011, SM1, SM0 = B′10, and a repetition operation in units of 512 kB is set. When the DAR40 (DAR1) of the channel 1 is incremented at T9, H′5FFFFF is changed to H ′. 5
It is updated to 80000 and the operation continues. That is, H'5
80000 to H'5FFFFF buffer RAM101
The upper ring buffer is configured. CPU2 reads DAR40 (DAR1) of channel 1 to
The input pointer of the ring buffer can be obtained. It becomes easy to read the ring buffer while referring to the input pointer so that the amount of data stored in the ring buffer becomes appropriate.

Further, since the EXDMAC 4 continues to operate without being stopped, the start request signal is not undesirably detected or cannot be detected at the time of restart.

When the CPU 2 requests read / write using the external bus and external bus transfer by the EXDMAC 4 at the same time, either the CPU 2 or the EXDMAC 4 temporarily stops, but the data access frequency of the CPU 2 is low and the CPU 2 In many cases, the access is not performed continuously, and the EXDMAC 4 does not continuously perform the data transfer. Therefore, it is possible to prevent the CPU 2 and the EXDMAC 4 from being stopped for a long time. At least the CPU 2
Executing the above program and external bus transfer by the EXDMAC 4 can be performed in parallel. In other words, external bus transfer can be performed without deteriorating the processing performance of the CPU 2. External data transfer by the EXDMAC 4 can be performed in parallel with transfer by the internal bus by the DMAC 3.

The transfer of the bus right between the CPU 2 and the DMAC 3 can be performed without overhead by synchronizing the internal bus request or the internal bus acknowledge signal with a clock or a bus ready signal. Similarly, CPU2
Alternatively, transfer of the bus right between the external access of the DMAC 3 and the EXDMAC 4 can be performed without any overhead.

FIG. 12 shows the general-purpose DMAC3 and EXD
External bus DMAC4A having both functions with MAC4
Is shown in FIG.

The data transfer channels are set to 0 to 7, and DTMR 42, SAR 40,
It has a DAR 41, a transfer counter TCR48, and another transfer counter (BTCR) 47B. Arithmetic operation unit 43A
Are provided with a shifter 47C, and there are three types of internal buses: an A bus, a B bus, and a C bus.

In the example of FIG. 10, similarly to FIG. 6, the interface to the external bus controller 121 and the CPU 2
In addition to the interfaces with the internal bus controller 120, an internal bus right request signal, an internal bus command, an IAB output, an internal bus right acknowledge, an internal bus ready input, and an IDB input / output are added.

When the EDTE bit of the DTMR 42 is set to “1”, the external bus controller 121
Output an external bus request or an external bus command,
The transfer on the external bus can be performed in parallel with the execution of the program on the internal bus by the CPU 2.

On the other hand, the I-not shown I
When the DTE bit is set to “1”, an internal bus right request or an internal bus command is output to the internal bus controller 120 to transfer data between arbitrary addresses using the internal bus (I bus). , And the operation of the CPU 2.

According to the configuration shown in FIG. 12, limited channels such as eight channels can be used by mutually interchanging. The external bus transfer as the external bus DMAC 4A can be two channels, and the transfer using the internal bus can be six channels. Also, logic such as an arithmetic operation unit and a bus interface can be commonly used. When a plurality of activation requests are generated, the priority of the external bus transfer may be set higher to enable parallel operation with the CPU 2.

Further, if a control circuit for external bus transfer and a control circuit for internal bus transfer are separately provided, and each arithmetic operation unit and bus are separately provided, external bus transfer and internal bus transfer operate in parallel. It becomes possible.

When the single address mode is selected, the external bus transfer is performed. When the dual address mode is selected, the internal bus transfer is performed. If the selectable activation factors are limited according to this, the usability is not significantly reduced. , Control bits can be saved.

FIG. 13 shows an example of a flow chart of data transfer between the printer system and a host device (not shown) connected to the host interface in the printer system shown in FIG.

When the host device prepares data such as a document and an image to be printed as required data, the host device starts data transfer. The host device first checks the status of the printer in S1. The microcomputer 1 transmits the status information set in EXDDR to EXD as described above.
Output by MAC4.

In the ready state, the host device sends transfer information in S2. Such transfer information includes information such as the content to be processed and the subsequent data length. The transfer information is stored in EXDDR by EXDMAC4. The CPU 2 analyzes this content and outputs
To reset the settings.

In S3, the status of the printer is checked. If the status is ready, the host device transfers the data in S4. The above data is stored in the buffer RAM 101 by the EXDMAC 4. The CPU 2 performs a required printing process on the data stored in the buffer memory.

In S5, the host device confirms completion of data transfer or printing as confirmation of the status.

FIG. 14 shows a modification of a microcomputer system using a single-chip microcomputer to which the present invention is applied for printer control.

In the present system, a flexible disk drive 110 is added. For example, image data from a digital still camera or the like can be input and printed by the flexible disk drive 110 without passing through a host device.

In this case, the microcomputer can give a data read command. For example, the CPU 2 prepares a data read command in EXDDR, and the EXDMAC transfers the command to the flexible disk drive 110. Or CPU2
Command is sent to the flexible disk drive 11
It may be transferred to 0. The CPU 2 resets the EXDMAC so as to correspond to the command.

The flexible disk drive 110
When data transfer corresponding to the above command is ready,
A request for data transfer is made by EXDREQ. The EXDMAC can transfer data from the flexible disk drive 110 to the buffer RAM 101 in response to the data transfer request.

Further, instead of the flexible disk drive, an EEPROM device composed of a flash memory or the like may be used via an interface. In particular, the recording medium and its form are not limited.

FIG. 15 is a block diagram of a main part of the external bus controller 121 and the buffer 72. IAB and EXAB are connected to the address decoder 1211 of the external bus controller 121, and the bus right to the external bus is determined by an external bus command. CPU2 or DMAC3
IA has the right to the external bus,
B, decode the address input from
When 4 has the bus right, it decodes the address input from EXAB. The result of decoding is passed to the control circuit 1212 as an area selection signal 1215.

The control circuit 1212 refers to the setting of the control register 1213 corresponding to the selected area. ABWCR, ASTCR, DR as an example of the control register
AMCR is shown. ABWCR and ASTCR
Has 8 bits each corresponding to an area, and selects 8 bits / 16 bits of the bus width and selects 2 states / 3 states of access. DRAMCR is DRAM
Specify interface settings, select address multiplex shift amount, etc.

The control circuit 1212 determines the bus cycle to be executed as described above, and
4 is started.

The timing control circuit 1214 outputs a control signal 1216 and controls the address multiplexer 722A according to an external bus command and a bus cycle specified by the control circuit 1212. Also, at the end of the external bus cycle, it outputs an external bus right arbitration timing signal 1217 for instructing arbitration of the external bus right.

FIG. 16 shows an example in which a DRAM control signal is described in the bus operation timing of the microcomputer system.

The RAS signal and the CAS signal are used for the address control of the DRAM. First Page (Fast Page) DRAM and EDO (Extended Data Out)
DRAMs such as a DRAM and a synchronous DRAM have a high-speed page mode for performing high-speed data access. In fast page mode, DRA
In order to access M, the RAS signal and the CAS signal are set to the selected state, and the RAS signal is kept in the selected state even after the DRAM access is completed. At the time of the next DRAM access, it is determined whether or not the data to be accessed is included in the access page at the time of the previous DRAM access. In the same page, only the CAS signal is set to the selected state again, so that the DRAM can be accessed. For example, in the write cycle of channel 0 of the EXDMAC from the timing T4, access is performed in two states in which the CAS signal is in the selected state.

In the single address cycle of channel 1 from T8 and T17, at the time of accessing the DRAM, the RAS signal is first set to the non-selection state, the precharge cycle has passed one state, and the RAS signal cycle has one state. RAS signal is selected during the process.
Thereafter, a CAS signal cycle is executed for two states, and DR
AM access is completed.

In this drawing, a refresh cycle of the DRAM is executed from T21. The refresh cycle is executed by a refresh timer on the semiconductor integrated circuit issuing a request at predetermined time intervals and securing a bus right. In the example of this timing chart, CA
S-before-RAS (CAS-before-RAS) refresh is executed, and can be executed in parallel with the internal bus access by the CPU.

FIG. 17 shows a modified example of a microcomputer system using a single chip microcomputer to which the present invention is applied for controlling a digital still camera.

Instead of the line feed motor 108, carriage return motor 109, and print head 106 used in the example of application to the printer shown in FIG. 9, a lens motor 111, a CCD / gain adjustment / correction circuit 112,
For example, a switch 11 functioning as a shutter button
4. LED1 indicating various statuses such as power-on state
15 and a frame memory. The program for controlling the digital still camera may be stored in the ROM 5 on the microcomputer, or may be stored in a program ROM connected to an external bus (not shown).

The microcomputer mainly uses the timer and the input / output signals of the IO to control the lens motor 111.
And the CCD / gain adjustment / correction circuit 112 and the like. The optical signal input through the lens 116 is a CCD
After being converted into an electric signal and subjected to gain adjustment and correction, the signal is stored in a frame memory. The image data stored in the frame memory is transferred to the buffer memory 101 by the EXDMAC 4.

The image data to be stored is EXDMAC4
Is stored in the flash memory device 118 via the interface 117 or output to a host computer or the like connected to the digital still camera via a transmission or reception circuit. Alternatively, data stored in the flash memory device 118 may be output to a host computer or the like via a transmission or reception circuit. These instructions may be made via the switch 114.

This operation is substantially the same as that of the printer except that the data transfer direction is reversed. As in the case of the printer, data received from a host computer or the like via a transmission or reception circuit may be stored in the flash memory device 118 via the interface 117. An on-screen display or the like may be used instead of the LED 115.

Other examples of the microcomputer system to which this embodiment can be applied include a digital video camera,
A digital video disk or the like is conceivable.

FIG. 18 shows an example of a system in which a plurality of the microcomputer systems are connected. In this system, an example is shown in which a personal computer (PC) 130, the printer 131, a television receiver (TV) 132, and the digital still camera 133 are connected via a data communication line 134. Digital still camera 1
The image data shot by 33 is output via a host interface, and can be transferred to a TV or a printer for display / printing, and can also be transferred to a PC. The PC can edit the image data and transfer the edited image data to a TV or a printer in the same manner. In the example of the present system, it is not necessary to fixedly have the host device as shown in the example of the printer, and the data communication line 1 is not necessary.
The device that has first requested the data transfer via 34 may be regarded as the host device.

In this embodiment, a plurality of microcomputer systems are connected by a daisy chain connection, but a star connection or the like via a hub may be used.

As the second data transfer device connected to the first internal bus of the microcomputer,
It is possible to use a data transfer controller (DTC). Regarding the above-mentioned DTC, the present inventor has already filed an application (Japanese Patent Laid-Open No. 7-129537, USP-5809).
259). FIG. 19 shows a block diagram of the DTC.

In the DTC, by arranging the data transfer information on the RAM, storing the data in the DTC from the RAM when the DTC is activated, performing data transfer, and saving the data transfer information on the RAM after the data transfer is completed, An increase in the physical and logical scale of the DTC can be prevented, or a large number of activation requests or transfer requests can be handled, and the number of bits of the address register can be made sufficiently large.

Further, according to the study of the present inventor, such D
The TC itself reads / writes transfer information from a RAM which is a memory shared with the CPU, performs data transfer, has only a function as a bus master, and does not have a function as a bus slave. A conflict operation between access from another bus master such as a CPU and use of the bus of the DTC itself is essentially avoided, so that the logical configuration can be further simplified and the development period can be shortened. There is a lot of room for expanding functions. By combining with external bus DMAC,
Flexible and high-speed data transfer can be performed while simplifying the logical configuration.

Due to the above, the DTC interfaces only with the IDB and has a source address register inside.
(SAR), destination address register (D
AR), transfer count register (TCR), block transfer count register (BTCR), transfer mode register (D
TMR) registers for one channel.

The DTC activation factor is an interrupt factor, and the DTC enable register selects whether to request an interrupt to the CPU or a transfer to the DTC. The start request to the DTC is input to the priority determination circuit, and the start request and the vector number are given to the DTC.

When predetermined data transfer is completed, a DTE clear signal or a factor clear signal is output, and the decode circuit clears the DTE bit or the interrupt factor flag corresponding to the activation factor.

FIG. 20 is a flowchart showing the operation of the DTC. The CPU previously sets the start address (m) of the register file to the DTC vector address on the RAM,
The initial value of the register file is set from the address (m). Thereafter, the permission bit of the interrupt factor (not shown) is set to 1, and the DTC permission bit is set to 1.

When a predetermined interrupt request is generated while the DTC permission bit is set to 1 and the DTC is activated, in step 1 (S1), the vector address register (VAR) is read from the vector address corresponding to the activation factor. ) Is read out and stored in a predetermined register inside the DTC.

In step 2 (S2), the data sequentially read from the address indicated by the contents of the vector address register (VAR) is stored in the mode register (D
TMR), block transfer count register (BTC)
R), a transfer count register (TCR), a source address register (SAR), and a destination register (DAR).

Data transfer is performed in accordance with the contents of the register read in step 3 (S3). The contents of the register are updated with the data transfer.

In step 4 (S4), the contents of the register are stored at the address indicated by the original vector address register (VAR). At this time, the mode register (DTM
If the NXTE bit included in R) is set to 1, the process returns to step 1 (S1), where information to be set in each register is read from consecutive addresses, and data transfer is repeated.

When the NXTE bit is set to 0,
The DTC transfer operation stops. The contents of the transfer counter are 0
If not, the factor clear signal is activated, and the interrupt factor flag is reset to 0 via the interrupt controller. When the content of the transfer counter is 0, the DTC enable bit is reset to 0 without resetting the interrupt factor flag. The transfer counter may use different registers according to the transfer mode of the DTC.

After the transfer operation of the DTC is stopped, the DTC enable bit is reset to 0, and the interrupt cause is held, so that the CPU executes the interrupt exception processing and executes the interrupt processing routine. In the CPU interrupt processing routine,
It is necessary to reset the interrupt factor flag to 0.

According to the embodiment described above, the following operation and effect can be obtained.

[1] The control of the internal bus of the microcomputer 1 and the control of the external bus are made independent, and the operation of the CPU 2 using the internal bus and the data transfer performed using the external bus by the EXDMAC 4 are performed independently. Thereby, the processing performance of the microcomputer 1 can be improved.

Further, the logical configuration of the microcomputer 1 can be simplified without using a bus dedicated to the DMAC or a dual-port type memory.

[2] A buffer register EXDiDRm is provided, which can be used as one of a source and a destination of data transfer, and can store transfer information such as a packet command, for example. The buffer register EXDiDRm does not need to be specified by an address or an acknowledge signal, and is specified by a unique control signal 45S.
When performing transfer with Rm, only one data access needs to be performed, and the speed can be increased. Buffer register EXDi having a unique address in the address space of CPU 2
By using the DRm, the transfer control information
When the analysis is performed, it is not necessary to perform a process of analyzing the address at which the transfer control information is stored. When a plurality of buffer registers EXDiDRm are provided, they are arranged at different addresses and can be read or written in an arbitrary order, so that they can be read in accordance with the format of the transfer control information and the like. It can be easily and speeded up. Higher-speed access can be achieved as compared with the case where the data is stored in an external memory.

[3] By selecting the buffer register EXDiDRm using the transfer counter 48, transfer information such as a packet command of an arbitrary length can be handled as long as the buffer register EXDiDRm has a capacity equal to or less than the capacity of the buffer register EXDiDRm. The buffer register EXDiDRm can be repeatedly used, so that reception of transfer information such as a packet command and the like, output of status, and the like can be repeated.

[4] The transfer control information and the data transfer start factor are made common, and the operation of the other location of the data transfer of the communication circuit 100 and the like can be made common to the transfer control information and the data transfer. External circuits can be simplified. Further, the number of channels required for the EXDMAC 4 can be saved, and the efficiency of hardware utilization can be improved.

[5] The external bus controller 121 divides the address space so that bus specifications such as the type of memory, bus width, and number of access states can be set.
The external bus controller 121 controls the external bus access by the internal bus master DMAC3 and the external access by the EXDMAC4 collectively by the external bus controller 121, thereby enabling the external bus access similar to the CPU2 and the DMAC3 to the EXDMAC4 not using the internal bus. , The increase in logical scale can be reduced.

[6] The address output from the external bus controller 121 is a dedicated signal transmitted via the bus EXAB, thereby simplifying the operation of the control signal and the state transition of the external bus DMAC, and logically. The scale can be reduced.

[7] The external bus controller 121 allows the CPU 2 and the DMAC 3 to access the external bus and
By arbitrating the XDMAC 4 or another external bus right request, it is possible to eliminate the overhead when transferring the external bus right between the external bus access by the CPU 2 and the DMAC 3 and the EXDMAC 4 and further improve the processing performance.

[8] By making the internal ROM 5 for storing the program of the CPU 2 selectable in an operation mode or the like so as not to include the vector of the CPU 2, the entire processing program can be stored in an external ROM and high-speed processing can be performed. Necessary programs and the like can be stored in the built-in ROM 5, and usability such as flexibility in changing programs can be improved.

[0242]

[9] The EXDMAC 4 has a plurality of channels, and each channel has an independent external transfer request input, so that usability can be improved and processing performance can be improved. By supporting single address transfer, bus cycles required for transfer can be reduced, and processing performance can be further improved. Buffer register EXDiD
In the case of using Rm, even in the case of single address transfer, data is input / output, so that transfer information such as a packet command and other data can be transferred without affecting external devices. Data transfer can be performed.

[10] The EXDMAC 4 is a communication circuit 10
Since it has a function suitable for external bus transfer such as data transfer from 0 to the buffer RAM 101 and does not use an internal bus when using the buffer register EXDiDRm, the logical scale can be reduced. By incorporating a latch circuit 72L for temporarily holding transfer data and a buffer register EXDiDRm in an input / output port,
A data bus connecting the EXDMAC 4 to the outside becomes unnecessary, and the physical scale can be reduced.

[11] The upper bits are fixed from predetermined bits of the source / destination address registers 40 and 41 to enable a repetitive operation, and a ring can be easily placed on the buffer RAM 101 or the like without a load on the CPU 2. Buffers can be configured. Even if the starting address and the ending address of the buffer cannot be arbitrarily specified, no major inconvenience occurs in a large-capacity memory such as the buffer RAM 101. The CPU 2 reads the contents of the EXDMAC 4 at any time /
Since writing can be performed, management of the amount of data accumulated on the ring buffer can be facilitated. By enabling the repetitive operation, a load such as an interrupt process of the CPU 2 can be eliminated.

[12] DMAC3 connected to internal bus
, And the data transfer using the external bus by the EXDMAC 4 are performed independently, whereby the processing performance of the microcomputer 1 can be improved. In a microcomputer system such as a printer, a transfer on an internal bus by a DMAC 3 for driving a motor and a buffer RAM of a communication circuit 100 are performed.
It is possible to simultaneously perform transfer using an external bus, such as transfer to the 101, thereby improving the processing performance of the microcomputer system.

[13] By realizing the microcomputer 1, the communication circuit 100, and the like as the same semiconductor integrated circuit, the size of the system can be reduced.

[14] DMAC3 connected to the internal bus
And an EXDMAC 4 specializing in transfer on an external bus, the increase in logical scale can be minimized while increasing the overall number of channels.
Further, the DMAC 3 connected to the internal bus has a general-purpose function, so that the usability is not reduced.

[15] DMAC3 connected to the internal bus
By configuring the EXDMAC 4 as an integrated module, the limited channels can be used interchangeably with each other. Further, a logic such as a bus interface can be commonly used.

[16] A plurality of microcomputer systems can be connected to each other via a host interface circuit. Not only when a host device is fixed, but also when a host device is not provided, other microcomputer systems can be connected. By temporarily regarding the microcomputer system that has made a data transfer request to the microcomputer system as a host device, data transfer between the microcomputer systems can be enabled.

[17] DMAC3 connected to the internal bus
Data transfer controller (DTC)
, Data transfer information can be held in the RAM. As a result, an increase in the physical and logical scale can be prevented, and a large number of activation requests or transfer requests exceeding the number of channels of the DMAC 3 can be handled.

The invention made by the present inventor is not limited to the description of the above embodiment, but can be variously modified without departing from the gist of the invention.

For example, a data transfer device using a buffer register is not limited to EXDMAC4. The buffer register only needs to be specified by the address of the data transfer device or the acknowledge signal, and the data transfer device may be a general DMAC or data transfer controller. For the data transfer controller, March 1995
It is described in "H8S / 2655 Series Hardware Manual" published by Hitachi, Ltd.

The number of buffer registers can be set arbitrarily.
Any number may be used according to the individual system. It may be provided independently for each channel, or may be commonly used between channels. The physical arrangement of the buffer register may be arranged in the module of the external bus DMAC, the module of the bus controller, or the like, in addition to the I / O port.

The number of bits of the address registers of DMAC3 and EXDMAC4 is not limited to 24 bits. The number of address bits can be changed according to the address space of the CPU or the semiconductor integrated circuit. For example, if the address space is 4 Gbytes, the address space may be 32 bits.

A transfer mode in a data transfer device such as EXDMAC4 can be variously changed. The capacity of the ring buffer can also be changed. It may have another register to specify the capacity of the ring buffer. It is also possible to limit to only the single address mode and to use one address register. The configuration of the microcomputer is not limited. In addition, it is also possible to incorporate a functional block.

Also, EXDMAC, bus controller,
The specific circuit configuration such as the configuration of the internal bus can be variously changed. Internal bus such as IAB, IDB and P
An internal bus such as AB and PDB may be integrally formed.

The microcomputer system is not limited to a printer or a digital still camera. For example,
It can be used for digital communication systems and the like. For example, when transferring from the receiving circuit to the buffer RAM, performing demodulation and error correction, performing further modulation, storing in another buffer RAM, and transferring from the buffer RAM to the transmitting circuit.
Transfer from receiving circuit to buffer RAM, buffer RAM
An EXDMAC is used for the transfer from the CPU to the transmission circuit, and external data transfer control can be performed in parallel with the processing of other processors such as a CPU, so that the processing performance can be improved. A data register can be used for receiving and transmitting a packet command, or outputting and inputting a status.

In the above description, the invention which was mainly made by the present inventor and which
The case where the present invention is applied to a built-in microcomputer has been described. However, the present invention is not limited to this. The present invention is also applicable to a microcomputer having no built-in ROM and a data processing device centered on a digital signal processor (DSP). At least, the present invention can be applied to a device having a built-in data transfer device.

[0259]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the buffer interface means is provided in the bus interface means used for external access by the data transfer device, and when the data transfer device transfers data on the external bus, the buffer is used as one of the source and destination locations. By enabling the use of the register means, reception and analysis of transfer control information such as a packet command can be facilitated, and the data transfer operation can be speeded up. This contributes to improvement of the processing performance of the microcomputer and improvement of the usability of the microcomputer.

By configuring the bus and the bus control means so that data transfer on the external bus by the data transfer device and instruction execution using the internal bus by the data processing device such as a CPU can be operated in parallel. In addition, the processing performance of the microcomputer can be improved, the usability can be improved, and the logical and physical scale can be minimized.

It is possible to improve the total performance of data processing by a microcomputer having a built-in data transfer device such as a DMAC.

A microcomputer system to which the above-mentioned microcomputer is applied is capable of controlling data transfer to and from the external device and arithmetic processing inside the microcomputer in parallel, has a small processing overhead, and has a small physical scale. Can also be minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a microcomputer according to the present invention.

FIG. 2 is an explanatory diagram showing an example of an address map in the microcomputer of FIG.

FIG. 3 is a block diagram mainly showing a bus configuration of the microcomputer of FIG. 1;

FIG. 4 is a block diagram illustrating an example of an address decoder included in the bus controller.

FIG. 5 is a block diagram illustrating an example of a register configuration of an external bus DMAC.

FIG. 6 is a block diagram showing the entire external bus DMAC.

FIG. 7 is a state transition diagram of the external bus DMAC.

FIG. 8 is a block diagram schematically showing a configuration of an I / O port.

9 is a block diagram illustrating an example of a system to which the microcomputer in FIG. 1 is applied.

FIG. 10 is a timing chart showing an example of operation timing of the microcomputer.

FIG. 11 is a timing chart showing another example of the operation timing of the microcomputer.

FIG. 12 is a block diagram showing another example of the external bus DMAC.

FIG. 13 is a flowchart illustrating an example of data transfer with a host device.

14 is a block diagram illustrating another example of a system to which the microcomputer in FIG. 1 is applied.

FIG. 15 is a block diagram showing a main part of an external bus controller and a buffer.

FIG. 16 shows the operation timing of the microcomputer and D
5 is a timing chart illustrating an example of a control signal of a RAM.

FIG. 17 is a block diagram showing another example of a system to which the microcomputer of FIG. 1 is applied.

18 is a block diagram illustrating an example of a system in which a plurality of systems to which the microcomputer in FIG. 1 is applied are connected.

FIG. 19 is a block diagram showing an example of a configuration of a data transfer controller applicable to a DMAC 3 connected to an internal bus.

FIG. 20 shows an example of using a data transfer controller.
FIG. 4 is a flowchart illustrating an example of performing data transfer.

[Explanation of symbols]

Reference Signs List 1 microcomputer 2 data processing device (CPU) 3 DMAC 4 data transfer device (EXDMAC) 5 ROM 6 RAM IDB, PDB internal data bus IAB, PAB, EXAB internal address bus 12 bus controller 120 internal bus controller 121 external bus controller 122 refresh Timer 21 to 26 IO port 31 to 35 IO port 40 Source address register (SAR) 41 Destination address register (D
AR) 42 data transfer mode register (DTMR) 43 arithmetic operation unit (AU) 44 data buffer (DB) 45 control circuit 45S EXDiDRm selection signal 46 address buffer (AB) 48 transfer count register (TCR) 72 external bus buffer circuit 72L Latch circuit 72C Control signal output circuit EXDiDRm Buffer register 100 Receiving circuit 101 Buffer RAM 102 CGROM 103 Program ROM

Claims (20)

[Claims] A microcomputer, an interface unit, a bus connected to the microcomputer and the interface unit, and a memory unit connected to the bus, wherein the microcomputer has a data processing unit, an internal memory unit, An internal bus connected to the data processing unit and the internal memory unit, an internal bus control unit that controls access to the internal bus, and an external bus control unit that controls access to the bus.
A data transfer control unit for controlling data transfer of the bus;
A bus interface unit for selectively connecting or disconnecting the bus and the internal bus; access to the internal bus by the data processing unit and access to a bus controlled by the data transfer control unit operating in parallel A microcomputer system characterized in that it is possible. 2. The data transfer control unit according to claim 1, wherein the data transfer control unit includes a transfer destination address register, a transfer source address register, and a transfer data amount for respectively storing a data transfer destination address, a data transfer source address, and a transfer data amount. The data processing unit has at least one register selected from registers, the data processing unit sets predetermined information in the at least one register, and the data transfer control unit has information set in the at least one register. 2. The microcomputer system according to claim 1, wherein data transfer using the bus is performed based on the following. 3. The microcomputer system is connected to a second microcomputer system via an interface unit using a connection line, and the second microcomputer system is connected to the second microcomputer system via the connection line and the interface unit. A data transfer request signal is transmitted to the microcomputer, and in response to the data transfer request signal, the data transfer control unit requests a bus right request for the bus to the external bus control unit, and the external bus control unit Arbitrates a bus right of the bus and gives the bus right to the data transfer control unit. The bus interface unit separates the bus from the internal bus. The microcomputer connects the interface unit to the second microcomputer. A data transfer ready signal is transmitted via the connection line, Transfer control unit through said bus and said interface unit and said connecting line, a microcomputer system according to claim 2, characterized in that the data can be transferred between said second microcomputer systems. 4. The data processing unit sets an address of the memory unit as a data transfer destination address, and the data transfer control unit transmits data transmitted by the second microcomputer system to the connection line and the interface. 4. The microcomputer system according to claim 3, wherein the data is stored in the memory unit via a unit. 5. The microcomputer system according to claim 1,
The microcomputer has a motor controlled by the microcomputer, the microcomputer has a buffer unit connected to the bus, the data has predetermined control information, and in the data transfer, the control information is 5. The microcomputer system according to claim 4, wherein said microcomputer is fetched into said buffer unit, and said data processing unit controls said motor in accordance with said control information. 6. The data processing unit stores transfer data in the memory unit, sets an address of the memory unit storing the transfer data in a data transfer source address, and the data transfer control unit sets the address of the memory unit. 4. The microcomputer system according to claim 3, wherein the transfer data stored in the second microcomputer system is transferred to the second microcomputer system via the interface unit and the connection line. 7. The transfer data comprises predetermined control information and data. The data processing unit issues a bus right request for an internal bus to the internal bus control unit, and transmits a bus right request to the external bus control unit. Request that the bus interface unit connect the internal bus and the bus, and store the transfer data in the memory unit via the internal bus and the bus. 7. The microcomputer system according to claim 6, wherein: 8. The microcomputer system is connected to a second microcomputer system via a connection line via an interface unit, and the microcomputer system is connected to the second microcomputer system via the connection line and the interface unit. A data transfer request signal is transmitted to the microcomputer, and in response to a data transfer preparation completion signal from the second microcomputer, the data transfer control unit requests the external bus control unit for a bus right request for the bus. The external bus control unit arbitrates the bus right of the bus, and gives the bus right to the data transfer control unit, and the bus interface unit separates the bus from the internal bus, and the data transfer control unit includes: The second microcomputer is connected via the bus, the interface, and the connection line. The microcomputer system of claim 2, wherein the between the system is capable of data transfer. 9. The data processing unit sets an address of the memory unit as a data transfer destination address, and the data transfer control unit transmits data transmitted by the second microcomputer system to the connection line and the interface. 9. The microcomputer system according to claim 8, wherein the data is stored in the memory unit via a unit. 10. The microcomputer system has a motor controlled by the microcomputer, the microcomputer has a buffer connected to the bus, and the data has predetermined control information. 10. The microcomputer according to claim 9, wherein, in the data transfer, the control information is taken into the buffer unit, and the data processing unit controls the motor in accordance with the control information. system. 11. The data processing unit stores transfer data in the memory unit, sets an address of the memory unit storing the transfer data in a data transfer source address, and the data transfer control unit includes: 9. The microcomputer system according to claim 8, wherein the transfer data stored in the second microcomputer system is transferred to the second microcomputer system via the interface unit and the connection line. 12. The transfer data includes predetermined control information and data. The data processing unit issues a bus right request for an internal bus to the internal bus control unit, and transmits a bus right request to the external bus control unit. Request that the bus interface unit connect the internal bus and the bus, and store the transfer data in the memory unit via the internal bus and the bus. The microcomputer system according to claim 11, wherein: 13. The microcomputer has a second data transfer control unit connected to the internal bus, the transfer data includes predetermined control information and data, and the data processing unit includes Storing the transfer data in a memory unit, requesting the bus interface to connect the internal bus and the bus, the second data transfer control unit transmits a bus right of the internal bus to the internal bus control unit; Requesting the external bus control unit to make a bus right request for the bus, and transferring the transfer data stored in the internal memory unit to the memory unit via the internal bus and the bus. The microcomputer system according to claim 11, wherein: 14. A microcomputer system capable of connecting a plurality of microcomputer systems by connection lines, wherein the microcomputer system includes a microcomputer, a transmission / reception circuit connected to the connection lines, a storage circuit, and a microcomputer. And a bus connecting the transmission / reception circuit and the storage circuit, a signal line connecting the microcomputer and the transmission / reception circuit, a switch circuit connected to the microcomputer, and a display circuit. Unit, an internal memory unit, an input / output circuit for connecting the switch circuit and the display circuit, an internal bus for connecting the data processing unit and the internal memory unit, and a bus for controlling access to the bus and the internal bus The control unit selectively connects the bus and the internal bus. Or a data transfer control unit for controlling data transfer of the bus, wherein the transmission / reception circuit receives a first signal from the connection line and connects the signal line to a first line. State, the microcomputer is in the first state, the switch circuit is in the first state, the microcomputer is in the second state, the transmission / reception circuit is the second signal on the connection line. And the microcomputer enters the second state. The data processing unit can acquire the bus right of the internal bus regardless of whether the microcomputer is in the first state or the second state. In response to the microcomputer being in the first state, the data transfer control unit requests the bus control unit for bus arbitration of the bus, and The separation of the bus and the internal bus requests the interface unit, after the bus right acquisition, the data transfer control unit, the data received by the transmitting / receiving circuit from the connection line, by using the bus,
Stored at a predetermined address of the storage circuit, and in response to the microcomputer being in the second state, the data transfer control unit requests the bus control unit to arbitrate for a bus right of the bus, and After requesting the interface unit to separate the bus from the internal bus, and acquiring the bus right, the data transfer control unit transmits the data stored at a predetermined address of the storage circuit to the transmission / reception using the bus. A microcomputer system for transmitting a signal from a receiving circuit to the connection line. 15. The transmission / reception circuit receives a third signal from the connection line, sets the signal line to a third state, sets the microcomputer to a second state, and sets the switch circuit to a second state. 15. The microcomputer system according to claim 14, wherein the microcomputer sets the signal line to a fourth state, the transmission / reception circuit transmits a fourth signal to the connection line, and the microcomputer enters the first state. 16. The microcomputer system, wherein a readable / writable recording medium is connected through an interface circuit connected to the bus, and the switch circuit is in a third state. The state becomes the third state, and the switch circuit becomes the fourth state.
When the microcomputer is in the third state, the data transfer control unit requests the bus control unit to arbitrate for the bus right of the bus. Requesting the bus interface unit to separate the bus from the internal bus, and after acquiring the bus right, the data transfer control unit uses the bus stored in a predetermined address of the storage circuit to use the bus. In response to the fact that the microcomputer is in the fourth state, the data transfer control unit requests the bus control unit to arbitrate for the bus right of the bus, and the bus interface unit Requesting separation of the bus and the internal bus, and after acquiring the bus right, the data transfer control unit uses the bus to transfer the data stored in the storage medium to the The microcomputer system of claim 15, wherein the storing in a predetermined address of 憶回 path. 17. The microcomputer system, wherein a readable / writable recording medium is connected via an interface circuit connected to the bus, and the switch circuit is in a fifth state. The state becomes the fifth state, and the switch circuit becomes the sixth state.
In this state, the microcomputer is in the sixth state. In response to the microcomputer being in the fifth state, the data transfer control unit requests the bus control unit to arbitrate for the bus right of the bus. And requesting the bus interface unit to separate the bus from the internal bus. After acquiring the bus right, the data transfer control unit transmits data received by the transmission / reception circuit from the connection line to the bus. In addition to storing the data in the storage medium, if necessary, the data is also stored in a predetermined address of the storage circuit. In response to the microcomputer being in the sixth state, the data transfer control unit includes: Requesting the bus control unit to arbitrate for the bus right of the bus, requesting the bus interface unit to separate the bus from the internal bus, and acquiring the bus right; The unit transmits the data stored in the storage medium from the transmission / reception circuit to the connection line and, if necessary, stores the data at a predetermined address of the storage circuit. 16. The microcomputer system according to item 15, 18. A microcomputer system capable of connecting a plurality of microcomputer systems by connection lines, wherein the microcomputer system includes a microcomputer, a transmission / reception circuit connected to the connection lines, a storage circuit, and a microcomputer. And a bus connecting the transmission / reception circuit and the storage circuit, a signal line connecting the microcomputer and the transmission / reception circuit, a switch circuit connected to the microcomputer, and a display circuit. Unit, an internal memory unit, an input / output circuit for connecting the switch circuit and the display circuit, an internal bus for connecting the data processing unit and the internal memory unit, and a bus for controlling access to the bus and the internal bus The control unit selectively connects the bus and the internal bus. Or a bus interface unit for separating data, and a data transfer control unit for controlling data transfer of the bus. When the switch circuit is in the first state, the microcomputer sets the signal line to the first state. The transmission / reception circuit transmits a first signal to the connection line, the microcomputer goes into a first state, and the data processing section operates regardless of whether the microcomputer is in the first state. In response to the microcomputer being in the first state, the data transfer control unit requests the bus control unit to arbitrate for the bus right of the bus, and the bus interface unit Requesting the separation of the bus from the internal bus, and after acquiring the bus right, the data transfer control unit transmits the data received by the transmission / reception circuit from the connection line. The, using the bus,
A microcomputer system storing the data at a predetermined address of the storage circuit. 19. The transmission / reception circuit according to claim 18, wherein the transmission / reception circuit receives a second signal from the connection line, sets the signal line to a second state, and sets the microcomputer to a first state. Microcomputer system. 20. The microcomputer system, wherein a readable / writable recording medium is connected through an interface circuit connected to the bus, and the switch circuit is in a second state. The second state is established, and the switch circuit becomes the third state.
In this state, the microcomputer is in the third state. In response to the microcomputer being in the second state, the data transfer control unit requests the bus control unit to arbitrate for the bus right of the bus. And requesting the bus interface unit to separate the bus from the internal bus. After acquiring the bus right, the data transfer control unit transmits data received by the transmission / reception circuit from the connection line to the bus. The data transfer control unit stores the data in the storage medium and, if necessary, at a predetermined address of the storage circuit. In response to the microcomputer being in the third state, the data transfer control unit Requesting the bus control unit to arbitrate the bus right of the bus, requesting the bus interface unit to separate the bus from the internal bus, and acquiring the bus right; 20. The data transmission apparatus according to claim 19, wherein the data stored in the storage medium is transmitted from the transmission / reception circuit to the connection line using the bus, and is also stored in a predetermined address of the storage circuit. Microcomputer system.