JPH09297732A - Serial i/o - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a serial I/O which can make effective use of a circuit by properly allocating remaining buffers even when one or none of transmitting and receiving buffers is being used. SOLUTION: The serial I/O 50 has the transmitting and receiving buffers (B60-B63) 51-54. This serial I/O is equipped with a transmitting and receiving buffer controller (CON20) 56 which uniquelly allocates transmitting buffers and receiving buffers, by specifying the number of transmitting buffers and the number of receiving buffers, and the selectors (S40-S43) 55-19 which selects one of the transmitting and receiving buffers (B60-B63) 51-54, according to the allocation indication of the transmitting and receiving buffers (B60-B63) 51-54 made by the transmitting and receiving buffer controller (CON20) 56, and reads and writes the specific transmitting and receiving buffer, and the data set in the transmitting and receiving buffer controller (CON20) 56 are altered.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial I / O incorporated in a microcomputer, and more specifically, a serial I / O having a transmission / reception buffer is incorporated in a microcontroller or the like and is combined with another microcontroller or the like. The present invention relates to a serial I / O that serially transmits / receives data.

[0002]

2. Description of the Related Art A microcomputer incorporates various I / O as an interface for connecting peripheral devices for data input / output. The serial I / O is an interface that performs bit-serial transfer and is used for communication such as a keyboard, a printer, and RS-232C standard.

A conventional serial I / O having a plurality of transmission / reception buffers is built in a microcontroller or the like and transmits / receives data serially to / from another microcontroller or the like.

A conventional serial I / O having a plurality of transmission / reception buffers will be described with reference to FIGS.

FIG. 15 is a block diagram showing the configuration of a conventional serial I / O. The serial I / O transmits / receives data of a plurality of bits. Here, the description will be made with 8-bit data.

In FIG. 15, the serial I / O 10 is
Reception shift register (RSF1) 11, transmission shift register (TSF3) 12, reception buffer (B50, B51)
13, 14, transmission buffers (B52, B53) 15, 1
6, selectors (S41, S42, S43) 17, 18, 1
9, a reception buffer controller (CON21) 20 and a transmission buffer controller (CON22) 21.

The reception shift register (RSF1) 11
Shifts the serially transferred data and holds it as 8-bit data.

The transmission shift register (TSF3) 12
Is a register that shifts 8-bit transfer data bit by bit and transfers serially.

The receiving buffers (B50, B51) 13,
Reference numeral 14 is a receive data storage buffer in which the number of buffers can be set to one or two according to the setting of the microcontroller.

The transmission buffers (B52, B53) 15,
Reference numeral 16 is a transmission data storage buffer in which the number of buffers can be set to one or two according to the setting of the microcontroller.

The selector (S41) 17 selects the reception buffers (B50, B51) 13, 14 for storing the data to be output to the microcontroller.

The selector (S42) 18 selects the transmission buffers (B52, B53) 15, 16 for storing the transmission data input from the microcontroller.

The selector (S43) 19 selects the transmission buffers (B52, B53) 15, 16 for setting data in the transmission shift register (TSF3) 12.

The reception buffer controller (CON2)
1) 20 is for receiving the data received by the reception shift register (RSF1) 11 into a plurality of reception buffers (B50, B51) 1
3, 14 and receive shift register (RSF
1) The control for permitting the operation 11 is performed.

The transmission buffer controller (CON2)
2) 21 is a plurality of transmission buffers (B52, B53) 1
Transmission data to be set in the transmission shift register (TSF3) 12 from 5 and 16 is allocated, and control for permitting the operation of the transmission shift register (TSF3) 12 is performed.

Each circuit constituting the serial I / O 10 will be specifically described below. First, the reception shift register (RSF1) 11 will be described.

Serial reception data 10 as an input signal
1, the reception clock 102, the reception permission signal 103,
Reception data signal 104 and reception completion signal 1 as output signals
There is 05.

Serial reception data 101 represents a serial data input signal. Also, the reception clock signal 102
Indicates a serial reception clock signal, and the serial reception data 101 is sampled by this clock.

The reception permission signal 103 is a signal for permitting the serial reception operation. When it is "0", the reception operation is prohibited,
When it is “1”, it indicates that the receiving operation is permitted.

The received data signal 104 is used to output the value set by the receive shift register (RSF1) 11 to the receive buffers (B50, B51) 13, 14 (8).
It is a bit data signal.

The reception completion signal 105 is a reception completion signal indicating that 8-bit data has been set in the reception shift register (RSF1) 11.

The transmission shift register (TSF3) 12
Will be described.

There are transmission data 116, a transmission clock signal 115, and a transmission permission signal 117 as input signals, and a serial transmission data signal 114 and a transmission completion signal 118 as output signals.

The transmission data 116 represents an 8-bit data input signal. Further, the transmission clock signal 115 indicates a serial transmission clock signal, and outputs the transmission data 116 set by this clock. Further, the transmission permission signal 117 indicates a signal for permitting the serial transmission operation,
"0" indicates that the transmission operation is prohibited, and "1" indicates that the transmission operation is permitted.

Further, the serial transmission data signal 114 is
This is a signal for outputting the value set in the transmission shift register (TSF3) 12 as serial data.

The transmission completion signal 118 is a transmission completion signal indicating that 8-bit data has been set in the transmission shift register (TSF3) 12.

The reception buffer controller (CON2)
1) 20 will be described.

There are a reception completion signal 105, a read / write signal 106, a reception buffer controller select signal 1071, and a data signal 119 as input signals, and a reception permission signal 103, a select signal 1091, a reception data read request signal 110, and a reception signal as output signals. There are buffer write enable signals 1080 and 1081.

The reception completion signal 105 is a reception completion signal indicating that 8-bit data has been set in the reception shift register (RSF1) 11. Read / write signal 1
06 is a read / write signal from the microcontroller.

Receive buffer controller select signal 1
Reference numeral 071 indicates that the read / write signal 106 from the microcontroller is the reception buffer controller (CON21).
It is a signal indicating that 20 is valid. When this signal is valid and the read / write signal indicates write, the control data is set and the receiving operation is permitted.

The data signal 119 is a data signal for permitting the number of receiving buffers and receiving operation.

The reception permission signal 103 is a signal indicating that the reception operation is permitted, and has a circuit for holding this signal inside.

The select signal 1091 is a signal for selecting the reception buffers (B50, B51) 13 and 14 for setting the reception data. Β when it is “0” 50 Β when it is “1”
51 is shown.

The reception data read request signal 110 is a signal indicating that reception data has been set in the reception buffers 50-1. When this request is generated, a read request is generated from the microcontroller.

Receive buffer write enable signal 1080,
Reference numeral 1081 denotes a reception buffer for receiving data (B50, B5
1) A signal for permitting writing to 13 and 14. It becomes "1" when the reception shift register completes the reception.

The reception buffer controller (CON2)
1) The internal structure of 20 will be described in more detail with reference to FIG.

FIG. 16 is a diagram showing an internal configuration of the reception buffer controller (CON21) 20. In this figure, the reception buffer controller (CON21) 2 is shown.
0 is the receive buffer number setting register (SREG210) 3
0, receive buffer select controller (CON201)
31 and a reception permission register (SEREG 211) 32.

The reception buffer number setting register (SRE
G2 10) 30 is a register for setting the number of receiving buffers. Receive buffer number setting register (SREG210) 3
0 is set by the read / write signal 106, the reception buffer control select signal 1071, and the data signal 119. When it is "0", the number of reception buffers is 1, "1".
Indicates that the number of reception buffers is two.

The receive buffer select controller (CON201) 31 is a circuit for outputting a receive buffer write enable signal, and controls the receive buffer write enable signals 1081 and 1082 by setting the receive buffer number setting register (SREG210) 30. .

The reception permission register (SEREG211)
Reference numeral 32 is a register for controlling permission / prohibition of the reception operation.

The transmission buffer controller (CON2)
2) 21 will be described.

Returning to FIG. 15, there are a transmission completion signal 118, a read / write signal 106 and a transmission buffer controller select signal 1072 as input signals, and a transmission permission signal 117 and select signals 1092, 10 as output signals.
There is a transmission data write request signal 111.

The transmission completion signal 118 is a transmission completion signal indicating that 8-bit data has been set in the transmission shift register (TSF3) 12.

The read / write signal 106 is a read / write signal from the microcontroller.

Transmit buffer controller select signal 1
072 is a transmission buffer controller (CON22) for which the read / write signal 106 from the microcontroller is transmitted.
21 is a signal indicating that it is effective. When this signal is valid and the read / write signal 106 indicates a write, the control data is set and the transmission operation is permitted.

The transmission permission signal 117 indicates a signal for permitting the serial transmission operation. When it is "0", the transmission operation is prohibited,
When it is "1", it indicates that the transmission operation is permitted.

The select signal 1092 is a signal for selecting the transmission buffers (B52, B53) 15, 16 for setting the transmission data, and when it is "0", the transmission buffer (B5
2) 15, the transmission buffer (B53) 16 is shown when "1".

The select signal 1093 is set in the transmission shift register (TSF3) 12 in the transmission buffer (B5).
2, B53) 15 and 16 are selected. The signal indicates a transmission buffer (B52) 15 when "0" and a transmission buffer (B53) 16 when "1". The transmission data write request signal 111 is transmitted to the transmission buffers (B52, B53) 15, 16
This is a signal that requests the microcontroller to write transmission data.

The transmission buffer controller (CON2)
2) The internal structure of 21 will be described in more detail with reference to FIG.

FIG. 17 is a diagram showing the internal configuration of the transmission buffer controller (CON22) 21. In this figure, the transmission buffer controller (CON22) 2 is shown.
1 is a transmission buffer number setting register (TREG220) 4
0, transmission buffer select controller (CON202)
41 and a transmission permission register (TEREG2 21) 42.

The transmission buffer number setting register (TRE
G2 20) 40 is a register for setting the number of transmission buffers. Transmit buffer number setting register (TREG220) 4
0 is set by the read / write signal 106, the transmission buffer control select signal 1072, and the data signal 119. When it is "0", the number of transmission buffers is 1, "1".
Indicates that the number of transmission buffers is two.

The transmission buffer controller (CON2)
02) 41 is a circuit which outputs select signals 1092 and 1093, and is a transmission buffer number setting register (TREG2
20) Control the write enable signal of the transmission buffer by setting 40.

The transmission permission register (TEREG221)
Reference numeral 42 is a register for controlling permission / prohibition of the transmission operation.

Returning to FIG. 15, the reception buffer (B5
0, B51) 13, 14 will be described. The reception buffers (B50, B51) 13, 14 are 8-bit buffers. Received data signal 10 as input signal
4. There are write enable signals 1080 and 1081, but description of the input signals is omitted. Output signals include received data signals 1120 and 1121. Received data signal 1
120 and 1121 are reception buffer write enable signals 10
Received data signal 10 by inputting "1" of 80, 1081
Set the value of 4.

The transmission buffers (B52, B53) 15,
16 will be described.

Transmission buffers (B52, B53) 15, 16
Is an 8-bit buffer. A transmission data signal 1131 and write permission signals 1082 and 1083 as input signals
And there is a transmission data signal 1122, 11 as an output signal.
There are 23. The transmission data signals 1122 and 1123 set the value of the transmission data signal 1131 by inputting "1" of the write permission signals 1082 and 1083.

The selector (S41) 17 will be described.

Read / write signal 10 as an input signal
6, select signal 1091, data signals 1120 and 112
1 and the received data signal 1130 as an output signal.

The received data signal 1130 is received by the receive buffer (B50, B51) 13 by the select signal 1091 from the receive buffer controller (CON21) 20.
14 is selected and the received data is output to the microcontroller. Here, the value of the data signal 1120 is output when the select signal 1091 is "0", and the value of the data signal 1121 is output when the select signal 1091 is "1".

The selector (S42) 18 will be described.

Read / write signal 10 as an input signal
6, there are select signals 1092, and there are transmission buffer select signals 1082 and 1083 as output signals. The transmission buffer select signals 1082 and 1083 are write enable signals for the transmission buffers (B52, B53) 15 and 16.

The selector (S43) 19 will be described.

A transmission data signal 1122 as an input signal,
1123 and a select signal 1093, and a transmission data signal 116 as an output signal. Transmission data signal 116
Selects data from the transmission buffers (B52, B53) 15, 16 and outputs the value to the transmission shift register (TSF3) 12.

18 and 19 show the above serial I / O1.
18 is a timing chart of a signal of 0, FIG. 18 shows a timing chart at the time of reception of serial I / O, and FIG. 19 shows a timing chart at the time of transmission.

The operation during transmission / reception will be described below by taking the case where the number of transmission buffers is set to 2 bytes and the number of reception buffers is set to 2 bytes as an example.

First, the operation at the time of reception will be described with reference to FIG.

Receive buffer controller select signal 1
From 071 and the read / write signal 106, the value of the reception permission register (SEREG211) 32 in the reception buffer controller (CON21) 20 is set to "1".
As a result, “1” is output to the reception operation permission signal 103.

Serial reception data 101 is sampled at the rising edge of the reception clock 102, and 8-bit reception data is set in the reception shift register (RSF1) 11.

When the reception completion signal 105 output from the reception shift register (RSF1) 11 is set to "1", the reception buffer controller (CON21) 2
The write enable signal 1080 of the receive buffer (B50) 13 from 0 is set to "1". As a result, the reception shift register (RSF1) is stored in the reception buffer (B50) 13.
11-bit 8-bit data "Ah" is set and the received data read request signal 110 is set to "1".

The serial reception data 101 is sampled at the next rise of the reception clock 102, and the 8-bit reception data is set in the reception shift register (RSF1) 11. When the reception completion signal 105 from the reception shift register (RSF1) 11 is set to "1", the write enable signal 10 of the reception buffer controller (CON21) 20 to the reception buffer (B51) 14 is set.
81 is set to "1".

As a result, the 8-bit data "Bh" of the reception shift register (RSF1) 11 is set in the reception buffer (B51) 14, and the reception data read request signal 1
10 is set to "1".

When the number of reception buffers is set to 1 byte, only the reception buffer (B50) 13 is operated and the reception buffer (B51) 14 is unused. Therefore, the received data is set only in the reception buffer (B50) 13.

Next, the operation during transmission will be described with reference to FIG.

Transmit buffer controller select signal 1
072, the read / write signal 106, and the transmission buffer select signal 1092, the value of the transmission data 1131 is "AA".
"h" is written in the transmission buffer (B52) 15. The data is set in the transmission buffer (B52) 15 so that the transmission shift register (TSF3) 12 receives the selection signal 1093 from the transmission buffer controller (CON22) 21. (B52) Value of 15 "A
Ah "is set.

The value set in the transmission shift register (TSF3) 12 is synchronized with the transmission clock 115, and 8-bit transmission data is output as serial transmission data 114.

Next, when the transmission buffer controller select signal 1072 is set to "1" and the read / write signal 106 is set to "0", the transmission buffer select signal 1 is set.
092 is output and the transmission buffer write enable signal 10
8 3 is set to “1”.

As a result, the value “ΒΒ” of the transmission data 1131 is
h ”is written in the transmission buffer (B53) 16. When data is set in the transmission buffer (B53) 16, a transmission shift register (TS) is transmitted by the select signal 109 from the transmission buffer controller (CON22) 21.
F3) The value of the transmission buffer (B53) 16 is "BBh" in 12
Is set.

The value set in the transmission shift register (TSF3) 12 is synchronized with the transmission clock 115, and 8-bit transmission data is output from 114.

When the number of transmission buffers is set to 1 byte, only the transmission buffer (B52) 15 is operated and the transmission buffer (B53) 16 is unused. Therefore,
The transmitted data is set only in the transmission buffer (B52) 15.

[0080]

However, such conventional serial I / O data transfer has the following problems.

That is, the receiving buffer (B50, B51)
13, 14 and transmission buffers (B52, B53) 15, 16
Is fixedly allocated, the circuit is not effectively used because one transmission buffer is used or the remaining transmission buffers are unused. Similarly, the reception buffers (B50, B51) 13, 14 and the transmission buffers (B52,
B53) Since 15 and 16 are fixedly allocated,
When one reception buffer is used or the remaining buffers are unused, the circuit is not effectively used.

An object of the present invention is to provide a serial I / O capable of effectively allocating the remaining buffer even when one transmitting / receiving buffer is not used or allocating the remaining buffer. .

[0083]

A serial I according to the present invention.
/ O is a serial I / O having a plurality of transmission / reception buffers
A plurality of transmission buffers and reception buffers to be used by designating at least one of the number of reception buffers or the number of transmission buffers, and a plurality of transmission buffers based on a transmission / reception buffer allocation instruction from the control means. And a selecting means for selecting a predetermined transmission / reception buffer from the transmission / reception buffer and reading / writing the selected transmission / reception buffer.

The control means may control one transmission buffer or allocate the remaining buffer as a reception buffer when it is not used, and the control means controls one reception buffer or when it is not used. The remaining buffer may be controlled to be allocated as a transmission buffer.

Further, the selecting means may be configured to select one from a plurality of transmission / reception buffers in accordance with an allocation instruction from the control means, and read / write to a predetermined transmission / reception buffer.

Further, the serial I / O is provided with an interrupting means for outputting a read request of received data, and the interrupting means receives the received data after receiving the designated number of reception buffers or every reception of one byte. The interrupt means may be configured to output a read request, and the interrupt means may be configured to output a received data read request in units of the number of receiving buffers or in units of 1 byte when the number of receiving buffers is changed. It may be.

Further, the control means comprises setting means capable of setting the number of reception buffers and the number of transmission buffers, respectively, and the setting means designates the number of reception buffers and the number of transmission buffers respectively, and sets the transmission and reception buffers not designated. The operation may be stopped, and the transmission / reception buffer may be a buffer that can be used as either the reception buffer or the transmission buffer depending on the input state of data.

[0088]

BEST MODE FOR CARRYING OUT THE INVENTION A serial I / O according to the present invention is
It can be applied to serial I / O such as a microcomputer.

FIG. 1 is a block diagram of a serial I / O according to the first embodiment of the present invention. The serial I / O according to this embodiment is a serial I / O having a plurality of transmission / reception buffers.
Is effective, but here, the case of four transmission / reception buffers will be described.

In the explanation of FIG. 1, the same components and the same signal portions as those in FIG. 15 are designated by the same reference numerals.

In FIG. 1, the serial I / O 50 includes a reception shift register (RSF1) 11, a transmission shift register (TSF3) 12, a transmission / reception buffer (B60, B61,
B62, B63) 51, 52, 53, 54, selector (S
40, S41, S42, S43) 55, 17, 18, 19
(Selection means) and transmission / reception buffer controller (CON
20) 56 (control means).

That is, the serial I / O according to this embodiment is
O50 is the conventional serial I / O 10 shown in FIG.
Instead of the reception buffer controller (CON21) 20 and the transmission buffer controller (CON22) 21 of
A transmission / reception buffer controller (CON20) 56 is installed, and reception buffers (B50, B51) 13, 14 and transmission buffers (B52, B53) 15, 16 are transmission / reception buffers (B60, B61, B62, B63) 51, 52, 53,
54, and a selector (S40) 55 is newly added.

The transmission / reception buffer controller (CON
20) 56 will be described.

The reception completion signal 105, the read / write signal 106, the transmission / reception buffer controller select signals 1070-1, the transmission completion signal 117, and the control data signal 119 as input signals are the same as in FIG.

The output signals are as follows. Reception permission signal 103, transmission permission signal 118, reception data read request signal 110, transmission data write request signal 111 ,. There are transmission / reception buffer write enable signals 1080 to 1083, reception data select signals 1090 to 1093, and transmission data select signals 1094 to 1097. Of these, the reception permission signal 103, the transmission permission signal 118, the reception data read request signal 110, and the transmission data write request signal 111 are the same as those in FIG. Here, transmission / reception buffer write enable signals 1080 to 1083, reception data select signals 1090 to 1093, and transmission data select signal 10
94 to 1097 will be described.

Transmit / receive buffer write enable signal 1080
-1083 is a transmission / reception buffer (B60-
B63) This is a signal for permitting writing to 51 to 54.

Received data select signals 1090-1093
Is a transmission / reception buffer (B60-
B63) This signal selects 51 to 54.

Transmission data select signals 1094 to 1097
Is a transmission / reception buffer (B60-
B63) This signal selects 51 to 54.

The transmission / reception buffer controller (CON
The internal structure of 20) 56 will be described in more detail with reference to FIG.

FIG. 2 is a diagram showing the internal structure of the transmission / reception buffer controller (CON20) 56. In this figure, the transmission / reception buffer controller (CON20) is shown.
56 is a transmission / reception buffer number setting register (ΤSREG2
05) 60, receive buffer controller (CON201) 6
1, transmission buffer controller (CON202) 62, transmission / reception buffer write enable controller (CON203)
63 and a transmission / reception permission register (TSEREG 206) 64.

The transmission / reception buffer number setting register (ΤS
REG205) 60 is a register for setting the number of transmission / reception buffers, and the values of the read / write signal 106, the transmission buffer controller select signal 1071, the reception buffer controller select signal 1070, and the control data signal 119 are set, and the reception buffer controller (CON201) 61 reception buffer number data signal 1
190, the transmission buffer number data signal 1191 is output to the transmission buffer controller. In this case, the number of transmission buffers is automatically determined by determining the number of reception buffers. This transmission / reception buffer number setting register (ΤS
The operating states of the REG 205) 60 are shown in Table 1 of FIG.

Reception buffer controller (CON201)
61 is a reception buffer write enable signal 108R0-10
This is a circuit that outputs 8R3. The write enable signal of the reception transmission / reception buffers (B60 to B63) 51 to 54 is controlled by the setting of the transmission / reception buffer number setting register (T SREG205) 60. This receive buffer controller (CO
The operating state of N201) 61 is shown in Table 2 of FIG.

Transmission buffer controller (CON202)
62 is a transmission buffer write enable signal 108T0 to 10
This is a circuit that outputs 8T3. The write enable signal of the reception transmission / reception buffers (B60 to B63) 51 to 54 is controlled by the setting of the transmission / reception buffer number setting register (T SREG205) 60. This receive buffer controller (CO
The operating state of N201) 61 is shown in Table 3 of FIG.

The transmission / reception buffer write permission controller (CON203) 63 is a circuit for outputting the transmission / reception buffer write permission signals 1080-1083, and transmits the reception buffer write permission signals 108R0-108R3 input from the reception buffer controller (CON201) 61. The transmission / reception buffer write permission signals 1080-1083 are controlled by taking an OR logic with the transmission buffer write permission signals 108T0-108T3 input from the buffer controller (CON202) 62.

Transmission / reception permission register (TSEREG206)
Reference numeral 64 is a control register that outputs the transmission permission signal 118 and the reception permission signal 103.

The selector (S40) 55 newly installed in the serial I / O 50 according to this embodiment will be described.

Returning to FIG. 1, there are received data signal 104 and select signals 1090 to 1093 as input signals, and buffer set data signals 1140 to 1110 as output signals.
There are 43. Buffer set data signal 1140 to 114
3 is a buffer set data signal 1140 to 1400 to receive data 104 according to the received data selection signals 1090 to 1093 from the transmission / reception buffer controller (CON20) 56.
One of 1143 is selected and output.

The selector (S41) 17 will be described.

A transmission data signal 1130 as an input signal,
There are select signals 1094 to 1097, and buffer set data signals 1140 to 1143 are output signals. The buffer set data signal 1140 to 1143 is one of the buffer set data signals 1140 to 1143 which is the transmission data 1130 according to the transmission data selection signal 1094 to 7 from the transmission / reception buffer controller (CON20) 56.
Select one and output.

The selector (S42) 18 will be described.

Data signals 1120-11 as input signals
23, select signals 1090 to 1093, and received data 1131 as an output signal. Received data signal 11
31 outputs one value out of the data signals 1120 to 1123 from the transmission / reception buffers (B60 to B63) 51 to 54 to the microcontroller by the received data select signals 1090 to 1093.

The selector (S43) 19 will be described.

Data signals 1120-11 as input signals
23, select signals 1094 to 1097, and a transmission data signal 116 as an output signal. Transmission data signal 1
16 outputs one value out of the data signals 1120 to 1123 from the transmission / reception buffers (B60 to B63) 51 to 54 to the transmission shift register (TSF3) 12 by the transmission data select signals 1094 to 1097.

As described above, the serial I according to this embodiment is
/ O50 is a plurality of transmission / reception buffers (B60 to B63) 5
A transmission / reception buffer controller (CON20) 56 which is a serial I / O having 1 to 54 and which uniquely allocates the number of transmission buffers and the number of reception buffers to be used by designating the number of reception buffers or the number of transmission buffers,
Based on the allocation instruction of the transmission / reception buffers (B60 to B63) 51 to 54 by the transmission / reception buffer controller (CON20) 56, a plurality of transmission / reception buffers (B60 to B6)
3) Selector (S40 to S) that selects one from 51 to 54 and performs read / write to a predetermined transmission / reception buffer.
43) 55 and 17 to 19 are provided.

Hereinafter, the serial I configured as described above will be described.
The operation of / O50 will be described.

6 and 7 are timing charts of the serial I / O 50, in which FIG. 6 shows three transmission buffers,
FIG. 7 is a timing chart showing the operation when the number of reception buffers is set to 1, and FIG. 7 is a timing chart showing the operation when the number of transmission buffers is set to 1 and the number of reception buffers is set to 3.

First, referring to FIG. 6, the number of transmission buffers is 3
The operation when the number is set to one and the number of reception buffers is set to one will be described.

As described above, the transmission / reception buffer controller (CON20) 56 transmission / reception buffer number setting register TSREG (T SREG205) 60 has the control data signal 119, reception buffer controller select signal 1070, transmission buffer controller select signal 1071 and read / write. The write signal 106 is input,
Transmission / reception buffer count setting register TSREG (ΤSREG
205) 60 is a transmission / reception buffer number setting register TSREG (ΤSREG 205) 6 according to the reception buffer controller select signal 1070, the transmission buffer controller select signal 1071 and the read / write signal 106.
The data "01" of the control data signal 119
h ”is held. In this case, the number of receive buffers is 1 and the number of send buffers is 3.

At the same time, the transmission buffer write enable signal 10
"1" (write enable) is output to 8T3, and "0" is output to the receive buffer write enable signal 108R3. As a result, the transmission / reception buffers (B60 to B63) 51 to
The transmission / reception buffer write enable signal 1083 of 54 is set to "1", and the transmission data select signal 1097
Is set to "1". As a result, the transmission data 113
0 is set in the transmission / reception buffer (B63) 54 by the buffer data set signal 1143.

After the transmission is completed, the transmission buffer controller select signal 1071 and the read / write signal 106 are transmitted.
Is asserted, the transmit buffer write enable signal 1
"1" (write enable) is output to 08T2, and "0" is output to the receive buffer write enable signal 108R2.
As a result, the transmission / reception buffer write enable signal 1082 of the transmission / reception buffer B52 is set to "1".

As a result, the transmission data 1130 is transmitted / received by the buffer data set signal 1142 to the transmission / reception buffer (B
62) Set to 53 and send data select signal 10
96 is set to "1".

As described above, every time the transmission buffer controller select signal 1071 and the read / write signal 106 are asserted, the transmission buffer write enable signal 10 is sent.
8T3 → 108T2 → 108T1 are sequentially asserted (at this time, the reception buffer write enable signals 108R1 to 108R3
Outputs “0”. ), The transmit / receive buffer write enable signal 1083 → 1082 → 1081 → 1083, and the transmit data select signal 1097 → 1096 → 1095 → 1097 are asserted in this order, and the transmit data 1130 is set in the transmit / receive buffers (B60 to B63) 51 to 54. .

Each time the reception completion signal 105 is set to "1", "0" (write enable) is output to the transmission buffer write enable signal 108T0 and "1" is output to the receive buffer write enable signal 108R0. It As a result, the transmission / reception buffer write enable signal 1080 is set to "1" and the reception data select signal 1090 is set.
Is set to "1". As a result, the serial reception data 104 is set in the transmission / reception buffer (B 60) 51 from the buffer data set signal 1140.

Next, referring to FIG. 7, the number of transmission buffers is 1
The operation when the number is set to 3 and the number of reception buffers is set to 3 will be described.

Receive buffer controller select signal 1
07, transmission buffer controller select signal 1071
Further, the read / write signal 106 holds the data “03h” of the control data signal 119 in the transmission / reception buffer number setting register TSREG (ΤSREG 205) 60. In this case, three reception buffers and one transmission buffer are held. At the same time, "1" (write enable) is output to the transmit buffer write enable signal 108T3, and "0" is output to the receive buffer write enable signal 108R3. As a result, the transmission / reception buffer (B63) 54
The transmission / reception buffer write enable signal 1083 is set to "1", and the transmission data select signal 1097 is set to "1".
Is set to As a result, the transmission data 1130 is set in the transmission / reception buffer (B63) 54 by the buffer data set signal 1143.

Thereafter, every time the transmit buffer controller select signal 1071 and the read / write signal 106 are asserted, "1" (write enable) is output to the transmit buffer write enable signal 108T3 and "0" is output to the receive buffer write enable signal 108R3. Is output. As a result, the transmission / reception buffer write enable signal 1083 is set to "1", and the transmission data 1130 is transmitted / received to the transmission / reception buffer (B6 by the buffer data set signal 1143).
3) Set to 54.

When the reception completion signal 105 is set to "1", the transmission buffer write enable signal 108T0
"0" (write inhibit) is output to, the receive buffer write enable signal 108R0 is output to "1", and the receive data select signal 1090 is set to "1". As a result, the serial transmission data 104 is transferred to the transmission / reception buffer (B 60) 51 according to the buffer data set signal 1140.
Is set to

Thereafter, every time the reception completion signal 105 is set to "1", the reception buffer write enable signal 108R0 →
108R1 → 108R2 are sequentially asserted (at this time, the transmission buffer write enable signals 108T0 to 108T2 are "0").
Is output. ), Transmit / receive buffer write enable signal 10
80 → 1081 → 1082 → 1080, reception data select signal 1090 → 1091 → 1092 → 1090 are asserted in this order, and serial reception data 104 is transmitted / received by the buffer data set signals 1140 to 1143.
60 to B62) are set to 51 to 53.

In the above description, the number of transmission buffers is uniquely determined by setting the number of reception buffers. However, the number of reception buffers may be uniquely determined by setting the number of transmission buffers. It is possible.

As described above, the serial I / O 50 according to the first embodiment has the transmission / reception buffers (B60 to B60).
63) A transmission / reception buffer controller (CON20) which is a serial I / O having 51 to 54 and which uniquely allocates the number of transmission buffers to be used and the number of reception buffers by designating the number of reception buffers or the number of transmission buffers
56 and a transmission / reception buffer controller (CON20) 5
Based on the allocation instruction of the transmission / reception buffers (B60 to B63) 51 to 54 according to No. 6, a plurality of transmission / reception buffers (B6
0 to B63) Select one from 51 to 54 to read / write to a predetermined transmission / reception buffer (S4)
0 to S43) 55 and 17 to 19 so that the data set in the transmission / reception buffer controller (CON20) 56 is changed, the number of buffers allocated to transmission or reception can be changed in a programmable manner.
One transmission buffer or the remaining buffer can be allocated to the reception buffer when unused, and the remaining buffer can be assigned to the transmission buffer when one reception buffer or the unused buffer is used effectively. be able to.

FIG. 8 is a block diagram showing the configuration of a serial I / O according to the second embodiment of the present invention. The serial I / O according to this embodiment is also a serial I / O having a plurality of transmission / reception buffers. Is effective, but here, the case of four transmission / reception buffers will be described. In the description of the serial I / O according to the present embodiment, the same components as those of the serial I / O shown in FIG. 1 will be assigned the same reference numerals and overlapping description will be omitted.

In FIG. 8, the serial I / O 70 includes a reception shift register (RSF1) 11, a transmission shift register (RSF3) 12, a transmission / reception buffer (B60, B61,
B62, B63) 51, 52, 53, 54, selector (S
40, S41, S42, S43) 55, 17, 18, 19 and a transmission / reception buffer controller (CON20) 71.

That is, the serial I / O according to this embodiment is
O70 is a transmission / reception buffer controller (CON20)
An interrupt controller (CON204) 72 inside 71
Has been incorporated.

FIG. 9 shows a transmission / reception buffer controller (CON20) 71 incorporating the above interrupt controller.
2 is a diagram showing the internal configuration of a transmission / reception buffer controller (CON20) 71, a transmission / reception buffer number setting register (T SREG205) 60, a reception buffer controller (CON201) 61, a transmission buffer controller (CON202) 62, and a transmission / reception buffer. It is composed of a write enable controller (CON203) 63, a transmission / reception enable register (TSEREG206) 64, and an interrupt controller (CON204) 72.

The interrupt controller (CON204)
A circuit 72 controls the output timing of the received data read request signal 110. Reception completion signal 105 and reception buffer number data signal 119 as input signals
0, there is a reception data read request control signal 120, and the reception data read request control signal 120 is a signal for controlling the reception data read request signal 110.

Further, there is a received data read request signal 110 as an output signal, and the received data read request signal 110
Is a signal requesting the microcontroller to read the received data. Received data read request signal 11
For 0, the received data read request control signal 120 is "1".
In the case of (fixed release of received data read request), when the reception completion signal 105 is asserted (“1” is input) for the set number of reception buffers, “1” is output to the received data read request signal 110. Received data read request control signal 12
When 0 is “0” (fixed reception data read request), “1” is output to the reception data read request signal 110 each time the reception completion signal 105 is asserted (“1” is input).

Hereinafter, the serial I configured as above will be described.
The operation of / O70 will be described.

FIG. 10 and FIG. 11 The above serial I / O70
The serial I / O 70 controls the received data read request signal by the operation shown in FIGS. 10 and 11. The other operations are the same as those in the first embodiment.

FIG. 10 is a timing chart showing the operation when the received read data request is fixed at every 1 byte.

As shown in FIG. 10, the reception buffer controller select signal 1071 and the read / write signal 10
Transmission / reception permission register (TSEREG206) 64 by 6
Is set to "1". As a result, "1" is output to the reception operation permission signal 103, and the reception operation is started. After receiving 8-bit data, “1” is set by the reception completion signal 105 of the reception shift register (RSF1) 11.
Is output. "1" (reception data read request) is output as the reception data read request signal 110 according to the states of the reception completion signal 105 "1" and the reception data read request control signal 120 "0".

Thereafter, every time "1" is output to the reception completion signal, "1" is output from the reception data read request signal 110.

FIG. 11 is a timing chart showing the operation when the reception read data request is released from the fixed state and operated every 3 bytes.

As shown in FIG. 11, the reception buffer controller select signal 1071 and the read / write signal 10
Transmission / reception permission register (TSEREG206) 64 from 6
Is set to "1". As a result, "1" is output to the reception operation permission signal 103, and the reception operation is started.

After receiving the 8-bit data, "1" is output from the reception completion signal 105 of the reception shift register (RSF1) 11. "0" (no reception data read request) is output as the reception data read request signal 110 according to the state of the reception completion signal 105 "1", reception data read request control signal 120 "1" reception buffer number data signal 1190 "3" It

Thereafter, when "1" is output twice as the reception completion signal, "1" is output from the reception data read request signal 110.

Thereafter, every time "1" is output to the reception completion signal three times, "1" is output from the reception data read request signal 110.

As described above, the serial I / O 70 according to the second embodiment has the interrupt controller (C) inside the transmission / reception buffer controller (CON20) 71.
ON204) 72, and an interrupt controller (CON
04) 72 outputs the reception data read request after receiving the specified number of reception buffers or every 1-byte reception. Therefore, the reception data read request output when the number of reception buffers is changed By switching to the unit of the number of receiving buffers or the unit of 1 byte, the processing for reading / writing the transmission / reception data can be collectively performed, and the processing of the microcontroller can be reduced.

FIG. 12 is a serial I / O transmission / reception buffer controller (CON2) according to the third embodiment of the present invention.
It is a figure which shows the internal structure of 0) 80. In the description of the serial I / O according to the present embodiment, the same components as those of the serial I / O shown in FIG. 9 will be assigned the same reference numerals and overlapping description will be omitted.

In FIG. 12, a transmission / reception buffer controller (CON20) 80 includes a reception buffer number setting register (SREG210) 81, a transmission buffer number setting register (TREG220) 82, and a reception buffer controller (C).
ON201) 61, transmission buffer controller (CON2
02) 62, transmission / reception buffer write permission controller (CON203) 63, transmission / reception permission register (TSERE
G206) 64 and interrupt controller (CON204)
It is composed of 72.

That is, the transmission / reception buffer controller (CON20) 80 according to the present embodiment is replaced with the transmission / reception buffer number setting register (ΤSREG205) 60, and the reception buffer number setting register (SREG210) 81 and the transmission buffer number setting register (ΤREG220). The number of buffers for transmission and reception can be independently set by adding this circuit.

The reception buffer number setting register (SRE
G 210) 81 is a transmission / reception buffer (B 60 to B 62) 51
It is a register for setting the number of buffers to be allocated to reception out of 53.

Read / write signal 10 as an input signal
6, receive buffer controller select signal 1070,
There is a data signal 119. Further, there is a reception buffer number data signal 1190 as an output signal, and the reception buffer number data signal 1190 is a transmission / reception buffer (B60 to B62).
It is a signal that outputs the number of 51 to 53 to be assigned to the reception buffer. This receive buffer number setting register (SR
The operating state of the EG 210) 81 is shown in Table 4 of FIG.

The transmission buffer number setting register (ΤRE
G 220) 82 is a transmission / reception buffer (B 60 to B 62) 51
It is a register for setting the number of buffers to be allocated to transmission out of 53.

Read / write signal 10 as an input signal
6, transmission buffer controller select signal 1071,
There is a control data signal 119. Further, there is a transmission buffer number data signal 1191 as an output signal, and the transmission buffer number data signal 1191 is transmitted and received by the transmission / reception buffer (B
60 to B62) A signal for outputting the number of 51 to 53 to be assigned to the transmission buffer. The operating state of the transmission buffer number setting register (TREG220) 82 is shown in Table 4 of FIG.

Hereinafter, the serial I constructed as described above will be described.
The operation of / O will be described.

FIG. 14 is a timing chart of the serial I / O and is a timing chart showing the operation when changing the settings of the number of transmission buffers and the number of reception buffers.

As shown in FIG. 14, when the value "1" of the reception buffer controller select signal 1070, the value "1" of the transmission buffer controller select signal 1071 and the read / write signal 106 are "0", the number of reception buffers is set. The data "03h" of the control data signal 119 is set in the register (SREG210) 81, and the number of receiving buffers becomes three.

At the same time, the transmission buffer number setting register (Τ
The data "03h" of the control data signal 119 is set in the REG 220) 82, and the number of transmission buffers becomes one. Here, since the number of transmission / reception buffers is 4, the number of transmission buffers is the number obtained by subtracting 4 from the number of control data (see FIG. 14 (1)).

Further, the value "1" of the reception buffer controller select signal 1070, the value "0" of the transmission buffer controller select signal 1071 and the read / write signal 1
When it is 06 “0”, the number of receiving buffer setting register (SR
The data "01h" of the control data signal 119 is set in the EG 210) 81, and the number of receiving buffers becomes one.

At this time, the control data signal 119 is sent to the transmission buffer number setting register (ΤREG 220) 82.
The data "01h" is not set, and the number of transmission buffers continues to be 1 (see FIG. 14 (2)).

Receive buffer controller select signal 1
When the value of 070 is "0", the value of the transmission buffer controller select signal 1071 is "1", and the read / write signal 106 is "0", the reception buffer number setting register (ΤSRE
The data "02h" of the control data signal 119 is not set in the G210) 81, and the number of receiving buffers continues to be one. Also, the transmission buffer number setting register (TR
The data "02h" of the control data signal 119 is set in the EG 220) 82, and the number of transmission buffers becomes two (see FIG. 14 (3)).

Receive buffer controller select signal 1
When the value of 070 is "0", the value of the transmit buffer controller select signal 1071 is "0", and the read / write signal 106 is "0", the receive buffer number setting register (SREG
The data "00h" of the control data signal 119 is not set in 210) 81, and the number of receiving buffers continues to be one. Also, the transmission buffer number setting register (TR
The data “00h” of the control data signal 119 is not set in the EG 220) 82, and the number of transmission buffers continues to be 2 (see FIG. 14 (4)).

As described above, the serial I / O according to the third embodiment has the transmission / reception buffer controller (C
ON20) 80 is the receiving buffer number setting register (SR
EG210) 81 and transmission buffer number setting register (ΤR
EG 220) 82 is added, and the reception buffer number setting register (SREG 210) 81 and the transmission buffer number setting register (ΤREG 220) 82 specify the reception buffer number and the transmission buffer number, respectively, and stop the operation of the transmission and reception buffers not specified. Since the number of receiving buffers and the number of transmitting buffers can be individually set, the system can be constructed with the number of buffers suitable for the system.

The serial I / O according to each of the above embodiments is
The O can be applied to a serial I / O of a microcomputer or the like, but any serial I / O having a plurality of transmission / reception buffers can be used and is a part of a circuit incorporated in the microcomputer. Good. It goes without saying that the same can be applied to devices other than the four transmission / reception buffers.

Further, it goes without saying that the number of controllers and various circuits constituting the serial I / O, the type connection state, etc. are not limited to those in the above-mentioned respective embodiments.

[0166]

The serial I / O according to the present invention is a serial I / O having a plurality of transmission / reception buffers and at least one of the number of reception buffers or the number of transmission buffers.
Control means for allocating the number of transmission buffers and the number of reception buffers to be used by designating one of them, and selecting a predetermined transmission / reception buffer from among the plurality of transmission / reception buffers based on an instruction to allocate transmission / reception buffers by the control means. Since the transmission / reception buffer is configured to include a selection unit for reading / writing the transmission / reception buffer, one transmission buffer or the remaining buffer can be allocated to the reception buffer when not in use, and one reception buffer or When not in use, the remaining buffer can be allocated to the transmission buffer, and the circuit can be effectively used.

In the serial I / O according to the present invention,
Since the interrupt means is configured to output a read request for receiving data, and the interrupt means is configured to output the receive data read request after receiving the designated number of reception buffers or each time one byte is received. The processing for reading / writing the transmission / reception data can be collectively performed, and the processing of the microcontroller can be reduced.

Further, the serial I / O according to the present invention is provided with setting means capable of setting the number of receiving buffers and the number of transmitting buffers, respectively, and the setting means designates the number of receiving buffers and the number of transmitting buffers respectively. Since it is configured to stop the operation of the transmission / reception buffers that are not stored, the number of reception buffers and the number of transmission buffers can be individually set, and the system can be constructed with the number of buffers suitable for the system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a serial I / O according to a first embodiment to which the present invention is applied.

FIG. 2 is a diagram showing an internal configuration of a transmission / reception buffer controller of the serial I / O.

FIG. 3 is a diagram for explaining an operation of the transmission / reception buffer number setting register of the serial I / O.

FIG. 4 is a diagram for explaining the operation of the serial I / O reception buffer controller.

FIG. 5 is a diagram for explaining the operation of the serial I / O transmission buffer controller.

FIG. 6 is a timing chart showing the operation when the number of serial I / O transmission buffers is set to 3 and the number of reception buffers is set to 1;

FIG. 7 is a timing chart showing the operation when the number of serial I / O transmission buffers is set to 1 and the number of reception buffers is set to 3;

FIG. 8 is a block diagram showing a configuration of a serial I / O according to a second embodiment to which the present invention is applied.

FIG. 9 is a diagram showing an internal configuration of the transmission / reception buffer controller of the serial I / O.

FIG. 10 is a timing chart showing the operation when the received read data request of the serial I / O is fixedly operated for each byte.

FIG. 11 is a timing chart showing an operation when the reception read data request of the serial I / O is released from fixed state and operated every 3 bytes.

FIG. 12 is a diagram showing an internal configuration of a serial I / O according to a third embodiment of the present invention.

FIG. 13 is a diagram for explaining the operation of the serial I / O transmission / reception buffer number setting register.

FIG. 14 is a timing chart showing an operation when changing the settings of the number of transmission buffers and the number of reception buffers of the serial I / O.

FIG. 15 is a block diagram showing a configuration of a conventional serial I / O.

FIG. 16 is a diagram showing an internal configuration of a conventional serial I / O receive buffer controller.

FIG. 17 is a diagram showing an internal configuration of a conventional serial I / O transmission buffer controller.

FIG. 18 is a timing chart showing an operation at the time of receiving a conventional serial I / O.

FIG. 19 is a timing chart showing an operation at the time of receiving a conventional serial I / O.

[Explanation of symbols]

50,70 serial I / O, 11 reception shift register (RSF1), 12 transmission shift register (TSF
3), 51, 52, 53, 54 Transmission / reception buffer (B6
0, B61, B62, B63), 55, 17, 18, 19
Selectors (S40, S41, S42, S43) (selection means), 56, 71 transmission / reception buffer controller (CO
N20) (control means), 60 transmission / reception buffer number setting register (T SREG205), 61 reception buffer controller (CON201), 62 transmission buffer controller (CON202), 63 transmission / reception buffer write enable controller (CON203), 64 transmission / reception enable register (TSEREG206) , 72 interrupt controller (CON204), 81 reception buffer number setting register (SREG210), 82 transmission buffer number setting register (ΤREG220)

Claims (8)

[Claims] 1. A serial I / O having a plurality of transmission / reception buffers, wherein control means for allocating the number of transmission buffers and the number of reception buffers to be used by designating at least one of the number of reception buffers or the number of transmission buffers. And a selection means for selecting a predetermined transmission / reception buffer from a plurality of transmission / reception buffers based on an instruction to allocate the transmission / reception buffer by the control means, and for performing read / write to the selected transmission / reception buffer. Characteristic serial I / O. 2. The serial I / O according to claim 1, wherein the control means controls one transmission buffer or allocates the remaining buffer as a reception buffer when it is unused. 3. The serial I / O according to claim 1, wherein the control means controls so as to allocate one reception buffer or the remaining buffer as a transmission buffer when it is unused. 4. The selection means is configured to select one from a plurality of transmission / reception buffers in accordance with an allocation instruction from the control means, and to perform read / write to a predetermined transmission / reception buffer. The serial I / O according to claim 1. 5. The serial I according to claim 1 above.
/ O, an interrupt means for outputting a read request of received data is provided, and the interrupt means outputs a received data read request after receiving the designated number of reception buffers or every 1-byte reception. The serial I / O according to claim 1, wherein the serial I / O is configured. 6. The serial device according to claim 5, wherein the interrupt means is configured to output a received data read request in units of the number of receiving buffers or in units of 1 byte when the number of receiving buffers is changed. I / O. 7. The control means includes setting means capable of setting the number of reception buffers and the number of transmission buffers respectively, and the setting means specifies the number of reception buffers and the number of transmission buffers respectively, and the transmission / reception not designated. 2. The operation of the buffer is stopped.
The serial I / O described in either 2 or 3. 8. The transmission / reception buffer is configured as a buffer that can be used as either a reception buffer or a transmission buffer depending on a data input state. Serial I / O as described.