JPH05143364A - Interruption control device - Google Patents

Abstract

PURPOSE:To obtain an interruption control device capable of receiving an inter ruption request from a peripheral circuit at approximately equal probability and eliminating necessity for developing a program for controlling priority order in respect of an interruption control device for receiving plural interruptions generated at random at the approximately equal probability. CONSTITUTION:The subject interruption control device is constituted of a select signal forming means 10 for forming a select signal A having a pattern to be changed at a prescribed time interval and circularly returned to the initial pattern at the time of arriving at a prescribed pattern, and a selection means 11 having input parts 10 to In for interruption request signals RQ0 to RQn corresponding to respective patterns of the signal A formed by the means 10 and selecting and outputting one of the signals RQ0 to RQn inputted to the input parts 10 to In in accordance with each pattern of the signal A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control device that accepts a plurality of interrupts that occur randomly with a substantially equal probability.

In recent years, various control devices are often constructed using a microprocessor and its peripheral circuits. In such a control device, an interrupt function is often used in order to smoothly and efficiently transmit and receive information between the microprocessor and peripheral circuits.

However, when interrupt requests are randomly generated from a plurality of peripheral circuits, the accepted interrupt requests are biased to predetermined peripheral circuits, and the system may not operate normally. Therefore, when a system is constructed by connecting a plurality of peripheral circuits to a microprocessor, it is desired that the interrupt requests from each peripheral circuit be accepted with equal probability.

[0004]

2. Description of the Related Art Conventionally, as shown in FIG. 5, in order to receive interrupt request signals RQ0 to RQ3 from a plurality of peripheral circuits and pass control to a processor (CPU) 51, for example, an LS.
A general-purpose interrupt controller 50 composed of I is used.

The interrupt controller 50 has a memory for storing programs therein, and the priority of interrupts can be set by the programs. And
Under the control of the above program, when a plurality of interrupt requests occur simultaneously, the interrupt requests are accepted according to the programmed priority order.

However, according to such a conventional method, the priorities must be set without fail. Therefore, when there are a plurality of types of interrupts that should be generated to the same degree, the interrupts from the peripheral circuits programmed with low priorities are generated. There is a drawback in that the probability of receiving an embedded request is low.

Further, since the priority order is controlled by the program, there is a problem that it is necessary to develop a program for controlling the priority order, which is troublesome.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances and is capable of accepting interrupt requests from peripheral circuits with a substantially equal probability and for controlling priority. It is an object of the present invention to provide an interrupt control device that does not need to develop a program.

[0009]

As shown in principle in FIG. 1, the interrupt control device of the present invention has a pattern that changes at a predetermined time interval and returns to the first pattern when the predetermined pattern is reached. Selection signal generating means 10 for generating a selection signal A having a circulating pattern, and the selection signal generating means 1
0 has input parts I0 to In of interrupt request signals RQ0 to RQn corresponding to the respective patterns of the selection signal A generated by 0, and the input parts I0 to I according to the respective patterns of the selection signal A.
The selection means 11 selects and outputs one of the interrupt request signals RQ0 to RQn input to n.

[0010]

According to the present invention, the selection signal A having a pattern that circulates while changing at a predetermined time interval is generated, and one of the plurality of interrupt request signals RQ0 to RQn corresponding to each pattern of the selection signal A is generated. Is to be selected.

As a result, the timing at which a certain interrupt request signal is selected is only in the case of a specific pattern among the circulating patterns, and the interrupt request signals RQ0 to RQn are evenly selected. You will get it. In other words, for example, interrupt requests from peripheral circuits can be accepted with a substantially equal probability.

Further, since it is not necessary to develop a program for controlling the priority as in the conventional case, there is an advantage that the development can be done with less labor.

[0013]

FIG. 2 shows the configuration of an embodiment of the interrupt control device of the present invention. In the following, for simplification of explanation, it is assumed that there are four peripheral circuits that generate an interrupt request. In addition, the same or corresponding parts as those in FIG.

In the figure, reference numeral 10 is a pattern generation section as selection signal generation means. The pattern generation unit 10 is supplied with two types of clocks CLK0 and CLK1 from a clock generation circuit (not shown).

The clocks CLK0 and CLK1 are clock signals each having a duty of about 50%, and the clock CLK1 has a cycle twice as long as the clock CLK0 as one cycle.

The pattern generation section 10 inputs the above-mentioned two types of clocks CLK0 and CLK1, performs processing for aligning the phases, and then outputs them as selection signals A0 and A1. As a result, the selection signals A0 and A1 are supplied to the selector 11 as signals in which the change points are aligned without phase shift, as shown in FIG.

By these two selection signals A1 and A0, 2
Four patterns of bits "00, 01, 10, 11" will be created.

Reference numeral 11 denotes a selector, which has four data input terminals I0 to I3 and two selection signal input terminals S0 and S1.
And one output terminal O. The interrupt request signals RQ0 to RQ3 are supplied to the data input terminals I0 to I3 from a peripheral circuit (not shown).

The selection signal input terminals S0 and S1 are connected to
Two selection signals A1 and A output by the pattern generator 10
0 is supplied respectively.

The selector 11 has a selection signal input terminal S.
0, S1 selects any one of the interrupt request signals RQ0 to RQ3 supplied to the data input terminals I0 to I3 according to the pattern of the selection signals A1 and A0, and outputs it from the output terminal O. is there.

That is, when the pattern of the selection signals A1 and A0 is "00", the interrupt request signal RQ0 supplied to the data input terminal I0 is selected and output, and when the pattern is "01", it is output to the data input terminal I1. The supplied interrupt request signal RQ1 is selected and output, and in the case of "10", the interrupt request signal RQ2 supplied to the data input terminal I2 is selected and output, and "1" is output.
In the case of "1", the interrupt request signal RQ3 supplied to the data input terminal I3 is selected and output.

Next, the operation of the above configuration will be described with reference to the timing chart of FIG.

Now, assume that two interrupt request signals RQ1 and RQ2 are simultaneously generated at the timing T0 shown in the figure.

Since the point T0 is the pattern "11", the interrupt request signal RQ supplied to the data input terminal I3.
Although it is the timing of selecting and outputting 3, the output of the selector 11 is non-active (L level) because the interrupt request signal RQ3 is not activated (H level).
It remains. At this time, the interrupt request signals RQ1 and RQ2 maintain the H level.

Next, the pattern generator 10 outputs a selection signal for the pattern "00". This is the timing for selecting and outputting the interrupt request signal RQ0 supplied to the data input terminal I0. However, since the interrupt request signal RQ0 is not activated (H level), the output of the selector 11 is non-transmission. It remains active (L level). In this case as well, the interrupt request signals RQ1 and RQ2 maintain the H level.

Next, the pattern generator 10 outputs a selection signal for the pattern "01". This is the timing for selecting and outputting the interrupt request signal RQ0 supplied to the data input terminal I1. In this case, the interrupt request signal RQ1
Is in an active (H level) state,
An active (H level) interrupt request signal IRQ is output to the output of the selector 11 (point T1 in FIG. 3). That is,
This means that the interrupt request signal RQ1 has been accepted.

At this time, the interrupt request signal RQ2 remains at H level. The interrupt request signal RQ2 will be accepted by the same method as described above when the pattern generation unit 10 next outputs the selection signal of the pattern "10".

It is also assumed that two interrupt request signals RQ1 and RQ2 are simultaneously generated at the timing T2 shown in the figure.

Since the point T2 is the pattern "10", the interrupt request signal RQ supplied to the data input terminal I2.
This is the timing for selecting 2 and outputting. At this timing, the interrupt request signal RQ2 is activated (H level), so that the active (H level) interrupt request signal IRQ is output to the output of the selector 11. That is, the interrupt request signal RQ2 is accepted at the same time as it is generated.

At this time, the interrupt request signal RQ1 remains at H level. This interrupt request signal RQ2 will be accepted by the same method as the above when the pattern generation unit 10 outputs the selection signal of the pattern "01" next time.

As described above, according to this embodiment, the timing at which a certain interrupt request signal is selected is only when a specific pattern among the patterns cyclically generated by the pattern generation unit 10 is selected. And each interrupt request signal RQ0-R
Q3 will get an equal chance of being selected. In other words, there is an effect that the interrupt request from the peripheral circuit can be accepted with a substantially equal probability.

Further, since it is not necessary to develop a program for controlling the priority order as in the conventional case, there is an advantage that the development can be done with less labor.

Next, an example in which the present invention is applied to a communication control device will be described with reference to FIG.

In the figure, the pattern generator 10 and the selector 11 are the same as those described in the embodiment of FIG.

Reference numerals 20 to 23 denote communication control units, which have the same configuration. The communication control units 20 to 23 control transmission and reception of data between the communication control device and an external device through a line.

Each of the communication control units 20 to 23 has a function of transmitting and receiving data by DMA (Direct Memory Access). Specifically, regardless of the operation of the CPU 12, data is transmitted from the memory 14 to the line via the system bus 15 or vice versa.

The communication control units 20 to 23 can send and receive data to and from the system bus 15, and the communication control units 20 to 23 send DMA transfer request interrupt signals HRQ0 to HRQ3. Are output to the selector 11. Further, the interrupt enable signals HLA0 to HLA3 are input from the decoder 13. Further, a line is connected to each of the communication control units 20-23.

The processor (CPU) 12 controls the entire communication control device. This CPU12
Transmits / receives data to / from other peripheral circuits via the system bus 15.

The HOLD signal is supplied from the selector 11 to the CPU 12. This HO
The LD signal is an interrupt signal for the CPU 12, and CP
This signal is a request for stopping the operation of U12.

Further, the HLDA signal is supplied from the CPU 12 to the decoder 13. This HLD
The A signal is a response signal to the HOLD signal,
This is a signal indicating that the operation stop request has been accepted.

The decoder 13 controls to which output terminal the input HLDA signal is output in accordance with the selection signal from the pattern generating section 10. The four outputs of this decoder 13 are interrupt enable signals HLA0 to HL.
A3 is supplied to the communication control units 20 to 23, respectively.

The memory 14 stores various data in addition to the control program. The data in the memory 14 is the target of the DMA transfer.

The system bus 15 is a bus for connecting the CPU 12, the memory 14, and the communication control units 20 to 23 to each other, and sends and receives various signals between these respective elements.

Next, the operation of the above configuration will be described. The communication control units 20 to 23 randomly generate interrupt signals HRQ0 to HRQ3 of a DMA transfer request.

Now, assuming that the communication control unit 20 generates the DMA transfer request interrupt signal HRQ0, the pattern of the selection signal from the pattern generation unit 10 is "00" for the DMA transfer request interrupt signal HRQ0. Selector 11
And is supplied to the CPU 12 as a HOLD signal.

Upon receipt of this HOLD signal, the CPU 12 releases the system bus 15 and sends the HLDA signal to the decoder 13. Since the pattern of the selection signal from the pattern generation unit 10 is “00”, the decoder 13 transmits the interrupt permission signal HLA0 to the communication control unit 20. As a result, the communication control unit 20 starts DMA transfer between the memory 14 and the line.

The same applies when an interrupt signal for a DMA transfer request is generated from another communication control unit. When the pattern of the selection signal assigned to the communication control unit is generated, the selector 11 issues an interrupt request. It will be accepted.

When two or more DMA transfer request interrupt signals are generated at the same time, as described above with reference to FIG. 2 and FIG. The interrupt request is accepted, and the system bus 15 is exclusively used for DMA transfer.

As described above, the interrupt request from each communication control unit is accepted only when the pattern of the selection signal which is cyclically generated as "00 → 01 → 10 → 11 → 00 → ..." matches. As a result, the interrupt requests from the respective communication control units can be accepted evenly, and therefore, the DMA transfer can be evenly permitted to the communication control units.

In the above embodiment, the case where the interrupt request signals are randomly generated from the four peripheral circuits has been described, but the peripheral circuits which generate the interrupt request signals are not limited to four. It may be configured to generate an interrupt request signal from any number of peripheral circuits as required by the system and receive the interrupt request signal in accordance with a pattern generated by circulating the interrupt request signal. The same effect is obtained.

[0051]

As described in detail above, according to the present invention,
It is possible to provide an interrupt control device that can receive interrupt requests from peripheral circuits with substantially equal probability and that does not require the development of a program for controlling the priority order.

[Brief description of drawings]

FIG. 1 is a principle diagram of an interrupt control device of the present invention.

FIG. 2 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 4 is a diagram showing an example in which the present invention is applied to a communication control device.

FIG. 5 is a diagram for explaining a conventional interrupt control circuit.

[Explanation of symbols]

 10 pattern generation unit (selection signal generation means) 11 selector (selection means)

Claims (2)

[Claims] 1. A selection signal generating means (10) for generating a selection signal (A) of a pattern that changes at a predetermined time interval and returns to the first pattern when the predetermined pattern is reached and circulates, Input section of interrupt request signals (RQ0 to RQn) corresponding to each pattern of the selection signal (A) generated by the selection signal generation means (10)
(I0 to In), and the interrupt request signal (R) input to the input section (I0 to In) according to each pattern of the selection signal (A).
An interrupt control device comprising: a selection means (11) for selecting and outputting one of Q0 to RQn). 2. The selection signal generating means (10) generates the signal pattern by a pulse signal having a predetermined cycle and a pulse signal corresponding to a signal obtained by dividing the pulse signal. The interrupt control device according to 1.