JPS5945756A - Line buffer device - Google Patents

Abstract

PURPOSE:To form a line buffer having >=2 kinds of constitution, by changing the rule of generation of an address generating circuit to an RAM so as to use efficiently a prescribed memory space. CONSTITUTION:An input data 14 is written in the RAM1 accessed with the address generating circuit 20 in an access control circuit 31 via function circuits 8-10 shown in the figure, and outputted via function circuits 4, 5. The write mode and the readout mode are switched in time division in the RAM1, and the RAM1 is used as a line buffer for the input data 14 from a facsimile device or the like. The address generating circuit 20 receives a buffer constituting designation signal 21 and gives an address based on the signal from counters 2, 36, 7 with the designated rule to the RAM1. Thus, the RAM1 functions as the line buffer applicable to each mode of a facsimile where the variable speed transfer of white and black binary value and the constant speed transfer of intermediate tone.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a line buffer device used for buffer storage of image information and the like.

Conventional configuration and its problems For example, in the N-Axismi 1.1 device, the reading section.

It is necessary to interpose a line path between the decoding section, the recording section, and the encoding section to perform speed conversion of image information.

Such a line buffer is 1 for single mode.
Both the capacity per line and the number of lines could be fixed, and there were no particular problems in realizing the line buffer. Recently, however, facsimile machines have adopted a mix of black and white binary variable speed transfer (digital transmission with processing such as encoding/decoding) and halftone constant speed transfer (analog transmission, etc.) as image information transfer formats. has appeared, causing the problem of increasing line buffer costs.

This problem will be explained assuming that the image size is 34 and the image scanning density is 8 dots/wLl.

In the case of black and white binary variable speed transfer, the capacity per line of the line buffer is 2048 bits, but since it is variable speed, it is necessary to have a large number of lines in order to deal with reading unevenness and storage unevenness. Eight copies are a must. On the other hand, in the case of constant speed transfer of halftones, the number of lines in the line buffer is at least two because the speed is constant, but since the transfer is halftones, the capacity per line becomes large. For example, in the case of 16 gradations, one dot of image information is expressed by 4 bits, so each line buffer requires a capacity of 8192 bits.

As described above, the line buffer 7 is required to have a large number of small capacitances on the one hand, and a small number of large capacitances on the other hand. In such a case, conventionally, the capacity per line is determined according to the constant speed transfer of halftones, and the number of lines is determined according to the variable speed transfer of black and white binary. Therefore, the total capacity of the line buffer is determined by the product of the maximum required line capacity and the maximum number of lines, and there is a problem in that the cost of realizing this increases significantly.

OBJECT OF THE INVENTION An object of the present invention is to solve the above-mentioned problems by using a random access memory (hereinafter abbreviated as RAM).
An object of the present invention is to provide a line buffer device that efficiently uses a certain memory space and realizes line buffers with two or more different configurations at low cost.

Structure of the Invention The line buffer device of the present invention includes a RAM and a
, and an access control circuit that switches its operation mode between an input mode and an output mode in a time-division manner. This access control circuit has an address generation circuit that generates a RAM address signal and supplies it to the RAM, but the generation of the RAM address signal in this address generation circuit depends on the configuration of the line buffer to be realized. By switching the rules, the RAM
9. Switch the division of the memory space. Each memory space divided in this way is allocated to one line of the line buffer.

Description of examples Hereinafter, the present invention will be described in detail with reference to one embodiment. FIG. 1 is a block diagram showing one embodiment of the present invention.

The line buffer device of this embodiment can be broadly divided into a RAM 1 and an access control circuit 31. The access control circuit 31 accesses the RAM 1 while switching the operation mode of the RAM 1 between an input (write) mode and an output (read) mode in a time-division manner. The 0 output mode compatible unit consisting of common parts is a line select counter 2 and a line address counter 3 (both are binary counters).
, an output data buffer 4, and a parallel/serial converter 5. The output data buffer 4 is composed of, for example, an 8-bit register or launch. The parallel/serial converter 6 is, for example, an 8-bit shift register with parallel input and serial output.

The input mode compatible section includes a line select counter 6 and a line address counter 7 (both are binary counters).
, a serial/parallel converter 8, an input data bus 7a 9, and a bus driver 1o.

For example, the serial/parallel converter 8 has a serial input and a parallel output.
This is a bit shift register. Input data buffer 9
is an 8-bit register or latch. The bus driver 10 is a three-state driver, and in the enabled state, the contents of the input data vanifer 10 are transferred to the RAM.
1 bidirectional data bus 3o, but in the disabled state, its output is set to a floating state to release the data bus 3o.

The common part for both modes in the access control circuit 31 includes two selectors 18, 19 . and an address generation circuit 20. The selector 18 selects one output word from the line select counters 2 and 6 and sends it to the address generation circuit 20 as a line select signal 27. The other selector 19 selects the output signal of one of the line address counters 3 and 7 and supplies it as a line address signal 28 to the address generation circuit 2o. The address generation circuit 2o combines the line select signal 27 and the line address signal 28 according to the generation rule specified by the buffer configuration designation signal 21, and generates the RAM address signal 29. By switching this generation rule, the method of dividing the memory space of the RAM 1 is switched. Each divided memory space is allocated as one line of the line buffer, so the buffer configuration designation signal 21 allows multiple types of line buffers with different configurations (capacity per line and number of lines) to be allocated to RAM. It can be achieved on the level of 1.

In this example, it is assumed that it is applied to a facsimile machine that mixes the above-mentioned black and white binary variable speed transfer and halftone (16 gradation) constant speed transfer. ). The size of RAM1 is 8 bits/word x 2048 words (16384 bits). This fixed continuous memory space of RAM 1 is divided into 8 units of 256 words (2048 bits) and used as a line buffer (number of lines is 8, capacity per line is 2048 bits) for variable transfer of black and white binary values. . Or, R.A.
M1 memory space is 1024 words (8192 pintos)
It is divided into two units, and a line buffer (
The number of lines is 2. The capacity per line is 8192 bits).

Note that the input/output of data (image information) to RAM1 is 1.
The operation mode of the RAM 1 is input mode when the input mode signal 17 is "1", and output mode when @OI+.

Various control signals 11 to 17 not mentioned in the above explanation are as follows:
It is supplied from an external circuit (not shown), the details of which will be described later. Further, 14 is input data, which is a serial signal, and 26 is output data, which is a serial signal.

When the line buffer device of this embodiment is used between the reading section and the one-dimensional encoding section of a facsimile machine, the output data of the reading section is input as input data 14, and the output data 2
6 is input to the one-dimensional encoding section.

Further, when used between a one-dimensional post-encoding unit and a recording unit, output data of the one-dimensional post-encoding unit is assigned as input data 14, and output data 26 is used as input data of the recording unit.

Note that by adding another set of circuits similar to the output mode compatible section of the access control circuit 31 and assigning it to the reference mode, it is possible to support two-dimensional sequential encoding/decoding with the same configuration.

Hereinafter, the operation of the line buffer device of this embodiment will be explained in detail. For ease of understanding, a waveform diagram of the main signals in FIG. 1 is shown in FIG. 2.

In the initial state, line select counters 2, 6, . And line address counters 3 and 7 are cleared, and their values are 0 (zero).

First, to explain the operation in the input mode, the input data 14 is bit-serially transmitted to an external device (for example, a reading section of a facsimile machine).
It is sent from. This input data 14 is sequentially taken into the serial/parallel converter 8 at the timing of the input clock 15 and assembled into 8-bit words. When the assembly of 8-bit input data is completed, an input data lanch signal 16 is generated, and the input data is latched into the input data buffer 9 in parallel.

Then, the input mode signal 17 turns on and rises to the "1" state (1), the bus driver 10 becomes enabled (operating state), and the input data (8 bits) in the input data gas sofa 9 is transferred to the data bus 30. The input enable signal 17 is also applied to selectors 18 and 19. The selectors 18 and 19 select the output signals of the line select counter 6 and line address counter 7 of the input mode corresponding section, respectively, and output the line select signals 27 and 19 respectively. It is sent to the address generation circuit 20 as a line address signal 28. In this embodiment, the line select signal 27 is a 3-bit 2
The line address signal 28 is a 10-bit binary code.

Now, assuming that the buffer configuration designation signal 21 is in the llOI+ state, the address generation circuit 2o combines the line select signal 2γ and the line address signal 28 according to the generation rule shown in FIG. 3(b), and generates an 11-bit signal. R.A.
M address signal 29 is generated. R shown in Figure 4(a)
This is a case in which the memory space 32 of AM1 is divided into eight equal parts as shown in FIG. 2(b) to realize a line buffer having a configuration of 2048 bits/line and 8 lines. In addition, L in Figure 3
SB indicates the least significant bit of the line select signal 2, line address signal 28, and RAM address signal 29, respectively.

Since the RAM 1 is in the input mode due to the input mode signal 17 being turned on, the input data on the data bus 30'2 is written to the address specified by the RAM address signal 29. At present, it is written to address 0 (zero) of RAM1.

When writing is completed, the input mode signal 17 turns off, and at the falling edge of the signal, the line address counter 7 counts and amplifies by 1 (at time t in FIG. 2, the next input data is assembled by the serial/parallel converter 8. , is latched in the input data buffer 9, the input mode signal 17 is turned on again, and the appropriate size is written to RAM 1 in the same manner as described above.The write address at this time is address 1 (the time shown in FIG. 2). t
2).

When one line of input data is written to the RAM 1 in this way, the line address counter 7 is cleared by the clear signal 13, and at the same time, the increment signal 22 is generated to increment the line select counter 6 by 1 (see Figure 2). time t3).

After that, each time the input mode signal 17 is turned on, K, RA
Input data is written to address 266 of M1, that is, to sequentially higher addresses from the head position of the second line, and is sized to an appropriate size. When writing of the input data for one line is completed, the line select counter 6 is incremented by 1, and the line address counter 7 is immediately cleared. When the value of the line select counter 6 reaches (111)2, it returns to (Ooo)2 with the next increment signal 22 and starts counting again.

As is clear from the above description, the line select signal 27
is a signal for specifying one specific line in the line buffer implemented on -RAMI. On the other hand, the line address signal 28 is a signal for specifying a specific storage position (digit position @) on an arbitrary line of the line buffer.

The following -1- is a case of a line buffer configuration as shown in FIG. 4(b), where the buffer configuration designation signal 21 is a1''
In this case, the memory space 32 of RAM1 is divided into two equal parts of 1024 words, and as shown in FIG. will be realized. Therefore, the rules for generating the RAM address signal of the address generation circuit 20 are changed as shown in FIG. 3(a). That is, R
The least significant bit of the line select signal 27 is assigned to the most significant bit of the AM address signal 29, and the line address signal 28 is assigned to the following 10 bits. Also, the line select counter 6 has a value of (00o)2. (o○
1) It is incremented by 2, and then it becomes (olo) 2, but as shown in FIG. 3 (-), it becomes LSBL or meaningless (xxo) 2. (However, × means Don't Car.
e) The rest is the same as above.

Next, the operation in the output mode will be explained. For convenience, if the line buffer configuration shown in FIG. 4(b) is specified by the buffer configuration designation signal 21, the output will be zero. Mode signal 23 is turned on. Since the RAM 1 is accessed by switching between the input mode and the output mode in a time-sharing manner, the output mode signal 23 and the input mode signal 17 are exclusively controlled, and of course the input mode signal 1'7 is in the off state at the moment. , R.A.
The operation mode of M1 is output mode.

When the output mode signal 23 is turned on, the selectors 18 and 19 select the output signals of the line select counter 2 and the line address counter 3 for the output mode, and the address generation circuit 2
Send to 0. RAM specified by the RAM address signal 29 (generated according to the generation rule shown in FIG. 3(b))
The stored data (8 bits) at address 1 is output to the data bus 3o, and when the output mode signal 23 turns off, it is latched into the output data bus 4 at the falling edge of the output mode signal 23.

At the same time, the line address counter 3 is incremented by 1 (time t4 in FIG. 2).

Thereafter, on condition that the parallel/serial converter 5 is empty, a load signal 24 is generated, and the data launched in the output data buffer sofa 4 is loaded into the parallel/serial converter 6.
At the timing of the output clock signal 25, the bits are sent out in series as output data 26 to the outside.

Similarly, when the output of one line is completed, the increment signal 32 is generated, and the line select counter 2 is incremented (if the value is (111)2, then (
00o)2), and the line address counter 3 is cleared by the clear signal 12 (time 15 in FIG. 2).

If the buffer configuration shown in Figure 4(C) is specified,
The RAM address signal 29 is generated according to the generation rule shown in FIG. 3(a'), and after the value of the line select counter 2 reaches (001)2,
However, as shown in FIG. 3(a), only the LSB is significant, so it becomes (XXo)2. (However, × is Don't
Data output is performed by the same operations as described above except for (Care).

In this way, according to this embodiment, by using a certain memory space in the RAM 1, line buffers having either of the configurations shown in FIGS. 4(b) and 4(c) can be realized. To achieve the same purpose with the prior art, 8192 bits x 8:656
Considering that 36 bits of memory space is required, the effect of reducing the memory space to realize the line buffer is remarkable.

Note that the address generation circuit 2o has a wiring logic P L
A (Programmable Logic Arr.
Since it can be easily realized by known means such as ay), a specific circuit example thereof will be omitted.

Although one embodiment has been described, the present invention is not limited to this configuration, and various modified embodiments are possible. The line buffer device of the present invention can be similarly applied to image processing devices and other devices other than facsimile devices.

Effects of the Invention As explained above, according to the present invention, the RAM memory space is efficiently used to realize line buffers with different configurations with different numbers of lines and 9 capacities per line in the smallest memory space. can. Therefore, if the present invention is applied to a facsimile machine or the like that uses both black and white binary variable speed transfer and halftone constant speed transfer, it is possible to reduce the memory space for buffer storage of image information, etc., and reduce the device cost. The effect is extremely large.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram of the main signals in FIG. An explanatory diagram, FIG. 4 is a diagram showing how the memory space of the RAM in FIG. 1 is divided.0 1...Random access memory (RAM), 2
゜6...Line selection counter, 3. Finished...
...Line address counter, 4...Output data buffer, 9...Input data buffer,
1o...Bus driver, 18.19...
・Selector, 2o...Address generation circuit, 27
...Line select signal, 28...Line address signal, 29...RAM address signal, 30...Data bus.

Claims (2)

[Claims] (1) A line buffer device that realizes a line buffer with a variable number of lines and a capacity per line in a fixed memory space, which comprises a random access memory (RAM) that provides the memory space, and this RAM. Same R
The access control circuit includes an access control circuit that switches and accesses the operation mode of the AM between an input mode and an output mode in a time division manner, and the access control circuit includes an address generation circuit that generates an address signal (RAM address signal) for the RAM. and which switches the division of the memory space by switching the generation rule of the RAM address signal in the address generation circuit, and allocates each divided memory space to one line of the line buffer. buffer device. (2) The access control circuit sends a line select signal for specifying a specific line of the line buffer;
A counter for generating a line address signal for specifying a storage location on the line is provided separately for the input mode and for the output mode, and a counter for generating a line address signal for specifying a storage location on the line is provided separately, and a The line select signal and the line address signal generated on the other hand are selected by a selector and inputted to the address generation circuit, and this address generation circuit converts the inputted line select signal and line address signal into the generation rule. 2. The line buffer device according to claim 1, wherein said RAM address signal is generated by combining the following.