JPH0363846A - Look-up table device - Google Patents

Abstract

PURPOSE:To reduce the number of signal lines to make access a look-up table(LUT) by storing at least two LUTs in one memory, and making access those plural LUTs in time division. CONSTITUTION:The device is equipped with a data selector 12, a memory 14 to store first and second LUTs, a latch circuit 16 to latch the output of the first LUT, and a latch circuit 18 to latch the output of the second LUT. Also, it is equipped with a bidirectional buffer 20 to transmit data to be transmitted to a central processing unit (CPU) and data to be written on the memory 14 from the CPU. And an input signal to one of the plural LUTs is selected sequentially with the data selector 12, and the data is read out from a selected LUT, and after it is held with the latch circuit transiently, it is outputted sequentially at need to the next processing circuit, and access to the plural LUTs are performed sequentially in time division. In such a way, it is possible to reduce the number of signal lines to make access the plural LUTs.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a lookup table device, and more specifically, the present invention relates to a lookup table device that stores a plurality of lookup tables used as elements constituting an image processing circuit in one memory. <Prior art> Regarding look-up table devices included in image reading devices, image reading/recording devices, etc., photomultiplier tubes, image pickup tubes, and CC
After reading the original image using a solid-state image sensor such as D, the read image signal is subjected to various image processing in an image processing device, and then recorded on a photosensitive material or photoconductor by an appropriate image recording device. recorded in the material.

For example, if an original with continuous tone images such as photographs or film is
In image reading/recording devices such as scanners that produce printing films with halftone images after reading them with an OD and converting them into electrical signals, the image signals read with a CCD are processed by an image processing device such as gain correction, etc. After analog correction, A/D conversion is performed, COD correction such as shading correction and dark correction is performed, and then after each processing such as logarithmic conversion, gradation conversion, magnification conversion, smoothing, sharpening, etc., shading processing is performed. The halftone dot image signal is modulated into a light emission signal from a light source in an image recording device to reproduce a halftone dot image on the film.

In such image processing devices and modulation processing devices of image recording devices (hereinafter collectively referred to as image processing devices), a large number of Lookup table (
LUT) is used. Traditionally, each of these look-up tables (LUTs) was stored in a separate memory.

In addition, such image processing apparatuses use highly integrated image processing circuits that are capable of performing a plurality of different image processes by converting a circuit that performs a plurality of image processes into an IC using a gate array method or the like.

<Problems to be Solved by the Invention> By the way, if one memory is used for one LUT, if a large number of LUTs are used, the memory peripheral circuit, for example, the central processing unit (CPU), will not be able to write data. The number of peripheral circuits increases, making the circuit configuration difficult.

For example, when trying to convert the image processing circuit into an IC using a gate array or the like, the memory storing the LUT is also integrated into the IC.
If you try to do this, the IC will become expensive and the cost of the entire circuit configuration will increase.

For this reason, conventionally, the memory that stores the LUT has been placed outside the IC. By the way, many LUTs
In an image processing device that uses , when one LUT is stored in one memory and multiple processing circuits are integrated into an IC using a gate array, etc., the data line and address line signals connecting the IC and external memory are There is a problem in that wires and the like are required for each memory, the number of bins for connection is insufficient, and the circuit scale that can be integrated into an IC is limited.

For example, the number of signal lines to access one LUT is N.
If this is required, 2N for 2 LLITs, M
When using three LUTs, M−N signal lines are required, and when integrated into an IC, the number of IC pins becomes insufficient.

Furthermore, recently, the capacity of memory for storing LUTs has been increasing, and arranging individual memory chips in very small LUTs is an impediment to cost reduction.

An object of the present invention is to solve the problems of the prior art described above, and to access LOT by storing at least two LUTs in one memory and configuring the plurality of LUTs to be accessed in a time-sharing manner. Not only can the number of signal lines be reduced, making the device configuration compact and inexpensive, but also when arranging the memory that stores the LUT externally, multiple processing circuits can be integrated into ICs using gate arrays, etc. It is also possible to increase the scale of the circuit that can be integrated into an IC, reduce the number of required memories, and
It is an object of the present invention to provide a lookup table device that can increase the processing functions of C and reduce the cost of the entire device configuration, for example, the entire image processing device.

Means for Solving the Problems To achieve the above object, the present invention provides one memory that stores a plurality of lookup tables, and selects an input signal to one of the plurality of lookup tables. The present invention provides a lookup table device comprising a data selector and a latch circuit provided corresponding to each of the plurality of lookup tables and latching the output of each lookup table.

Preferably, the memory stores two look-up tables.

<Operation of the Invention> A lookup table device according to the present invention stores two or more LUTs in one memory, and inputs an input signal to one of the plurality of LUTs by a data selector connected to the memory. By sequentially selecting, reading data from the LUT selected by this input signal, and temporarily holding the output data from this LUT in a corresponding latch circuit, sequentially outputting it to the next processing circuit as necessary. Alternatively, a plurality of LUTs can be sequentially accessed in a time-sharing manner by manually inputting output data from the LUT to the CPU or writing data from the CPU to the LLIT.

Therefore, the look-up table device of the present invention can reduce the number of signal lines for accessing multiple LUTs, reduce the number of required memories, and make the circuit configuration of the device compact and inexpensive. can be taken as a thing.

Therefore, in the circuit configuration of a processing device using the look-up table device of the present invention, such as an image processing device, the circuit scale can be increased when a small amount of memory is placed externally and integrated into an IC using a gate array or the like. IC
6. Embodiment: A look-up table device according to the present invention is attached. A detailed description will be given based on a preferred embodiment shown in the drawings.

FIG. 1 is a block diagram showing an embodiment of a look-up table device of the present invention.

The lookup table device 10 shown in the figure includes a data selector 12 and a first lookup table (hereinafter referred to as L
A memory 14 that stores two LUTs (UT) and an LUT i2, a latch circuit 16 that latches the output of the first LUT, and a latch circuit 18 that latches the output of the second LUT, not shown. It has a bidirectional buffer 2o that transmits data to be transmitted to the CPU and data to be written from the CPU to the memory 14.

The data selector 12 inputs an input signal IN to the first LUT.
One input signal is sequentially selected from three input signals: I, the input signal IN2 to the second LUT, and the CPU 7 address signal CPU ADRESS, according to a command from a CPU (not shown) or a predetermined order, This is for transmitting 14 memories, and a data selector such as a multiplexer (MUX) can be used. The data selector 12 and the memory 14 are connected by a set of signal lines, that is, address lines, and one input signal selected by the data selector 12 is transmitted to the memory 14.

The memory 14 is a memory that stores the first LUT and the second LUT, and may be a ROM if its contents are not written or rewritten by the CPU, but write from the CPU is considered. If necessary, it is better to configure it in RAM. One memory has two LUTs, LU which is the first lookup table.
Any method may be used to allocate the contents of T1 and the second lookup table LUT2, but
For example, LUT 1 and LL as shown in Table 1 below
When the contents of IT2 are 8 bit data, the address data is 9 bits and the memory address is ooooooooo
Assign o to 011111111 to LUT 1,
Memory address 100000000 to 11111111
Up to 1, a method such as assigning to LOT2 can be used.

Table 1 Memory Allocation Here, the address data for reading the contents of LUT 1 and LUT 2 is 9-bit data, and the first Ib1t is data for determining which LUT to select between LUT 1 and LUT 2, for example, 0. If it is 1, the contents of the LUT 2 lookup table are read out. The data read in this way is 8-bit data as described above.

With this configuration, the address line to the memory 14 storing two LUTs consisting of abit memory data is 9 bits, which transmits 9 bits of address data.
Any real signal line will suffice. On the other hand, when two LUTs consisting of 8-bit memory data are stored in separate memories, the address data for each memory is 8 bits, and 8 signal lines are required for each memory to access each memory, for a total of 16 lines. signal lines are required. In one memory 14 storing two LUTs like the look-up table device 10 of the present invention shown in FIG. 1, the number of signal lines for access can be nine.

Although in the above example, the memory amounts of LUT 1 and LOT 2 are made equal, the present invention is not limited to this, and one may be increased and the other may be decreased.

Further, the number of LUTs stored in the memory 14 is not limited to two, and may be three or more, and the number of LUTs stored in the memory 14 may be changed as appropriate depending on the capacity of the memory 14, the size of the LUT, and the contents. However, as the number of LUTs stored in one memory increases, the time required to read data of a particular LOT from the memory increases.

Therefore, if the look-up table device 10 of the present invention can be operated at low speed, a large number of LUTs can be stored in one memory.

When a certain degree of speed is required for data processing, such as when an image processing device processes a large amount of pixel data, it is preferable to store two LUTs in one memory.

- When the number of signal lines for accessing one LUT in a is N, when two LUTs are used, if one LUT is stored in one memory and used as in a conventional device, it is 2N. Although a tree signal line is required, if two LUTs are stored in one memory and used as in the look-up table device of the present invention, the number can be reduced to N+1 signal lines. Furthermore, 2M or 2M-1 LUTs
When using 2M-N or (2
M-1) - N signal lines can be reduced to N+M signal lines.

The data line extended from the memory 14 is the latch circuit 1.
6.18 and bidirectional buffer 20.

The latch circuits 16 and 18 are connected to a first LUT (LUTl) and a second LUT that are sequentially output from the memory 14, respectively.
The latch circuit 16 is a circuit that temporarily stores the data of the LUT (LOT2) of
The latch circuit 18 outputs the 8-bit data of T1 as 0UTI, and the latch circuit 18 outputs the 8-bit data of LOT2 by IN2 as 0UT2.

The bidirectional buffer 20 is a transmission direction switch that can transmit data from the memory 14 to the CPU and also transmit data to be written to the memory 14 from the CPU.

Here, in the look-up table device 10 of the present invention, except for the memory 14 storing two LUTs, that is, the data self-fitter 12, two latch circuits 16.
18 and the bidirectional buffer 20 can be integrated into an IC using a gate array or the like together with a CPU (not shown).

At this time, between the memory 14 and the IC, a data line consisting of, for example, nine signal lines connected to the data selector (MUX) 12 of the IC and two latch circuits 16 and 18, for example, are connected to the data selector (MUX) 12 of the IC. A data line consisting of eight signal lines is tangential. In addition, although not shown, memory 1
A control line for controlling reading from the memory 14 to the CPU or writing from the CPU to the memory 14 is connected between the memory 14 and the CPU. Although not shown, in the IC, a data selector (MUX) 1
A control line for controlling the latch circuits 16 and 18, a control line for controlling the latch circuits 16 and 18, etc. are connected between the timing control circuit and the timing control circuit. As described above, conventionally known circuit configurations can be used for the configuration of the CPU and the control circuit.

The look-up table device 10 of the present invention is basically configured as described above, and its operation will be described below.

First, the data selector (MUX) 12 selects INI based on a predetermined signal from the timing control circuit, and
The 9-bit address data input from I and starting with O is output to the memory 14. In memory 14, LUT
1 reads out 8-bit memory data according to the address data, outputs it to the latch circuit 16, and outputs it to the latch circuit 16.
After temporarily holding it at 6, it outputs it to 0UT1. On the other hand, when the signal from the timing control circuit switches, the data selector (MLIx) 12 selects IN2 and outputs the 9 bft address data input from IN2 with 1 at the beginning to the memory 14. LLJT2 to 5
After reading the memory data of btt and outputting it to the latch circuit 18 and temporarily holding it in the latch circuit 18, 0UT2
Output to.

In this way, the data selector (MUX) 12 alternately selects input signals from INI and IN2 in a time-division manner according to a predetermined signal of the timing control circuit, for example, a clock signal.
Output to memory 14. In addition, latch circuits 16 and 18
Then, data is alternately temporarily held and output in a time-division manner according to a predetermined signal of the timing control circuit, for example, a signal corresponding to a clock signal.

In addition, data selector (MUX) 12 TE cPU 8 DR
When ESS is selected, an address is specified by this signal, and the CPU reads or writes data to the memory at that address via the bidirectional buffer 20.

FIG. 2 shows an example of a specific circuit configuration of the look-up table device 10 of the present invention shown in FIG. 1, and FIGS. 3 and 4 show the look-up table device 10 shown in FIG. The components of the lookup table device 10 shown in FIG.
The look-up table device 10 shown in FIG.
Since it is exactly the same as , detailed explanation thereof will be omitted.

In Figure 2, A% of data selector (MUX) 12
B and C are INI, IN2 and Aort respectively
(Indicated as CPIJ ADRESS in the 'M1 figure) indicates the input side terminal, and Y indicates the output side terminal. Also, S
1 and S2 are selection signals (input terminals) for the human cutting edges A, B, and C.

In the memory 14&:, A indicates memory address data (input terminal), D indicates memory data (output terminal), and WE and OE are timing signal input terminals for reading and writing from the memory 14, respectively.

In the latch circuits 16 and 18 &:, D is memory data (input terminal) and Q is output data (output terminal).

DATA of the bidirectional buffer 20 is an input/output line between the CPU and the memory 14 (not shown) for transmitting data (for example, image data).

The timing control circuit 22 includes a MUX 12, a memory 14,
This is a control circuit for controlling signal selection and input/output timing of the latch circuits 16 and 18 and the bidirectional buffer 20. Here, on the input side, CLK is the clock signal (input side terminal), MODE is the CPU access operation (
A mode selection signal (input side terminal) that selects between MODE=0) and real-time operation (MODE=1), RD and WR indicate the memory read signal and memory write signal (input terminal) from the CPU, respectively, and the output On the side, G1 and G2 are transmission direction control signals (output terminals) for reading and writing data from the memory 14 by the CPU of the bidirectional buffer 20, respectively;
As mentioned above, SL and S2 are the select signals (output terminals) of the MUX 12, WE and OE are the write and read timing signals of the memory 14, and C
1 and C2 are input/output timing control signals of latch circuits 16 and 18, respectively.

Here, the operation of the MUX 12, which is a data selector, is to set the cutting edge to A by signals Sl and S2 from the control circuit 22.
, B, and C and outputs it to the memory 14 as a Y output. Table 2 shows an example of the selection method.

Table 2 First, LUT 1 or LU of memory 14 by CPU
When performing a CPU access operation for reading and writing T2, the mode selection signal MODE=O is input to the timing control circuit 22, and the MUX selection signal 51=O is input from the timing control circuit 22 to the MUX 12.

52=1 is input.

At this time, as shown in FIG. 3C, the timing control circuit 22
When the memory read signal RD and memory write signal WE change, G1 changes in accordance with the change in RD, and the data transmission direction is switched from the bidirectional buffer 20 to the direction in which data is transmitted from memory 4 to the CPU, and OE changes. Then, according to the change in WR, G2 switches the data transmission direction of the bidirectional buffer 20 from the CPU to the memory 14, and WE puts the memory 14 in a readable state. do.

On the other hand, when performing a real-time operation of sequentially reading out LUT 1 and LUT 2 stored in the memory 14, the mode selection signal MODE=1 is input to the timing control circuit 22, and the MUX selection signal 52 is always sent from the timing control circuit 22 to the MUX 12. =0 is input. Also, at this time, the timing control circuit 22
A memory write signal WE=1 and a memory read signal 0E=O are always input to the memory 14, and writing to the memory 14 is prohibited, while reading from the memory 14 is always enabled.

Here, as shown in FIG. 4, the timing control circuit 22
When the lock signal CLK is input manually as shown in the figure, the MUX select signal S1 changes accordingly, and the C blade tip is set to A (0, INI) and B (1, IN2) as shown in Table 2.
, and the tying control signals C1 and C2 change correspondingly to latch circuits 16 and 1, respectively.
Controls input/output of 8. That is, as shown in FIG. 4, the contents of the input end memory A of the memory 14 change from 0 to 1 according to the change of the MUX select signal S1 between 0 and 1. The table changes to the memory address data of INI and the memory address data of 1 and IN2, and the contents of the memory D on the output side of the memory 14 and the input side of the latch circuits 16 and 18 are read out according to these address data. 1, that is, the data of LUT 1 and LOT 2.

Further, as shown in FIG. 4, the OUT of the latch circuit 16
! and 0UT2 of the latch circuit 18 are the signals C1 and 0UT2 of the latch circuit 18, respectively.
And it switches at the rising edge of C2.

In this way, the lookup table device 10 shown in FIG.
At this time, the contents of two look-up tables, LUT 1 and LOT 2 shown in Table 1, are sequentially read out from one memory 14.

The look-up table device of the present invention can be suitably used for circuits that require a plurality of LOTs, particularly various processing circuits of image processing devices, such as tone conversion processing circuits, smoothing processing circuits, and sharpening processing circuits. can.

The present invention has been described above with reference to preferred embodiments, but
The present invention is not limited to this, and it goes without saying that various improvements and changes in design can be made without departing from the gist of the present invention.

<Effects of the Invention> As detailed above, according to the present invention, a plurality of lookup tables are stored in one memory, so compared to the case where one lookup table is individually stored in one memory. Therefore, the number of signal lines for accessing lookup table C can be reduced.

Therefore, according to the present invention, when a plurality of processing circuits are integrated into an IC using a gate array or the like, a plurality of lookup tables can be stored in one external memory, and each external one can be stored in the memory. Since the number of signal lines can be reduced compared to the case, the number of bins will not be insufficient when integrated into an IC, and the scale of integration into an IC is not limited.

Therefore, according to the present invention, it is possible to reduce the number of memories used, and it is also possible to make it compact when integrated into an IC, so that the implementation of rJl# can be made compact and inexpensive. Therefore, the look-up table device of the present invention can be suitably used in each fit processing circuit of an image processing device that performs a large number of processes.

Explanation of symbols 10... Lookup table device, 12... Multiplexer (MUX), 14... Memory, 16.18... Latch circuit, 20... Bidirectional buffer, 22... Tie main control circuit

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a look-up table device according to the present invention. FIG. 2 is a block diagram of an example of a specific circuit configuration of the look-up table device shown in FIG. 1. 3 and 4 are time charts showing examples of different operating states of the lookup table device shown in FIG. 2.

Claims (1)

[Claims] (1) One memory that stores a plurality of lookup tables, a data selector that selects an input signal to one of the plurality of lookup tables, and a data selector that is provided corresponding to each of the plurality of lookup tables. , and a latch circuit that latches the output of each lookup table.