KR920008274B1 - 16/256 color switching apparatus - Google Patents

Abstract

The circuit switches 16 color/256 color in one circuit according to the need of a user. It comprises a graphic system processor (GSP;10) for inputting/outputting the data responding to a display (18) to/from the video RAM of defined address, a decoder (11) , video RAM (14) for storing one frame video data which is 4 bit or 8 bit per pixel, the 1st multiplexer (22), and the 2nd multiplexer (26) for responding to the control signal inputted to a video data output control port (A/B).

Description

16/256 color switching devices in graphics systems

1 is a schematic block diagram of a graphics control portion of a graphics system.

2 is a schematic block diagram of a 16/256 color switching device according to the present invention.

3A-3D are timing diagrams of respective parts of the apparatus in the 16 color mode.

4A-4D are timing diagrams of respective parts of the apparatus in 256 color mode.

* Explanation of symbols for main parts of the drawings

10: graphics system processor 14: video RAM

17: color pallet 22, 26: multiplexer

24: decoder 25, 35, 45, 55: flip flop

The present invention relates to an apparatus for selectively switching an image displayed on a workstation, a graphic terminal in a graphics system to be reproduced by the user at 16 colors or 256 colors as arbitrarily designated.

In general, when processing graphics on a CRT display, image processing is performed using a central processing unit (CPU) of the system and a CRT controller which generates various signals necessary for graphics under the control of the CPU.

However, in recent years, in parallel with the development of the semiconductor industry, a device has been developed to perform all image processing functions that can be controlled in-house, that is, within a single unit system without the help of a system CPU. This is a processor (Graphic System Processor).

This GSP is a dedicated graphics processor in the form of a processor that is completely outside the scope of conventional CRT controllers and has a completely different design idea and architecture.

GSP applications are widely applied to CRT output control of various computers to page printers (particularly laser printers) and facsimile devices.

The conventional method for reproducing an image composed of video data on a CRT display using color GSP, for example, 16 colors or 256 colors, is a system having only one function of 16 colors or 256 colors at user's option. It was fixed and used. As such, since there was no way to use 16 colors and 256 colors at the same time, it was only possible to change the color circuit configuration in hardware in order for the user to select the desired color, which was inefficient and expensive.

The present invention has been invented to solve the above-described problems, and an object thereof is to provide an apparatus which enables a user to switch a desired 16 color or 256 color selection in one circuit. The invention is explained as follows with reference to the accompanying drawings.

Referring to the drawings, FIG. 1 shows only a graphic control part inside a conventional computer, and 10 is a GSP that functions as a separate processor without the help of a processor of the main system, and works with the display 18. FIG. The corresponding data is input to the designated address of the video RAM through the data bus, and the data is output to perform graphics processing.

The decoder 11 decodes the control signal output from the GSP 10 to access each part as shown in the figure. ROM and RAM 12 and 13 may be shared with the memory means of the main system, respectively, as the memory means of the graphics system. The video RAM 14 stores one frame of video data corresponding to the CRT display 18 one-to-one. The data is stored in the video RAM 14 in a bitmap manner, and is composed of 4 bits or 8 bits per pixel. Thus, one pixel can be expressed in 16 or 256 kinds of colors. Data of the video RAM 14 is output by 32 bits and applied to the color pallet 17 through the flip-flop 16.

The pallet 17 includes a pixel mask register (not shown) therein, and the R (Red) component, the G (Green) component, and the B (Blue) component are used to process an image on a CRT display. There is a memory that can store a video screen as it is so that the colors can overlap and generate a variety of colors. 15 is a 16/256 color switching device according to the present invention.

FIG. 2 shows the overall hardware for implementing the present invention, which is a detailed circuit diagram of (15) of FIG. 3A to 3D and 4A to 4D are timing diagrams of respective parts of FIG. 2 in the 16/256 color mode, respectively, and the color selection scheme of the present invention will be described in detail with reference to the drawings.

In order to reproduce the displayed image arbitrarily in 16 colors or 256 colors, the user first initializes the pixel mask register (not shown) in the pallet 17 to a value suitable for the 16 color mode or the 256 color mode. This operation is to be applied to the input terminal of the pallet 17 by 4 bits in case of 16 color mode and 8 bits in case of 256 color mode, which can be accomplished by a simple program. The 4-bit or 8-bit video data will be a unit constituting one pixel each in 16/256 color mode.

/B)는 GSP(10)로 부터 인가되는 16/256 컬러 선택 제어 신호에 의해, 예로, 16 컬러인 경우 ＂0＂, 256 컬러인 경우 ＂1＂로 각기 세트된다. 이 멀티플렉서(22)는 3개씩의 입력선(A1,A2 및 A3) 및 (B1,B2 및 B3)으로 이루어진 두 입력 집합중의 하나를 선택하는 회로로서, 다음에 설명될 카운터(21)로부터 출력되는 신호에 따라 선택된 하나의 집합 신호를 그 해당하는 출력 단자(1,2 및 3)를 통해 각기 출력한다. 또한, 제2도에서 도시된 바와같이, 멀티플렉서(22)는 입력단자(B1 내지 B3)의 단자(B1)에는 하이(high)상태의 Vcc가 인가되고 있음을 알 수 있다.Then, according to the external operation keys, for example, the selection signal of the keyboard, the 16/256 color selection input terminal of the multiplexer 22 (

/ B) is set to, for example, '0' for 16 colors and '1' for 256 colors by a 16/256 color selection control signal applied from the GSP 10, respectively. This multiplexer 22 is a circuit for selecting one of two input sets consisting of three input lines A1, A2 and A3 and (B1, B2 and B3), which is output from the counter 21 to be described later. One set signal selected according to the signal is output through the corresponding output terminals 1, 2 and 3, respectively. In addition, as shown in FIG. 2, it can be seen that the multiplexer 22 is applied with the high state Vcc to the terminal B1 of the input terminals B1 to B3.

및 B)중에서 단자(B)의 데이타만을 출력하게 해주기 위한 것으로, 이것은 명세서를 통해 볼때 이해될 것이며, 여기에서

및 B는 본 발명에서 각기 16 컬러 모드 및 256 컬러 모드와 연관된 사항을 지칭하는 것으로 한다.This is because the terminal of the second multiplexer 27 is selected when 256 color mode is selected according to the present invention.

And B) to output only the data of the terminal (B), which will be understood from the specification, where

And B is to refer to the matter associated with 16 color mode and 256 color mode respectively in the present invention.

The counter 21 initially initialized outputs the counted signal from the outside to the input terminals Al to A3 and B1 to B3 of the multiplexer 22 by input through the data buses DBO to DB2. The output waveform is shown in FIGS. 3A and 4A.

In this case, when one color mode is selected by the above-described 16/256 color selection control signal, the multiplexer 22 input terminals Al to A3 or B1 to B3 corresponding to the selected color mode. Is connected to the output terminals (1, 2 and 3).

Two output signals of the multiplexer 22 are applied to the decoder 24 of the next stage, and the other output signal is applied to the second multiplexer 21.

As is well known, the decoder 24 generates four output signals decoded according to the two output signals, and the next four flip-flops 25, 35, 45, 55, (Fig. 16), respectively (see FIGS. 3b and 4b). The flip-flop selection signal is an output enable signal for outputting video data latched to the flip-flop.

및

)를 비디오 RAM(14) 및 각각의 플립플롭(25 내지 55)으로 각기 출력하며, 이러한 클럭신호의 파형은 제3d도 및 4d도에서 도시된다.On the other hand, in Fig. 2, it can be seen that the output of the counter 21 is also input to the PAL (Programmable Array Logic) 23. This PAL 23 is synchronized with the clock oscillator 20 and the system clock signal (

And

) Are output to the video RAM 14 and the respective flip-flops 25 to 55, respectively, and the waveforms of these clock signals are shown in FIGS. 3d and 4d.

에 동기하여 그 내부의 32비트 비디오 데이타를 병렬 데이타 라인(SDO 내지 SD31)을 통하여 출력하면, 네개의 플립플롭(25 내지 55)은 상기 클럭신호

에 동기하여 상기 32비트 데이타를 병렬 데이타 라인(SDO 내지 SD7,SD8 내지 SD15,SD16 내지 SD23 및 SD23 내지 SD21)을 통하여 각기 8비트씩 수신한다.Video RAM 14 is the clock signal

When the 32-bit video data therein is output through the parallel data lines SDO to SD31, the four flip-flops 25 to 55 generate the clock signal.

The 32-bit data is received by 8 bits in parallel through the parallel data lines SDO to SD7, SD8 to SD15, SD16 to SD23, and SD23 to SD21.

As described above, 8-bit video data each latched to four flip-flops is output in accordance with each flip-flop sequentially selected by the decoder 24.

Once 8-bit data is output from one flip-flop 25, then 8-bit data is output again from another flip-flop in succession, where the 8-bit data is a data line (PO to P3) and ( Four bits are input to the second multiplexer 26 through P4 to P7).

및 B가 선택되므로 (PO 내지 P3) 및 (P4 내지 P7)을 통해 입력된 비디오 데이타가 선택적으로 출력된다. 또한, 256 컬러 모드인 경우, 상기 제1멀티플레서 (22)의 단자(1)로 부터의 제어 신호에 의해 항시 데이타 라인(P4 내지 P7)을 통해 입력된 데이타만을 출력한다. 그리고 (PO 내지 P3)를 통해 입력되는 데이타는 직접파렛트(17)로 인가됨을 알수 있다.The second multiplexer 26 selectively corresponds to the video data output control terminal A / B, two input terminals A1, A2, A3 and A4 and B1, B2, B3 and B4, and the two input terminals. And output terminals 1, 2, 3, and 4, and the output data are selectively outputted by a control signal from the output terminal 1 of the multiplexer 22. That is, as can be seen in FIGS. 3C and 4C, in the 16-color mode, the low and high signals are repeatedly switched.

And B are selected, so video data input via (PO to P3) and (P4 to P7) is selectively output. In the 256 color mode, only data input through the data lines P4 to P7 is always output by the control signal from the terminal 1 of the first multiplexer 22. And it can be seen that the data input through (PO to P3) is directly applied to the pallet (17).

As described above, the data selectively output is commonly input to the input terminals P4 to P7 of the pallet 17. Since this initializes the pallet 17 to initially select the desired color, the video data cannot be input to the disabled input terminals PO to P3 of the pallet 17 when in the 16 color mode, and the 256 color mode. In this case, the input may be input through the entire input terminals PO to P7 of the pallet 17.

By this operation, the pallet 17 is configured to selectively reproduce the input 4-bit data (in 16 color mode) or 8-bit data (in 256 color mode) into one pixel, respectively, on the CRT display 18. It becomes possible.

Claims (3)

A color graphics system for displaying 16 colors or 256 colors respectively corresponding to one pixel composed of 4 or 8 bits of video data, comprising: a graphics system processor (GSP) 10; A video RAM 14 for storing one frame of video data corresponding one-to-one with an image reproduced on the CRT display 18; Respective latch circuits (25, 35, 45, 55) for latching the video data output 32 bits from the video RAM 14 by 8 bits, respectively; A counter (21) for counting control signals transmitted from the graphics system processor (10) via data buses (DBO to DB2); A color selection input terminal for receiving specified 16 and 256 color selection signals from the graphics system processor 10;

/ B), two input terminals (A1 to A3 and B1 to B3) for receiving the count output of the counter 21, and a signal received at the two input terminals in response to a designated one of the color selection signals. A multiplexer (22) having output terminals (1, 2 and 3) for outputting selectively; A decoder (24) for providing a decoded output in accordance with the output of the multiplexer (22) and for enabling the respective latch circuits (25 to 55); Receives an output substantially identical to the output of the counter 21 applied to the multiplexer 22 and the output of the clock oscillator 20 to clock the system to the video RAM 14 and the respective latch circuits 25 to 55. Programmable array logic 23 for generating signals SCLK and SCLK1, respectively, and video data in the video RAM 14 are outputted by the clock signal SCLK. Receive the video data; A video data output control terminal for receiving a control signal from the output terminal 1 of the multiplexer 22 (

/ B), a first having two input terminals A1 to A4 and B1 to B4 to which data of the latch circuits 25 to 55 are input, and output terminals 1 to 4 selectively corresponding to the two input terminals. Two multiplexers 26; And a pallet (17) for combining the video data applied from the latch circuits (25 to 55) to provide a 16/256 color image on the monitor (18). 2. The multiplexer (22) according to claim 1, wherein the multiplexer (22) causes the terminal (B1) of one of the input terminals associated therewith to always be applied with a high value for 256 color selection, and the second multiplexer (26) is a video. Data output control terminal

/ B) in response to the control signal input to the 16 color mode, alternately outputs the data input to each of the two input terminals (A1 to A4 and B1 to B4) alternately, in the case of 256 color mode input terminal (B1) To B4) 16/256 color switching device of the graphics system for outputting only the data input. The pallet 17 is inputted with the upper 4-bit data directly applied from the latch circuits 25 to 55 and the 4-bit data selectively outputted from the second multiplexer 26. 16/256 color switching device of a graphics system having terminals (PO to P7), the terminals being initialized to input data constituting one pixel according to a 16/256 color selection.

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