JPH07262349A - Method and circuit for dither modulation, method and circuit for generating address for dither table and hard copy circuit using these methods and circuits - Google Patents

Abstract

PURPOSE:To eliminate the necessity to which the control unit of an address for referring to a dither table correspondingly to the requested number of gradations to be added in the case of executing dither modulation. CONSTITUTION:When it is desired to selectively use the dither table of 3X3 and the dither table of 4X4, a storage space 100 of 12X12 is prepared as a storage space. The dither table of 3X3 is uniformly stuck on the storage space 100 without space as a unit dither table 102. When using the dither table of 4X4, the dither table of 4X4 is uniformly stuck on this storage space 100 without space as a unit dither table 104. Since the size of the storage space 100 is set to the least common multiple among sizes of various dither tables to be required, only one address generation control unit corresponding to the storage space 100 of 12X12 is required for reading a threshold value from the dither table.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hard copy circuit used for hard copying a graphic displayed on the screen of a display device such as a graphic display device, and more particularly to a dither modulation suitable for this hard copy circuit. The present invention relates to a method and a circuit, a dither table address generating method and a circuit.

[0002]

2. Description of the Related Art Graphic display devices are widely used as devices capable of displaying graphics. In Figure 4,
The configuration of a system using a graphic display device as an intelligent terminal having a graphic display function is shown.

In the system shown in this figure, graphic information is transmitted from the host computer 10 to the graphic display device 12. The transmitted graphic information includes information indicating the display position of the graphic on the screen of the CRT 14 of the graphic display device 12, the type of graphic to be displayed, and the like. The graphic display device 12 includes a coordinate transformation device 1 in addition to the CRT 14.
6, a digital differential analyzer (DDA) 18, a frame buffer (FB) 20, a video signal converter 22, and a hard copy circuit 24.
The graphic information transmitted from is first input to the coordinate conversion device 16.

The coordinate conversion device 16 performs coordinate conversion on the information indicating the display position and the like among the graphic information received from the host computer 10. That is, from the coordinate system used in the host computer 10, the CRT14
Convert to the coordinate system corresponding to the screen. DDA18
Performs a digital differential analysis, that is, a process of generating a vector, based on the graphic information after the coordinate conversion. The graphic information that has been subjected to this type of processing is expanded on the FB 20 having a storage space corresponding to the screen of the CRT 14 (drawing of a graphic). The video signal converter 22 converts the figure drawn on the FB 20 into a video signal and displays the figure on the screen of the CRT 14 based on the obtained video signal. In this way, the graphic is displayed on the screen of the CRT 14 based on the graphic information transmitted from the host computer 10.

The hard copy circuit 24 is a circuit for making a hard copy of an image such as a graphic displayed on the screen of the CRT 14 using the hard copy device 26. As described above, since the graphic information corresponding to the graphic displayed on the screen of the CRT 14 is expanded on the FB 20, the hard copy is basically FB 20.
It can be realized by data transfer from. Also, CRT14
Hard copy device 2 and the three primary colors used to display graphics on top
6 is different from the three primary colors used in hard copying, and the latter three primary colors are yellow (Y), magenta (M), and cyan (C), and therefore color conversion of graphic information is required.
For these reasons, the hard copy circuit 24 includes a look-up table (LUT) 28 and a direct memory access controller (DMAC) 30. DMAC3
0 transfers the graphic information on the FB 20 to the LUT 28 by DMA when a hard copy request is issued by the host computer 10 or the operator. LUT28 is 3
It is composed of tables corresponding to the primary colors Y, M, and C, and the graphic information DMA-transferred from the FB 20 is developed in these tables. By outputting the graphic information expanded on the LUT 28 to the hard copy device 26 via the interface (I / F) circuit 32, the CRT 14
The figure displayed on the screen of can be color-converted and then hard copied.

However, if only such processing is performed, L
When performing color conversion in the UT 28, much of the color information in the graphic information is lost. That is, each of the three Y, M, and C tables constituting the LUT 28 has two tables.
Since it is a gradation and the total of 3 sheets is only 2 ³ = 8 gradations,
When the graphic information is developed on the LUT 28, most of the color information in the graphic information is lost. In order to deal with such a problem, the graphic display device 1 shown in FIG.
The hard copy circuit 24 in FIG. 2 has a dither modulation circuit 34.

The dither modulation circuit 34 artificially increases the number of gradations of the graphic information, which actually drops to 8 gradations in the LUT 28, to the required degree, and then the I / F circuit 32.
To the hard copy device 26 via. That is,
The dither modulation circuit 34 artificially increases the number of gradations based on the principle that "when an image in a certain narrow range is viewed from a distance, it looks like an averaged color of all pixels in the range". Specifically, the dither modulation circuit 34 binarizes (generally N-valued, N is plural) the graphic information on the LUT 28 by using a threshold value set according to a predetermined rule, to thereby obtain the number of gradations. Is increased artificially. The threshold for that is stored in the dither table 36, and
For the graphic information on T28, refer to this dither table 3
After being binarized by the threshold value read from 6, the data is output to the hard copy device 26 via the I / F circuit 32. An address for accessing the dither table 36 and obtaining a necessary threshold value is generated by a counter 38 according to the required pseudo gradation number.

FIG. 5 shows the counter 3 in this conventional example.
8 configurations are shown. Counter 3 shown in this figure
8 is an I / O register 40, a control circuit 42, a selector 4
4 and an XY counter 46. The control circuit 42 includes a decoder 48 and a 1 × 1 control unit 5
0, 2 × 2 control unit 52, 3 × 3 control unit 54
And a 4 × 4 control unit 56.

The counter 38 shown in FIG.
DMA indicating that DMA transfer from 0 to LUT 28 has started
When the signal is notified from C30, the generation of the address for accessing the dither table 36 is started. Prior to this, the counter 38 receives the mode designation from the firmware. That is, the firmware gives information indicating the setting of the number of gradations to be added in a pseudo manner,
It is stored in the I / O register 40. As the number of additional gradations that can be set from the firmware, 2, 4, 8 and 16 are prepared. The control circuit 42 selectively activates any one of the four control units 50 to 56 according to the setting of the number of additional gradations from the firmware. The decoder 48 of the control circuit 42 decodes the gradation setting information on the I / O register 40 to realize such selective activation, determines which control unit 50 to 56 should be activated, and the determination result An operation selection signal is generated in accordance with.

Generally, in binary dither modulation, 2 ⁿ
In order to add the gradation in a pseudo manner, a threshold value is set for each pixel in the range of n pixels in the X direction × n pixels in the Y direction, and the range of the n pixels × n pixels is “averaged in pixel color”. Must be in the range. If the range of "pixel color averaging" is widened, the resolution of the image is reduced, so this range is limited to a range of at most 4 pixels x 4 pixels from a practical point of view. Each of the four control units 50 to 56 provided in FIG. 5 has a range of 1 pixel × 1 pixel, 2 pixels × 2 pixels, 3 pixels × 3 pixels, or 4 pixels × 4 pixels in the range of “pixel color A control signal is generated in order to control the counting operation of the XY counter 46 so that it is in the range of "averaging". Therefore, of these four control units 50 to 56, the 1 × 1 control unit 5
0 is 2 when the gradation setting information indicates “addition of 2 gradations”.
The × 2 control unit 52 is 4 × 4 when the gradation setting information indicates “addition of 4 gradations”, and the 3 × 3 control unit 54 is 4 × 4 when the gradation setting information is “addition of 8 gradations”. When the gradation setting information indicates “addition of 16 gradations”, the control unit 56 is activated in accordance with the operation selection signal from the decoder 48.

The selector 44 includes four control units 50.
The control signal from the unit that has been activated is selected from to 56 and is supplied to the XY counter 46. XY counter 46
Performs a counting operation according to the supplied control signal, and generates X and Y addresses for reading the threshold value from the dither table 36. When the threshold value is read from the dither table 36 by using the X and Y addresses and the figure information on the LUT 28 is dither-modulated by using the read threshold value, the figure is added by the number of additional gradations designated by the firmware. The number of gradations of information increases in a pseudo manner.

FIG. 6 shows an example of the contents of the dither table 36. (A) to (d) show examples of table contents used when the number of additional gradations is 2, 4, 8 or 16, respectively. These 4 as dither table 36
Although it is possible to provide all kinds of tables, normally, one of the four kinds of contents is pasted on a single table as needed. That is, as shown in FIG.
Different contents are pasted on the storage space having a size of × 4 depending on the required number of additional gradations. In this way, any of the four types can be selected according to the designation from the firmware. In FIG. 7, (a) to (d) show examples of table contents used when the number of additional gradations is 2, 4, 8 or 16, respectively.

[0013]

However, in the case of such a configuration, the control content of the counting operation in the counter must be switched according to the number of additional gradations required by the firmware. Therefore, conventionally, there has been a problem that the scale of hardware is large. In order to avoid such a problem, it suffices to eliminate the function of selecting one of a plurality of additional gradation numbers.
This leads to reduced usability.

The present invention has been made to solve the above problems, and by devising the structure of the dither table, a counting operation for generating an address for reading a threshold value from the dither table is performed. The purpose is to enable the same operation regardless of which additional gradation number is selected.

[0015]

In order to achieve such an object, the dither modulation method and circuit of the present invention uses the size of the dither table as the size of a plurality of types of unit dither tables that may be used. It is characterized by setting a common multiple and arranging a unit dither table of a size actually used on the dither table.

In the dither table address generating method of the present invention, the dither table having the above-mentioned size and in which the unit dither table of the size to be actually used is arranged, threshold value reading is performed by counting. It is characterized by generating an address for.

The dither table address generating circuit of the present invention has a counter for generating an address for reading a threshold value from the dither table by counting and a size of the above-mentioned and actually used size. A dither table in which unit dither tables are arranged is provided with a control circuit that controls a counter so that an address is generated.

The hard copy circuit of the present invention includes color information conversion means for converting the color of image information stored in the storage means into a color suitable for hard copy in a mode corresponding to the screen of the display device, and color information. The image information after conversion by the conversion means is set to N using the threshold value read from the dither table.
A dither modulation circuit that pseudo-increases the number of gradations of the image information by binarizing (N: plural), and means for hard-copying the image information whose gradation number is pseudo-increased by the dither modulation circuit , And the dither modulation circuit has a size set to a common multiple of the sizes of multiple types of unit dither tables that may be used, and the unit dither table of the actually used size is arranged on the dither modulation circuit. A dither table, a counter for counting in synchronization with color conversion of image information stored in the storage means, and a control circuit for controlling the counter to generate an address for reading a threshold value from the dither table. , Are included.

The present invention is characterized in that the size of the dither table is set to the least common multiple of the sizes of a plurality of types of unit dither tables that may be used.

[0020]

In the present invention, the size of the dither table is set to a common multiple of the sizes of a plurality of types of unit dither tables that may be used. The unit dither table corresponds to each dither table shown in FIG. 6, for example. Further, a unit dither table of a size to be actually used is arranged on this dither table. Since the size is set to a common multiple of the size of the unit dither table, when arranging the unit dither table of the size to be actually used, the unit dither table can be arranged uniformly and without any space on the dither table. Therefore, in the present invention, the control of the counting operation for reading the threshold value from the dither table is switched according to the number of gradations to be pseudo-added in the dither modulation, that is, the size of the unit dither table actually used. There is no need. As a result, the hardware scale can be reduced, and it is not necessary to instruct the firmware to switch the counting operation due to the change in the number of additional gradations. When the present invention is applied to a hard copy circuit such as a graphic display device, it is possible to obtain a hard copy having a large number of gradations with a small scale hardware. Also, change the size of the dither table
When the size is set to the least common multiple of the sizes of multiple types of unit dither tables that may be used, the above-mentioned effect becomes most remarkable.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. The same components as those in the conventional example shown in FIGS. 4 to 7 are designated by the same reference numerals and the description thereof will be omitted.

FIG. 1 shows the configuration of a system according to an embodiment of the present invention. The system shown in this figure is based on the graphic information transmitted from the host computer 10 and is the CRT 14 of the graphic display device 58.
Is a system that displays graphics on the screen.

The graphic display device 58 is similar to the conventional example in that the coordinate conversion device 16, the DDA 18, and the FB2.
0, a video signal converter 22 and a CRT 14. Further, the graphic display device 58 shown in this figure further includes a hard copy circuit 6 for making a hard copy of a graphic displayed on the screen of the CRT 14.
0, and the graphic information expanded on the FB 20 can be hard copied by the hard copy device 26 via the hard copy circuit 60.

The hard copy circuit 60 has a LUT 28 and a DMAC 30. LUT28 from above FB20
When the graphic information is DMA-transferred by the DMAC 30, the graphic information is color-converted by the LUT 28 into colors having Y, M and C as primary colors. The graphic information color-converted by the LUT 28 is dither-modulated by the dither modulation circuit 62 and then supplied to the hard copy device 26 via the I / F circuit 32. As a result, the graphic displayed on the screen of the CRT 14 is hard copied based on the graphic information developed on the FB 20.

The feature of this embodiment is the configuration of the dither modulation circuit 62. The dither modulation circuit 62 in this embodiment includes a dither table 64 for binarizing the graphic information on the LUT 28, and a counter 66 for reading a threshold value from the dither table 64. FIG. 2 shows the configuration of the counter 66 in more detail.

As shown in FIG. 2, the counter 66 is
It is composed of a control circuit 68 and an XY counter 46. Further, the control circuit 68 includes a 12 × 12 control unit 7
Has 0. DM from FB20 to LUT28
Upon receiving the notification from the DMAC 30 that the A transfer has started, the control circuit 68 activates the 12 × 12 control unit 70. The 12 × 12 control unit 70 generates a control signal accordingly and controls the counting operation of the XY counter 46. The XY counter 46 generates X and Y addresses according to the control signal, and addresses the dither table 64 with the obtained X and Y addresses. As a result, when the threshold value is read out from the dither table 64, the threshold value is used to determine 2 of the graphic information on the LUT 28.
The digitization is performed, and thereby the dither-modulated graphic information is obtained.

FIG. 3 shows the contents of the dither table 64 in this embodiment. The dither table 64 shown in this figure has a storage space 100 of 12 pixels in the X direction and 12 pixels in the Y direction. 3 × in this example
When it is attempted to add 8 gradations to the graphic information on the LUT 28 by averaging 3 pixels, FIG.
As shown in FIG. 3, the unit dither table 102 is evenly attached to the storage space 100 without any space. For example,
A unit dither table 102 having the same contents as the dither table shown in FIG.
Stick x 4 in Y direction = 16 pieces.

Further, in the case of averaging 4 × 4 pixels and adding 16 gradations in this embodiment, FIG.
As shown in (b), the X direction 3 is set on the storage space 100.
Pieces × 3 in Y direction = 9 unit dither tables 104 are attached uniformly and without gaps. The content of the unit dither table 104 to be pasted is, for example, the content shown in FIG.

The dither table 64 is thus 12 × 1
In this embodiment, the size of each unit dither table (102, 104, etc.) having the necessary contents is evenly and without gaps, so that the control unit of the control circuit 68 controls 12 × 12. Unit 70
It only needs to be used. That is, it is not necessary to provide a plurality of control units corresponding to dither tables of different sizes as in the conventional case, and only the 12 × 12 control unit 70 can be used to read the X and Y values required to read the threshold values from the dither table 64. Addresses can be generated. Therefore, it is not necessary to set the number of additional gradations in the control circuit 68 from the firmware. As a result, according to the present embodiment, it is possible to obtain a hard copy having a gradation number equal to or higher than that of the conventional one with a smaller scale hardware. That is, a hard copy can be obtained at a lower cost.

Although the above description shows an example in which the 3 × 3 unit dither table 102 is pasted on the 12 × 12 storage space 100 and an example in which the 4 × 4 unit dither table 104 is pasted. In this way, when the storage space 100 of 12 × 12 is provided, the unit dither table of 1 × 1 and the unit dither table of 2 × 2 can be attached uniformly and without a gap. Moreover, the size of the storage space 100 of the dither table 64 is not limited to 12 × 12. For example, when it is sufficient to prepare only three types of gradations to be added, that is, 2, 4, and 8,
3 each with a size of 1x1, 2x2 or 3x3
Prepare different types of unit dither tables, dither table 6
As the storage space 100 of 4, it is sufficient to prepare a storage space having a size related to a common multiple of the sizes of these three types of unit dither tables, for example, a size of 6 × 6 which is the least common multiple. Further, in the above description, the size of the storage space 100 of the dither table 64 is the least common multiple of the sizes of the 3 × 3 unit dither table 102 and the 4 × 4 unit dither table 104 related to the number of additional gradations to be realized. Although it is set to 12, it does not have to be the least common multiple.
Of course, by setting the least common multiple, dither table 6
The storage space 100 of 4 can be the smallest, and the structure of the counter 66 can also be the smallest.

[0031]

As described above, according to the present invention,
The size of the dither table is set to a common multiple of the size of the multiple types of unit dither tables that may be used, and the unit dither table of the actually used size is arranged on the dither table. The control of the counting operation for reading the threshold value from the
That is, there is no need to switch according to the size of the actually used unit dither table. As a result, the hardware scale can be reduced, and it is not necessary to instruct the firmware to switch the counting operation according to the change in the number of additional gradations. When the present invention is applied to a hard copy circuit such as a graphic display device, it is possible to obtain a hard copy having a large number of gradations with a small scale hardware. Further, when the size of the dither table is set to the least common multiple of the sizes of the plurality of types of unit dither tables that may be used, the above effect becomes most remarkable.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a counter in this embodiment.

FIG. 3 is a diagram showing the contents of a dither table in this embodiment, and in particular, (a) shows an example in which a 3 × 3 unit dither table is evenly and closely attached on a 12 × 12 dither table, (B) is a figure which respectively shows the example which stuck the unit dither table of 4x4 on the 12x12 dither table uniformly and without a space | gap.

FIG. 4 is a block diagram showing a configuration of a system according to a conventional example.

FIG. 5 is a block diagram showing a configuration of a counter in this conventional example.

FIG. 6 is a diagram showing the contents of a dither table in this conventional example, in particular (a) is a 1 × 1 dither table,
FIG. 7B is a diagram showing a 2 × 2 dither table, FIG. 8C is a diagram showing a 3 × 3 dither table, and FIG. 8D is a diagram showing a 4 × 4 dither table.

FIG. 7 is a diagram showing an implementation example of a dither table in this conventional example, in particular, (a) shows an example in which a 1 × 1 dither table is pasted on a part of a 4 × 4 storage space, (b) Is 2
An example in which a × 2 dither table is pasted on a part of a 4 × 4 storage space is shown in (c), and a 3 × 3 dither table is 4 × 4.
(D) is an example in which a 4 × 4 dither table is pasted in a 4 × 4 storage space.
It is a figure which respectively shows.

[Explanation of symbols]

 10 host computer 14 CRT 16 coordinate conversion device 18 digital differential analyzer (DDA) 20 frame buffer (FB) 22 video signal converter 26 hard copy device 28 look-up table (LUT) 30 direct memory access controller (DMAC) 32 interface ( I / F) circuit 46 XY counter 58 graphic display device 60 hard copy circuit 62 dither modulation circuit 64 dither table 66 counter 68 control circuit 70 12 × 12 control unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 1/40 C

Claims (6)

[Claims] 1. An address for reading a threshold value from a dither table is generated by counting, a threshold value corresponding to the generated address is read from the dither table, and the image information is read by N using the read threshold value. In the dither modulation method in which the number of gradations of the image information is pseudo-increased by the binarization (N: plural), the size of the dither table is set to the size of the plural types of unit dither table that may be used. A dither modulation method characterized by setting to a common multiple and arranging the unit dither table of the size actually used on the dither table. 2. A dither table having a size set to a common multiple of the sizes of a plurality of types of unit dither tables that may be used, and a unit dither table of an actually used size arranged on the dither table. A counter for generating an address for reading the threshold value from the dither table by counting, and a threshold value corresponding to the generated address is read from the dither table, and the read threshold value is used to convert the image information into N-value ( N: a plurality of N-valued circuits, and a dither modulation circuit characterized by increasing the number of gradations of the image information in a pseudo manner. 3. A dither table address generation method for generating an address for reading a threshold value from a dither table by counting, wherein the dither table is set to a common multiple of the sizes of a plurality of types of unit dither tables that may be used. An address generating method for a dither table, characterized in that an address is generated by counting for a dither table having a size and a unit dither table of a size to be actually used arranged thereon. 4. A dither table address generation circuit comprising a counter for generating an address for reading a threshold value from a dither table by counting, to a common multiple of the sizes of a plurality of types of unit dither tables that may be used. For a dither table that has a set size and on which a unit dither table of the size to be actually used is arranged, an address is generated,
A dither table address generation circuit comprising a control circuit for controlling a counter. 5. A color information conversion means for converting the color of the image information stored in the storage means into a color suitable for hard copy in a mode corresponding to the screen of the display device, and a color information conversion means after conversion by the color information conversion means. A dither modulation circuit that pseudo-increases the number of gradations of the image information by converting the image information into N-values (N: plural) using the threshold value read from the dither table, and the gradation by the dither modulation circuit. Means for making a hard copy of the image information whose number is pseudo increased,
The dither modulation circuit stores a threshold value for N-valued (N: plural) the image information converted by the color information conversion unit, and a color of the image information stored in the storage unit. The size of the dither table can be used in a hard copy circuit that has a counter that counts in synchronization with conversion and a control circuit that controls the counter to generate an address for reading a threshold value from the dither table. A hard copy circuit, which is set to a common multiple of the sizes of various types of unit dither tables, and unit dither tables of sizes actually used are arranged on the dither table. 6. The method or circuit according to claim 1, wherein the size of the dither table is set to the least common multiple of the sizes of a plurality of types of unit dither tables that may be used. Or circuit.