KR100469284B1 - Device for controling buffer bank of digital TV - Google Patents

Abstract

The present invention relates to a digital TV, and more particularly, to a buffer bank control apparatus for a digital TV, in which a plurality of buffer controllers are integrated to share a buffer, thereby enabling efficient hardware configuration and use. In the digital TV having an external memory for the operation of the functional blocks, A plurality of buffer units for storing divided data in consideration of the processing capacity of the plurality of functional blocks and the external memory; Dividing the used buffer in bank units of the available bank It has a structure of a buffer bank that can change the number, control the buffer bank by multi-buffer addressing according to the input and output flow of data, adjust the read and write requests between the function block and external memories, and control the buffer status Adjusting the reference position of occurrence of the signal (FULL / EMPTY) A buffer bank control unit is included.

Description

Device for control buffer bank of digital TV

The present invention relates to a digital TV, and more particularly, to a buffer bank control apparatus for a digital TV, which enables a plurality of buffer controllers to share a buffer so that efficient hardware configuration and use are possible.

In the data broadcasting, the transmitting side transmits additional data information in addition to the TV A / V stream so that information other than the broadcasting program can be viewed through the screen.

In addition, by attaching a high-speed memory device such as a hard disk to the digital TV to record and play the received broadcast information, after recording the program being broadcast without a separate recording device, the recorded broadcast program can be played and viewed. Doing.

In this way, various types of images are input and output. In order to convert the original image into the size of the desired image, data must be stored using a memory. This memory stores data through the buffer and reads the stored data using the buffer to display an image.

As a method for converting the original image, the image data is stored in the memory, and the data is read and converted, and then stored in the memory. The converted image data is read from the memory and displayed immediately.

Alternatively, the original image is stored in memory, and the data is read and converted at the same time. At this time, when the clock used for the memory is displayed faster than the displayed clock, the converted image can be made.

Hereinafter, a memory and memory control of a digital TV according to the related art will be described with reference to the accompanying drawings.

1 is a block diagram of a conventional buffer and a buffer control unit.

Digital TVs are required to handle a variety of inputs and outputs, and functional blocks are designed to meet these needs, some of which operate without the use of external memory.

In addition, some functional blocks are read / write of data between external memories according to various individual timings and rules.

When data is read / written between the functional block and the external memory as described above, the buffer is used as an interface means between the functional block and the memory to refer to various signals indicating the state of the functional block and the memory to control the input / output of the data. do.

Each of the functional blocks is configured by assigning respective buffers 11a, 11b, 11c, 11d, 11e, and 11f, and a buffer control unit 12a for requesting reading and writing to each of the buffers. 12b, 12c, 12d, 12e, and 12f are allocated to control data input and output of the external memory.

Here, each of the buffer controllers 12a, 12b, 12c, 12d, 12e, and 12f is not only the state of the corresponding buffers 11a, 11b, 11c, 11d, 11e, and 11f. It is important to know the state of the functional blocks and external memory.

Otherwise, if a data request is made, new data may be introduced into or out of the buffer without all of the data in the buffer being processed, that is, some data is lost.

Here, the function block makes an external memory occupation request to the external memory controller during its timing period through the buffer controller, and the external memory controller accesses the memory by accepting / rejecting the request.

As the number of functional blocks increases, the external memory controller sets a certain rule such as priority for each read / write request and processes the requests in order.

The size of the buffer is determined in consideration of the data processing capacity of the functional block and external memory and the frequency of read / write requests of the functional block. Since the size of the buffer is directly connected to the hardware size, the most optimized size should be determined. .

As the number of functional blocks that use external memory increases, the number of buffers also increases, and the number of individual buffer controllers also increases. This represents an increase in hardware.

The memory and memory control apparatus of the digital TV of the prior art will be described in more detail as follows.

Conventional digital TVs include a memory, a buffer for storing data to be read and written between functional blocks, a write controller for transferring data stored in the buffer to the memory, and a read controller for transferring data stored in the buffer to the functional block. do.

The read control unit and the write control unit send a "FULL" or "EMPTY" signal indicating the state of the buffer to the memory control unit, and the memory control unit refers to the "buffer access signal" or "memory access disable signal" referring to the "buffer status signal". To control the memory occupancy request.

In this way, the function block handles the data stored in the buffer without loss.

However, the memory control apparatus according to the related art described above has the following problems.

First, as the number of functional blocks using external memory increases, the number of buffers also increases, and each functional block cannot use each other's buffers in common.

That is, when a specific function block does not operate, the currently allocated function block cannot use the buffer allocated to this block.

Second, while the memory controller processes a plurality of memory occupancy requests, a buffer that has not been processed for its request during a given timing interval loses data in the buffer. In order to prevent such a situation, Constraints are placed on the operation of the block.

There is a limitation in using the memory efficiently because the memory is controlled based on the limitation of the memory usage and only whether the data is full or empty in the buffer.

The present invention has been made to solve the problems of the conventional memory control device, a digital TV buffer bank that allows the efficient configuration and use of hardware by integrating a plurality of buffer control unit to share the buffer The object is to provide a control device.

1 is a block diagram of a buffer and a buffer control unit of the prior art

2A and 2B are diagrams illustrating a buffer bank addressing method

3 is a configuration diagram of a buffer bank and parameters

4 is a configuration diagram of a buffer bank and a buffer bank control unit according to the present invention.

5 is a configuration diagram when deforming to a four bank structure

6 is a configuration diagram when deforming to a six-bank structure

Explanation of symbols for the main parts of the drawings

41. Buffer bank control

42a.42b.42c.42d.42e.42f. Buffer section

The digital TV buffer bank control apparatus according to the present invention for achieving the above object in the digital TV having a plurality of functional blocks and an external memory for the operation of the functional block, processing capacity of the plurality of functional blocks and the external memory A plurality of buffer units for storing divided data in consideration of the above; By having a structure of a buffer bank that can be used to divide the buffer used in bank units to vary the number of available banks, by multi-buffer addressing in accordance with the flow of data input and output And a buffer bank controller for controlling a buffer bank, adjusting read and write requests between a function block and external memories, and adjusting a reference position of a signal FULL / EMPTY indicating a buffer status. .

Other objects, features and advantages of the present invention will become apparent from the following detailed description of the embodiments.

A preferred embodiment of a digital TV buffer bank control apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

2A and 2B are diagrams illustrating a buffer bank addressing method, and FIG. 3 is a diagram illustrating buffer banks and parameters.

4 is a configuration diagram of a buffer bank and a buffer bank controller according to the present invention.

The present invention relates to the control of a buffer control device between a plurality of functional blocks for processing digital broadcasting and an external memory, and simplifies the hardware structure by integrating a buffer control device between blocks having different timing characteristics of memory read / write. In addition, the buffer built in each block is shared.

SD-level signals such as NTSC / PAL broadcast signals operate before and after format conversion to improve image quality, and in most cases, functional blocks operate using external memory and buffers to improve image quality. .

These functional blocks will not work for HD signals, so they will waste a lot of hardware without sharing buffers.

In addition, the format converter may experience excessive memory local bandwidth when performing various format conversions on the HD signal. When the unused buffer is used as the format converter's buffer, the format converter uses external memory. This can be done efficiently.

The present invention considers such matters, and includes a buffer control unit for common use of a plurality of buffers allocated to a plurality of functional blocks.

Specifically, as shown in FIG. 4, a control block for controlling a buffer bank, addressing read and write requests between a function block and external memories using addressing of multiple buffers in accordance with an input / output flow of data according to an external signal. A buffer bank controller 41 having a control block, a control block for adjusting a reference position of a signal indicating a buffer status such as FULL and EMPTY to a reference position determined through a register input from an external host, and a plurality of functional blocks; And a plurality of buffer sections 42a, 42b, 42c, 42d, 42e and 42f for storing divided data in consideration of the processing capacity of the external memory.

Here, the "buffer bank" means a buffer structure having a buffer unit and a control unit as components.

Such a buffer bank control apparatus of a digital TV according to the present invention can programmatically adjust parameters and a buffer structure of a buffer control unit to an external register, and adjust a memory local bandwidth that can be generated at any time using a freely adjustable buffer structure. Can be.

As shown in FIG. 2, the single buffer addressing method divides the divided buffer into banks by taking a dichotomy for one buffer.

For example, as shown in FIG. 2B, the buffer divided by the [64 address] * [64 bit] buffer is divided into [32 address] * [64 bit] * 2.

To access bank 0 and bank 1, one-bit bank address (BANK ADDR.) And five-bit data address (DATA ADDR.) Are used.

In the method of addressing multiple buffers, a buffer address for accessing a plurality of buffers is defined so that each bank can be accessed as shown in FIG. 2A by combining a bank address and a data address mentioned in the method of addressing a single buffer. .

FIG. 2A illustrates an addressing method when applied in a two bank structure using one buffer, in a four bank structure using two buffers, and in a six bank structure using three buffers.

Here, a bank structure is defined as a "buffer bank" by dividing a generally used buffer into banks so that unused banks can be used to vary the number of available banks.

As shown in FIG. 3, the buffer transmits the FULL and EMPTY signals to the memory controller to indicate its status, and adjusts to which register the host registers the FULL and EMPTY signals at which bank position in the buffer bank structure. It effectively adjusts memory local bandwidth.

FIG. 5 is a configuration diagram when deforming into a four bank structure, and FIG. 6 is a configuration diagram when deforming into a six bank structure.

According to the present invention, when some of the functional blocks using the buffer are not used, the buffer allocated to the functional block is allocated to the functional block using the current buffer to enable adjustment of the memory local bandwidth. FIGS. 5 and 6 As described above, the four bank structure and the six bank structure of the bank structures that can be assumed to have six buffers are represented.

Such a buffer bank control apparatus for a digital TV according to the present invention exceeds the memory local bandwidth caused by using a buffer that is not used by some function blocks in a structure in which a plurality of function blocks use a plurality of buffers. Reduce and integrate multiple buffer controllers to make buffer sharing more efficient and simple.

The digital TV buffer bank control apparatus according to the present invention has the following effects.

First, in designing a plurality of buffer controllers, it is possible to minimize the complexity of the design that can occur by using a single buffer controller for overlapping blocks.

In addition, even if there is an increase in functional blocks using an external memory, it is not necessary to increase the number of buffers and the buffer control unit.

This makes it possible to remove unnecessary hardware, thereby reducing the manufacturing cost.

Second, the function control of the buffer controller can be implemented as programmable access using registers to make the most of the functions of the buffer bank.

Third, in a structure with many asynchronous buffers having different read clocks and write clocks, the buffers can be efficiently controlled and the memory local bandwidth can be effectively adjusted.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (5)

In the digital TV having a plurality of functional blocks and external memory necessary for the operation of the functional blocks, A plurality of buffer units for storing divided data in consideration of the processing capacity of the plurality of functional blocks and the external memory; The buffers used can be divided into bank units to have a buffer bank structure that can vary the number of available banks. The buffer bank is controlled by multiple buffer addressing according to the input / output flow of data, the read and write requests between the function block and external memories, and the reference position of the generation of the signal (FULL / EMPTY) indicating the buffer status are adjusted. And a buffer bank controller for controlling the digital TV buffer bank. The buffer bank control unit of claim 1, wherein the buffer bank controller outputs a signal related to a buffer state (FULL / EMPTY), a memory occupancy request enable / disable signal, and a signal related to buffer bank mode control so that the functional blocks can share the buffer units. The buffer bank control device of the digital TV. The apparatus of claim 1, wherein the buffer units transmit signals related to their states (FULL / EMPTY signals) to a memory control block of the buffer bank controller. 2. The digital TV buffer bank control apparatus according to claim 1, wherein the buffer bank control unit adjusts, through a register input of the host, at which bank position to generate the FULL and EMPTY signals in order to adjust the memory local bandwidth. 2. The apparatus of claim 1, wherein the multi-buffer addressing is a combination of a bank address and a data address to access each bank.