JPH10307790A - High-speed processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To structure a new system which can be constituted at a low cost and can use a bus efficiently by connecting each bus slave to one of buses which has corresponding transfer capability and connecting bus masters directly to the address buses and data buses of the respective buses. SOLUTION: The respective bus slaves 20 and 21 are connected to the buses 10 and 11 which have corresponding transfer capability or operation speeds corresponding to response speeds. The bus masters 1 and 2 are connected directly to the address buses and data buses of the buses 10 and 11. Consequently, a decrease in the use efficiency of the buses 10 and 11 due to the coexistence of the bus slaves 20 and 21 differing in data transfer capability is prevented to actualize the efficient use of the buses 10 and 11. Further, the problem that the data transfer width of the bus 10 with high transfer capability is consumed by the bus 11 with low transfer capability in hierarchical bus system is solved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video game device, a communication network information device, a portable information device,
The present invention relates to a high-speed processor used in communication karaoke equipment, car navigation equipment, educational toys, learning teaching equipment, word processors, practical information providing equipment, inspection equipment used in factory production lines, and various measuring equipment.

[0002]

2. Description of the Related Art Conventionally, there are many multiprocessor systems in which a plurality of processors (bus masters) share and cooperate to perform processing. In such a system, there are many configurations in which a plurality of processors (bus masters) share a single bus and resources connected to the bus. Here, the resources connected to the bus refer to devices that receive addresses, such as memory devices, input / output control devices, and other functional blocks. In the present specification, these are referred to as bus slaves with respect to the bus master that issues addresses. As described above, a system in which a plurality of processors (bus masters) share resources has great advantages in that the system is simplified by sharing resources and the efficiency of the system is reduced by reducing the need for data transfer between resources. .

However, in recent years, the performance of the processor (bus master) has been remarkably improved, and the speed difference between the processor (bus master) and the memory device has widened. Is coming. Many systems use a high-speed cache memory or the like to reduce this bottleneck.

In a multiprocessor system having a shared bus, the period during which each processor (bus master) can use the shared bus is a single processor (bus master).
This bottleneck is more of a problem, as it is less than in systems with only one. In many systems, a cache memory inside a processor (bus master) and a local memory occupied by each processor (bus master) are actively introduced to reduce the need for data transfer using a shared bus as much as possible. ing.

As another method for solving this bottleneck, a processor (bus master) may include a plurality of external buses. A known example is a Harvard architecture processor in which a bus for instruction acquisition and a bus for data access are separated. Alternatively, there is an example of a processor in which a memory access bus and an input / output control bus are separated.

[0006] In a single bus system, all bus slaves are connected to this bus. However, if there are mixed bus slaves having different response speeds (access speeds) and data bus widths, the buses are not connected. Use efficiency will decrease.

Therefore, as shown in FIG. 16, there is a system in which a plurality of buses having different data transfer capacities are provided and bus slaves corresponding to the respective transfer capacities are connected to increase the bus utilization efficiency. In this specification, the data transfer capability of the bus means a value which is compared by a product of a bus cycle frequency and a bit width of the data bus. As an example of such a system in which a plurality of buses are provided for each data transfer capability, there is a hierarchical bus system often found in personal computers and workstations.

Recent PCs equipped with an Intel Pentium processor as a CPU (Central Processing Unit) /
Taking an AT compatible machine as an example, a processor external bus having a bus cycle frequency of 60 MHz or 66 MHz and a data bus width of 64 bits, a PCI bus having a bus cycle frequency of 33 MHz and a data bus width of 32 bits, and a bus cycle frequency of around 10 MHz. Generally, there are provided three buses having different data transfer capabilities of an AT bus having a data bus width of 8 bits.

A semiconductor memory such as a DRAM is connected to an external bus of a processor, a peripheral device such as a graphic processing device which requires high-speed data transfer is connected to a PCI bus, and a peripheral device such as a magnetic memory is used to transfer data at a relatively low speed. The device is AT
Connected to the bus.

In this system, the CPU directly controls the bus as a bus master only with respect to the processor external bus (high-speed first bus), and the PCI bus (low-speed second bus) and the AT. As for the bus (third low-speed bus), an inter-bus interface device mediates data transfer. Generally, an inter-bus interface device that interfaces between a processor external bus (high-speed first bus) and a PCI bus (low-speed second bus), a PCI bus (low-speed second bus), and an AT And a bus-to-bus interface device for interfacing between buses (third low-speed bus). In this system, access to the lower bus is performed via the upper bus.

In a system in which a plurality of processors (bus masters) share a bus and a bus slave, a system for bus arbitration is indispensable. This is because the bus is shared in a time-division manner, and when focusing on a certain point in time, only one processor (bus master) can use the bus.

Generally, a processor (bus master) issues a bus use request to a bus arbitration circuit, and the bus arbitration circuit performs arbitration based on the bus use request. A method of using a bus after receiving a bus use permission is often used.

[0013]

However, in the above-described system, the other bus and the bus slave are occupied by the one bus master until one bus master releases the bus by itself or for a predetermined period. Will be done.

In particular, in a multiprocessor system having a plurality of bus masters, if the use efficiency of the shared bus deteriorates, there is a problem that the processing capability of the entire system is lowered.

In a system using a cache memory, a local memory, or the like, which is often used in the prior art, it is difficult to configure the system at low cost.

The cache memory not only needs to be composed of a high-speed memory element, but also a memory element for storing address information in addition to a memory element for storing data, and the contents of a cache memory and a memory device on a shared bus. Therefore, a control circuit or the like for keeping the same is required, and the whole system becomes expensive and complicated.

Also, the cache memory and the local memory often hold the same data as the memory device on the shared bus, and the same data is held redundantly among a plurality of memory devices. This was undesirable in terms of effective utilization of

The present invention solves a bottleneck in data transfer between a bus master and a bus slave by increasing the use efficiency of a shared bus as much as possible without using a technique such as a cache memory. With the goal.

When a single shared bus is used, all bus slaves having different data transfer capabilities are connected to this bus. This means that the total amount of data transfer on the bus is low, which is one of the factors that hinders efficient use of the bus. In view of this point, separating the shared bus into a plurality of buses having different data transfer capabilities and connecting bus slaves corresponding to each data transfer capability is an effective means for achieving efficient use of the bus. It is. However, the known hierarchical bus system has the problem that the upper data transfer width must be consumed to access the lower bus. In the inter-bus interface device, a function for controlling a lower-side bus as a bus master, and a FIFO (first / first) for absorbing a difference in data transfer capability of the bus are provided.
In many cases, an (in-first-out) memory or the like is used, which is not suitable for a system intended to be inexpensive.

Therefore, according to the present invention, it is possible to construct a new system which can be constructed at a low cost and can use the bus efficiently, without using the conventionally known hierarchical bus system. Aim.

Another object of the present invention is to provide a high-speed processor which is inexpensive but has the highest possible performance.

Focusing on the arbitration method, there are many existing arbitration methods in which a processor (bus master) occupies and uses a bus during a certain period of time. In such an arbitration method, during a period in which the processor (bus master) is performing an internal operation or a period in which the processor (bus master) is accessing the internal cache memory or the like, the processor (bus master) does not actually use the bus. Regardless, other processors (bus masters) cannot use the bus. Further, the bus cycle speed depends on the bus cycle speed of the processor (bus master) to which the right to use the bus has been given. If a low-speed processor (bus master) occupies the bus, the bus use efficiency is reduced. Accordingly, it is another object of the present invention to realize efficient use of a bus by adopting a unique bus arbitration method.

[0023]

Means for Solving the Problems The present invention has been made to achieve the above-mentioned object, and a first aspect of the present invention is to provide at least one bus master and a plurality of bus masters having different data transfer capabilities. A bus, and a plurality of bus slaves according to a transfer capability of each of the buses, wherein each of the bus slaves includes:
Each of the buses is connected to any of the buses having a corresponding transfer capability, and each of the buses has an independent address bus and a data bus. A high-speed processor characterized by being directly connected to a bus and a data bus.

According to a second aspect of the present invention, there is provided at least one bus master, a plurality of buses having different operation speeds, and a plurality of bus slaves capable of responding at a speed corresponding to the operation speed of each bus. A bus slave connected to any one of the buses having an operation speed corresponding to the response speed thereof, wherein each of the buses has an independent address bus and a data bus; Are directly connected to the address bus and the data bus of each of the buses.

Further, a third aspect of the present invention includes a plurality of bus masters, a plurality of buses having different data transfer capacities, and a plurality of bus slaves corresponding to the transfer capacities of the respective buses. Each of the buses is connected to one of the buses having a corresponding transfer capability, and each of the buses has an independent address bus and a data bus. A high-speed processor, which is directly connected to an address bus and a data bus, and further includes a bus arbitration circuit for arbitrating access to the bus from the plurality of bus masters for each of the buses. Things.

Still further, a fourth aspect of the present invention includes a plurality of bus masters, a plurality of buses having different operation speeds, and a plurality of bus slaves which can respond at a speed corresponding to the operation speed of each bus. A bus slave is connected to each of the buses having an operation speed corresponding thereto, and each of the buses has an independent address bus and a data bus, and each of the bus masters has A bus arbitration circuit that is directly connected to an address bus and a data bus of each of the buses, and further includes a bus arbitration circuit that arbitrates access to a bus from a plurality of the bus masters for each of the buses. The gist is a processor.

The bus master has a function of outputting a bus use request signal to the bus arbitration circuit, a function of waiting for access to the bus until a bus use permission signal is obtained, and sending an address to the bus. It is preferable to use a function having an independent interface for each of the connected buses, and having an independent interface for each of the connected buses.

As the interface, a plurality of sets of three-state buffers independent of each bus for controlling output / non-output of an address to the bus, and control of data input / output and connection / non-connection to the bus are provided. A plurality of sets of bidirectional 3-state buffers independent for each bus;
A device including means for controlling the three-state buffer based on the bus permission from the bus arbitration circuit may be used.

As the processor, at least one of the means for issuing a logical address inside the processor, a decoder for decoding the issued logical address, and one of a plurality of buses based on the decoded address information. Means for selecting one of them and outputting a bus use request signal; means for selecting only necessary address information from the logical addresses to generate a physical address; or means for converting a logical address to generate a physical address; A plurality of sets of three-state buffers for outputting generated physical addresses to a bus, whereby a plurality of independent physical address spaces are assigned to a part of a single logical address space for each bus. It is desirable that it is what was done.

As the bus arbitration circuit, the shorter of the fastest time during which the bus slave can be accessed and the fastest time during which the bus is operable is defined as the bus cycle time, and the bus arbitration circuit always determines the bus cycle time. The processor has a function of determining a bus use right and giving a bus use permission to a processor only in units of one bus cycle, and the processor has a function of transmitting and receiving data within the bus cycle period. It is desirable to have one.

Further, the bus arbitration circuit comprises: priority information storage means for storing a plurality of sets of bus master priority information, each of which includes a set of bus master priority information defining the priorities of the bus masters; Priority information selecting means for sequentially selecting one set of the bus master priority information for each bus cycle using a plurality of sets of bus master priority information as a repetition unit; and one set of the priority selected by the selection means A bus use permission signal for outputting a bus use permission signal for permitting use of the bus by one bus cycle to the bus master having the highest priority among the bus masters requesting the use of the bus, based on the rank information. It is desirable to have a generating circuit.

Further, all the above-mentioned components may be integrated in a single semiconductor device.

The processor includes one or a plurality of central processing units, a processor having means for performing graphic processing and generating a video signal, and a processor having means for performing sound processing and generating an audio signal. A first bus which controls data transfer and exchange between a functional block inside the semiconductor device and a high-speed semiconductor memory, and a second bus which controls data transfer and exchange between a peripheral device outside the semiconductor device and a low-speed semiconductor memory as the bus. A bus that includes a semiconductor memory connected to the first bus as the bus slave; and a bus that arbitrates the first bus as the bus arbitration circuit.
And a second bus arbitration circuit for controlling arbitration of the second bus.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The basic concept of a high-speed processor according to the present invention will be described below with reference to FIG.

As shown in FIG. 1, this system includes one or a plurality of bus masters (1) and (2) and a plurality of buses (10) and (11) having different data transfer capacities or operation speeds.
And a plurality of bus slaves (20) (21) capable of responding at a speed corresponding to the transfer capacity or operation speed of each bus.
And

Each of the bus slaves (20) and (21)
Any one of the buses (10) (1) having a transfer capacity corresponding thereto or an operation speed corresponding to the response speed thereof.
1). Here, each of the buses (10) and (11) has an independent address bus and data bus. The bus masters (1) and (2) are directly connected to the address bus and the data bus of each of the buses (10) and (11). Here, the term "directly connected" in this specification refers to FIG.
6, each of the bus masters (1) and (2) is connected to each bus (1) without passing through an inter-bus interface interposed between the buses as in the conventionally known hierarchical bus system shown in FIG.
0) means that they are connected to (11). Needless to say, the bus master (1) (2) and the bus (1)
0) and (11) are connected via a conventionally known interface, and this interface has an extremely simple configuration compared to the inter-bus interface.

Further, each of the buses (10) and (11) is provided with a bus arbitration circuit (not shown) for arbitrating access to the bus from the plurality of bus masters (1) and (2). However, when a single bus master is used, the bus arbitration circuit is basically unnecessary.

The bus masters (1) and (2) provide a function of outputting a bus use request signal to the bus arbitration circuit, a function of waiting for access to the bus until a bus use permission signal is obtained, It has a function of transmitting an address to a bus and a function of completing data transmission / reception within a bus cycle period determined by a bus arbitration circuit. An independent interface (not shown) is provided for each.

The interface includes a plurality of independent sets of three-state buffers for controlling output / non-output of addresses to the buses (10) and (11), and data for the buses (10) and (11). A plurality of sets of bidirectional three-state buffers independent of each bus for controlling input / output and connection / disconnection of the bus, and means for controlling the three-state buffers based on permission of bus use from the bus arbitration circuit. .

At least one of the bus masters (1) and (2) includes means for issuing a logical address inside the bus master, a decoder for decoding the issued logical address, and a plurality of bus masters based on the decoded address information. Means for outputting a bus use request signal by selecting one of the above, means for selecting only necessary address information from logical addresses to generate a physical address, or converting a logical address to generate a physical address And a plurality of sets of three-state buffers for outputting the generated physical addresses to the bus, whereby a plurality of independent physical address spaces for each bus can be stored in a single logical address space. Partially assigned.

The bus arbitration circuit determines the shorter of the fastest time during which the bus slaves (20) and (21) can be accessed and the fastest time during which the bus can operate as a bus cycle time. The bus master (1) (2) is provided with a function of always determining a bus use right for each bus cycle and granting the bus masters (1) and (2) use of the buses (10) and (11) only in units of one bus cycle. ) Has a function of transmitting and receiving data within the bus cycle period.

Further, the bus arbitration circuit comprises: priority information storage means for storing a plurality of sets of bus master priority information, each of which includes a set of bus master priority information defining priorities among the bus masters; Priority information selecting means for sequentially selecting one set of the bus master priority information for each bus cycle using a plurality of sets of bus master priority information as a repetition unit; and one set of the priority selected by the selection means A bus use permission signal for outputting a bus use permission signal for permitting use of the bus by one bus cycle to the bus master having the highest priority among the bus masters requesting the use of the bus, based on the rank information. And a generation circuit.

By the way, all the above-mentioned components, that is, all the components including the bus masters (1) and (2), the buses (10) and (11) and the bus slaves (20) and (21) are as follows.
Integrated within a single semiconductor device.

The high-speed processor according to the present invention has different data transfer capabilities as described above in order to solve a bottleneck in data transfer between the bus masters (1) and (2) and the bus slaves (20) and (21). Multiple buses (10)
(11), and a method in which the bus masters (1) and (2) directly access these buses (10) and (11). As a result, it is possible to prevent a decrease in bus use efficiency due to a mixture of bus slaves (20) and (21) having different data transfer capacities, and to realize efficient bus use.

Further, the problem that the data transfer width of the high transfer capacity bus (10) seen in the hierarchical bus system is consumed by the low transfer capacity bus (11) is also solved. Further, no special circuit is required as a device for interfacing between the buses (10) and (11), so that the system can be configured at low cost.

Further, when a plurality of bus masters (1) and (2) request to use the same bus at the same time, the right to use the bus is determined independently for each bus, so that the bus master (1) (2) uses only the bus for which use is granted and does not occupy another bus.
Therefore, the opportunity for the bus master to occupy the unused buses and bus slaves is reduced, and the bus use efficiency can be further improved.

As the bus arbitration circuit, the bus use permission is determined for each bus cycle, and the bus use permission is given to the bus master only in units of one bus cycle, so that the bus cycle always performs effective access. The bus master is dynamically allocated to the bus master, so that the bus master does not occupy the bus during periods when the bus is not used for internal operations or the like.

Further, if the bus cycle speed is determined by the bus arbitration circuit, the bus arbitration circuit can be made independent of the bus cycle speed of the bus master. Therefore, even when there is a speed difference in the bus cycle between the bus masters, the bus can always operate at the maximum speed. When the bus cycle speed of the bus master is low, the difference between the bus cycles may be buffered by, for example, providing a read buffer and a write buffer on the data bus or delaying the output of the bus use request signal.

By arranging the physical address spaces of a plurality of buses in a single logical address space, not only can the physical address spaces of all buses be handled in a unified manner, but also A data block as a processing unit can be arranged so as to straddle the physical address space of a plurality of buses, and programming becomes easier and more flexible.

[0050]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an example of a central processing unit according to the present invention will be described.

This central processing processor is one of a plurality of bus masters constituting the high-speed processor according to the present invention. The central processing unit has a function of accessing two sets of shared buses, a first bus and a second bus.

The first bus is a 16-bit address bus,
This is a shared bus composed of a read / write signal and an 8-bit data bus, and accesses from a plurality of bus masters are arbitrated by a first bus arbitration circuit. This is a high-speed bus with one cycle of a clock signal as one bus cycle.
It is mainly used for high-speed access to semiconductor memories and data transfer between functional blocks inside a high-speed multiprocessor.

The second bus is a 24-bit address bus,
This is a shared bus comprising a read / write signal and an 8-bit data bus, and accesses from a plurality of bus masters are arbitrated by a second bus arbitration circuit. This is a relatively low-speed bus having one to two to eight cycles (however, an integer) of a clock signal, and is mainly used for accessing a low-speed semiconductor memory and transferring data with a device external to a high-speed multiprocessor. . The setting of the number of clock cycles per bus cycle is controlled by a second bus cycle length control register included in the external memory interface circuit.

FIG. 2 shows an outline of the main part of the central processing unit. This central processing unit includes a processor core (50), an address decoder (51), a first bus interface control means (52), a second bus interface control means (53), a clock control means (54),
Sets of three-state buffers (55) and (60), two sets of bidirectional three-state buffers (56) and (61), a peripheral function block (57), an internal address bus and a read / write signal (58), and an internal data bus (59) ).

The processor core (50) controls various operations and controls the entire system according to a program stored in the memory. Operated by a clock signal input from a clock control means (54), a 24-bit address bus,
It has a read / write signal and an 8-bit data bus as bus interface signals. Further, it has a function of outputting an access valid signal synchronized with its own bus cycle and notifying the outside of the processor core (50) that the bus interface signal is invalid during an internal operation cycle.

The address bus and read / write signal connected to the processor core (50) are connected to the internal address bus and read / write signal (58), and the data bus is connected to the internal data bus (59). , First
It is not directly connected to the bus and the second bus. Hereinafter, it is assumed that the space of the internal address bus is treated as a logical address space as viewed from a program, separately from the physical address space of the first bus and the second bus.

The peripheral function block (57) includes a multiplication circuit,
It has a barrel shifter, an internal vector register, and a status register for an interrupt request signal. Further, a signal obtained by ORing the six interrupt request signals is transmitted to the processor core (5
0) is output as an interrupt request signal.

The address decoder (51) decodes a logical address signal. Based on the decoded address information, an access valid signal, and a memory map mode control signal transmitted from an external memory interface circuit (not shown), an access is determined. It is determined which of the first bus, the second bus, and the peripheral function block (57) the area corresponds to. If the access corresponds to the first bus area, a first bus area selection signal is sent to the first bus interface control means (52), and if the access corresponds to the second bus area, the second bus interface control means ( 53), a second bus area selection signal is transmitted. If the access corresponds to the internal peripheral function block area or if the access is not valid, the first bus and second bus area selection signals are not sent out, and the central processing unit does not access the external function block.

The first bus interface control means (5
2) generates a first bus use request signal from the first bus area selection signal received from the address decoder (51) and sends it to the first bus arbitration circuit. The first bus use request signal is transmitted for a period until a first bus use permission signal is received from the first bus arbitration circuit. The first bus use permission signal is output only during one bus cycle period of the first bus, that is, one clock cycle period. The first bus interface control means (52) permits output to the three-state buffer (60) only during this period. And permitting input / output to / from the bidirectional three-state buffer (61).

The second bus interface control means (5
3) generates a second bus use request signal from the second bus area selection signal received from the address decoder,
Send to bus arbitration circuit. The second bus use request signal is transmitted for a period until a second bus use permission signal is received from the second bus arbitration circuit. The use of the second bus is permitted during the period from the reception of the second bus use permission signal to the reception of the second bus cycle end signal, so that the second bus interface control means (53) operates only during this period. The output permission for the three-state buffer (55) and the input / output permission for the bidirectional three-state buffer (56) are performed.

The clock control means (54) controls the clock supplied to the processor core (50) in accordance with the processor wait control signals sent from the first bus interface control means (52) and the second bus interface control means (53). Stop and put the processor core (50) in the wait state.

The three-state buffer (60) controls the output of the lower 16 bits of the internal address and the read / write signal to the first bus according to the control signal transmitted from the first bus interface control means (52). That is, the three-state buffer (60) controls 17 signal lines.

The three-state buffer (55) controls the output of the internal address 24 bits and the read / write signal to the second bus according to the control signal transmitted from the second bus interface control means (53). That is, the three-state buffer (55) controls 25 signal lines.

The bidirectional three-state buffer (61) is connected to the internal data bus (59) according to a control signal transmitted from the first bus interface control means (52).
An output to the data bus and an input from the first data bus to the internal data bus (59) are controlled. That is, the bidirectional three-state buffer (61) controls eight signal lines.

The bidirectional three-state buffer (56) receives the second signal from the internal data bus (59) according to a control signal transmitted from the second bus interface control means (53).
An output to the data bus and an input from the second data bus to the internal data bus (59) are controlled. That is, the bidirectional three-state buffer (56) controls eight signal lines.

The address space of the central processing unit will be described below. Hereinafter, the hexadecimal number is represented by adding “h” to the end of the number to distinguish it from the decimal number.

The processor core (50) of the present central processing unit has a 24-bit address signal, that is, a 16-megabyte address space. This is a logical address space viewed from a program executed by the processor core (50).

The first bus has a 16-bit address signal, that is, a physical address space of 64 kilobytes.

The second bus has a 24-bit address, that is, 16 bits.
It has a megabyte physical address space. The address space of the second bus is roughly divided into two areas, and different bus cycle lengths can be set for each area.
Here, these two areas are referred to as a second bus area A and a second bus area A.
It is called a bus area B.

In the present central processing unit, a plurality of physical address spaces are arranged in the logical address space of the processor core (50), and each time the processor core (50) accesses, a plurality of physical address spaces are allocated. One is selected and used. For buses not selected, the processor core (50) does not occupy them and is in an open state available to other bus masters.

As shown in FIGS. 3 and 4, the CPU has two different memory map modes. Here, these are called memory map mode 1 and memory map mode 2. These modes are switched by a memory map mode switching control register included in an external memory interface circuit (not shown).

The memory map mode switching control register is connected to the first bus, and is readable and writable from the bus master of the first bus including the central processing unit. By doing so, not only the central processing unit but also other bus masters can control this memory map mode, and can share this memory map mode.

The 24-bit address issued by the processor core (50) is largely divided into upper 8 bits and lower 16 bits, and the address of the upper 8 bits functions as a bank address. That is, the 16-megabyte logical address space is divided into 256 unit spaces called 64-kilobyte banks. For example, the FFFFh address of the 00h bank and the 0000h address of the 01h bank are not continuous. Therefore, the memory maps shown in FIGS. 3 and 4 are represented in parallel for each bank in order to clearly show them.

The memory map mode 1 will be described.

In the peripheral function block (57), the lower 16 bits of the logical address are 00FEh, 00FFh, 7FF0
h to 7FFFh. If the physical address of the first bus is from 0000h to 7FEFh (00FEh, 0
0FFh) is the lower one of the logical address.
6 bits are 0000h to 7FEFh (00FEh, 00FEh
(Excluding FFh). The physical address of the first bus is 00FEh, 00FFh, 7FF0-FF
The space indicating FFh is inaccessible from the central processing unit.

In the memory map mode 1, in the peripheral function block area and the first bus area, the same image is arranged in all the banks 00h to FFh. For example, both the access to the logical address space 000000h and the access to 010000h are access to the physical address space 0000h of the first bus.

The physical address of the second bus is 008000h
~ 00FFFFh to FF8000h ~ FFFFFFh
Indicates that the logical address is between 008000h and 00F
It is arranged in a space indicating FFFh to FF8000h to FFFFFFh. Here, the logical address is 008000h
~ 00FFFFh to 7F8000h ~ 7FFFFFFh
Is the second bus area A, and the logical address space is from 808000h to 80FFFFh to FF8000h.
The space indicating ＦＦFFFFFFh is the second bus area B.
In the memory map mode 1, the physical address of the second bus is from 000000h to 007FFFFh to FF000h.
The space from 0h to FF7FFFh is inaccessible from the central processing unit.

The memory map mode 2 will be described.

In the peripheral function block, the bank address in the logical address space indicates 00h to 7Fh, and the lower 16
Bit address is 00FEh, 00FFh, 7FF0h
~ 7FFFh.

The physical address of the first bus is from 0000h to 7
The space indicating FEFh (excluding 00FEh and 00FFh) indicates the bank addresses 00h to 7Fh of the logical address space, and the lower 16-bit addresses are 0000h to 7F.
It is arranged in a space indicating EFh (excluding 00FEh and 00FFh). As in the memory map mode 1, the physical addresses of the first bus are 00FEh, 00FFh, 7FF0 to F
The space indicating FFFh is inaccessible from the central processing unit.

The physical address of the second bus is 008000h
~ 00FFFFh to 7F8000h ~ 7FFFFFFh
Indicates that the logical address is between 008000h and 00F
In the space indicating FFFh to 7F8000h to 7FFFFFFh, the physical address of the second bus is set to 800000h to 80Fh.
The space indicating FFFFh to FF0000h to FFFFFFh has a logical address of 800000h to 80FFFF.
h to FF0000h to FFFFFFh. Here, the logical address is 008000h to 00
A space indicating FFFFh to 3F8000h to 3FFFFFh, and a space indicating 80000000h to 80FFFFh to BF00
The space indicating 00h to BFFFFFh is the second bus area A
And the logical address is 408000h to 40FFFF
h to the space indicating 7F8000h to 7FFFFFh and C0000h to C0FFFFh to FF0000h to
The space indicating FFFFFFh is the second bus area B.
In the memory map mode 2, the physical address of the second bus is from 000000h to 007FFFFh to 3F000h.
The space indicating 0h to 3F7FFFh is inaccessible from the central processing unit.

As described above, the physical address space of about 32 kilobytes of the first bus and the physical address space of 8 megabytes (mode 1) or 12 megabytes (mode 2) of the second bus correspond to the 16 megabyte logical address space of the processor core. And can be handled uniformly and continuously on the program.

Further, since the peripheral function block, the first bus, and the second bus are selectively used each time access is performed according to the value of the logical address, the central processing unit occupies the first bus and the second bus simultaneously. The other bus master can use the other bus even while the central processing processor uses one bus.

An example of access from the central processing unit to the first bus and the second bus will be described below.

FIG. 5 shows an example of a timing chart of access to the first bus of the central processing unit.

One bus cycle period of the first bus corresponds to one cycle period of the clock signal, and the first bus arbitration circuit arbitrates access from a plurality of bus masters including the central processing processor every bus cycle. .

On the other hand, one bus cycle period of the processor core (50) of the present central processing unit corresponds to three cycles of the clock signal even when operating without the wait state. Longer. The use permission period of the first bus given to the bus master is one bus cycle, that is, one clock cycle. In order for the low-speed central processing unit to perform access, the above-described function shown in FIG. Timing control is required.

The processor core of the central processing unit operates based on the falling edge of the clock signal supplied thereto. In other words, one operation cycle of the processor core is from one falling point to the next falling point, and one bus cycle of the processor core is the same.

The logical address is sent from the processor core based on the fall of the clock signal to the processor core, and the address decoder accesses the first bus area based on the logical address, the access valid signal and the memory map mode information. It is determined whether or not. If the access corresponds to the first bus area, the address decoder
The bus area selection signal is sent to the first bus interface control means, and the first bus interface control means generates a first bus use request signal based on this signal and sends it to the first bus arbitration circuit.

The first bus arbitration circuit receives a first bus use request signal from each bus master, determines a bus master to which the bus use is permitted in each bus cycle of the first bus, and gives the first bus use permission to the bus master. Send a signal.
At this time, the use of the first bus is not permitted to two or more bus masters at the same time.

The first bus use permission signal is issued only in units of one bus cycle, and each bus master is permitted to use the first bus only in the bus cycle receiving the first bus use permission signal.

The clock control means controls the period until the central processing unit receives the first bus use permission signal.
The clock supplied to the processor core is stopped at the high level, and the processor core is set to the wait state. When the central processing unit receives the first bus use permission signal, it lowers the clock to a low level and causes the processor core to end the bus cycle and release the wait state.

The central processing unit sends a part of the internal address bus and the read / write signal in response to the first address bus and the read / write signal while the use of the first bus is permitted. Here, the low level of the read / write signal indicates data writing, and the high level indicates data reading.

When the central processing processor reads data from the first bus, the internal data bus signal is sent to the first data bus in a bus cycle in which use of the first bus is permitted. Output. However, in order to prevent data collision on the first data bus, the clock signal is not output during a low level period.

When the central processing unit writes data to the first bus, the first data bus signal is input to the internal data bus in a bus cycle in which use of the first bus is permitted. . Based on the falling edge of the clock signal to the processor core, the processor core (5
0) acquires data.

FIG. 6 shows an example of a timing chart of access to the second bus of the central processing unit.

One bus cycle period of the second bus corresponds to a period of 2 to 8 cycles of the clock signal, and access from a plurality of bus masters including the central processing processor is arbitrated by the second bus arbitration circuit every bus cycle. You.

The length of one bus cycle period of the second bus is equal to the length of the second bus included in the external memory interface circuit (not shown).
It is determined by the bus cycle length control register. Second
The bus cycle length control register is connected to the first bus, and can be read and written by a bus master such as a central processing processor. The area of the second bus is the second bus area A and the second bus area.
The bus area B is divided into two areas, each of which is provided with a different bus cycle length control register, so that different bus cycle lengths can be set. However, in the example shown in FIG. 6, for simplicity of description, one bus cycle period is limited to access to an area set to four clock signal cycles.

A logical address is sent from the processor core based on the fall of the clock signal to the processor core, and the address decoder accesses the second bus area based on the logical address, the access valid signal, and the memory map mode information. It is determined whether or not. If the access corresponds to the second bus area, the address decoder
The bus area selection signal is sent to the second bus interface control means, and the second bus interface control means generates a second bus use request signal based on this signal and sends it to the second bus arbitration circuit.

The second bus arbitration circuit receives a second bus use request signal from each bus master, determines a bus master to which the bus use is permitted in each bus cycle of the second bus, and gives the bus master the second bus use permission. Send a signal.
As in the case of the first bus, no two or more bus masters are allowed to use the second bus at the same time.

The second bus use permission signal is issued only in units of one bus cycle, and the bus master uses the second bus for a period from the reception of the second bus use permission signal to the reception of the second bus cycle end signal. Allowed. This period is equal to the bus cycle length set by the second bus cycle length control register. In this example, one bus cycle corresponds to four cycles of the clock signal.

The central processing unit sends an internal address bus and a read / write signal in response to the second address bus and the read / write signal while the use of the second bus is permitted. Here, the low level of the read / write signal indicates data writing, and the high level indicates data reading.

The external memory interface circuit decodes the address signal of the second address bus issued by the bus master and, based on the decoded address information and the memory map mode information, makes an access to the second bus area A and the second bus area.
It is determined which of the bus areas B corresponds to which area, a second bus cycle end signal is generated from the value of the second bus cycle length control register corresponding to each area, and all bus masters of the second bus and the second bus cycle end signal are generated. It is sent to the 2-bus arbitration circuit.

The clock control means stops the clock supplied to the processor core at a high level until the central processing unit receives the second bus use permission signal and receives the second bus cycle end signal, and waits for the wait state. To When the central processing unit receives the second bus cycle end signal, it lowers the clock to low level, causes the processor core to end the bus cycle, and release the wait state.

When the central processing unit writes data to the second bus, the internal data bus signal is sent to the second data bus in a bus cycle in which use of the second bus is permitted. Output. However, in order to prevent data collision on the second data bus, no data is output during the low level of the clock signal in the clock cycle at the beginning of the bus cycle.

When the central processing unit reads data from the second bus, the second data bus signal is input to the internal data bus in a bus cycle in which use of the second bus is permitted. . The processor core acquires data on the basis of the fall of the clock signal to the processor core.

Hereinafter, a bus arbitration system will be described with reference to examples of the first bus arbitration circuit and the second bus arbitration circuit. FIG. 7 shows the configuration of the first bus arbitration circuit, and FIG. 12 shows the configuration of the second bus arbitration circuit.

The first bus arbitration circuit shown in FIG. 7 includes four ordinary bus masters A, B, C, and D (not shown) and one privileged bus master S (hereinafter, referred to as privileged bus master S) for a total of five bus masters. Arbitrates access to the first bus. The first bus arbitration circuit always grants use permission of the first bus in the next one bus cycle in response to a use request of the first bus from one privileged bus master S. On the other hand, in response to the use request of the first bus from the other four normal bus masters A, B, C and D, only the bus master having the highest priority is permitted to be used in the next one bus cycle according to the priority information. Arbitration to give Here, a DRAM refresh control circuit or the like is assumed as the privileged bus master S, while the above-mentioned central processing processor or the like is assumed as a normal bus master.

The first bus arbitration circuit controls the arbitration of the first bus including the first address bus, the read / write signal, and the first data bus, and the internal register is accessed from the first bus. It has been done. A bus cycle corresponds to one cycle of a clock signal, and arbitration is performed for each bus cycle.

As shown in FIG. 7, the first bus arbitration circuit comprises 16 fixed priority information storage means (101 to 116),
16 programmable priority information storage means (registers) (101 'to 116'), address decoder (117), fixed / programmable switching control register (118), bus cycle counter (119), priority information selection means (selector) ) (120), use permission signal generation means (121), data selector (122), three-state buffers (123, 124) and alternative address generation means (125).

The address decoder (117) decodes a first address bus and a read / write signal,
Each programmable priority information register (101 'to 116')
, A control signal for the data selector (122), and a control signal for the three-state buffer (123).

The fixed / programmable switching control register (118) includes fixed priority information storage means (101 to 116).
And programmable priority information registers (101 'to 116')
To select either fixed priority information or programmable priority information.

Each of the programmable priority information registers (101 'to 116') is a register for storing a set of programmable priority information, and a bus master such as a processor accessing the first bus stores the information. It has been made rewriteable.

Each fixed priority information storage means (101 to 1)
16) is a means for storing one set of fixed priority information, and is constituted by wired logic. This information cannot be rewritten. In this example, the magnitude of the value of these pieces of priority information is 2 bits, and represents a combination of four priorities. However, the magnitude of this value need not be 2 bits. An optimum value should be used in consideration of the number of bus masters to be arbitrated, the number of combinations of priorities, and the circuit scale.

In this example, the number of fixed priority information storage means (101-116) and the number of programmable priority information registers (101'-116 ') are both 16, and
Arbitration is performed with 16 bus cycles as a unit of repetition. However, this number does not have to be 16. An optimum value should be used in consideration of the number of bus masters to be arbitrated, the allocation ratio of bus cycles to each bus master, and the circuit scale.

The bus cycle counter (119) counts the number of bus cycles of the first bus and indicates a current value in which 16 bus cycles are used as a repetition unit. The maximum value of the count should be set equal to the number of sets of priority information.

The selector (120) selects one of 16 sets of priority information from the information of the current value of the bus cycle indicated by the bus cycle counter (119). The use permission signal generating means (121) receives four normal bus masters of a bus master A, a bus master B, a bus master C, and a bus master D, and a use request signal of a first bus from one privileged bus master S, and receives the selector ( 12
A use permission signal for the first bus is generated for the bus master having the highest priority from the priority information selected in (0), and is issued to the bus master.

Here, when the first bus use request signal from privileged bus master S is received, other bus masters A, B,
Regardless of the first bus use request signals from C and D and the priority information of these bus masters A, B, C and D, the use permission of the next one bus cycle is unconditionally given to the privileged bus master S. However, in the present invention, the number of bus masters to be accessed and the presence or absence of a privileged bus master are not limited to this embodiment.

The data selector (122) receives each register (11) from a bus master such as a processor via a first bus.
When reading the values of (8, 101 ′ to 116 ′), data to be read is selected according to the control signal generated by the address decoder (117).

The three-state buffer (123) determines whether or not to output a register value sent from the data selector (122) to the first data bus according to a control signal generated by the address decoder (117). To control.

The other three-state buffer (12
4) operates to output a substitute address issued from the substitute address generating means (125) to the first address bus and the read / write signal when there is no bus use request signal from the bus master.

Next, an arbitration example of the first bus arbitration circuit will be described. In the arbitration example described below, for the purpose of simplifying the description, it is assumed that only the bus masters A and B issue a bus use request signal, and the bus masters C and D do not issue a bus use request signal. That is, the arbitration targets are limited to the bus master A and the bus master B.

One bus cycle of the first bus corresponds to one cycle of the clock signal. Bus cycle counter (119)
Increments the value every bus cycle, from 0 to 15
The value up to is periodically counted. Then, for each bus cycle, one of the priority information storage means (101, 101 'to 116, 116') corresponding to the value of the bus cycle counter (119) on a one-to-one basis is selected and stored in the selected storage means. Priority information is retrieved. In this example, the priority information has a size of 2 bits, and 0, 1,.
Indicates any one of the four values of 2, 3.

FIG. 8 shows an example of setting the value of the priority information corresponding to the value of the bus cycle counter. This setting of the priority information can be applied to both fixed priority information and programmable priority information. FIG. 8 shows an example of setting the values 0, 1, 2, and 3 of the priority information and the priority order of the bus masters A, B, C, and D corresponding thereto.

FIG. 10 shows a first example of arbitration, and FIG. 11 shows a second example of arbitration. The arbitration example 1 shown in FIG. 10 and the arbitration example 2 shown in FIG. 11 are based on partially different design schemes. The difference between the two is that when the bus master obtains the bus use permission, it can be immediately reflected in a bus use request signal issued by itself.

In the design method for realizing the arbitration example 1 shown in FIG. 10, the bus master can immediately reflect the change in the bus use request signal in the cycle in which the bus use is permitted. , The same bus master is allowed to continuously issue a bus use request signal.

On the other hand, in the design method for realizing the arbitration example 2 shown in FIG. 11, the bus master cannot reflect it in the bus use request signal in the cycle in which the bus use is permitted. The arbitration circuit ignores the use request from the bus master that has given the use permission in the cycle in which the use permission of the bus is given. Therefore, in the arbitration example 2 design method, the same bus master cannot continuously obtain the right to use the bus. However, the arbitration example is easier to design than the first design method, and is an effective design method especially when high-speed arbitration is required.

The first bus arbitration example 1 and 2 will be described below.
First, common points will be described.

When none of the bus masters has issued a bus use request signal, the bus arbitration circuit does not issue a bus use permission signal to any of the bus masters. For example, in the first bus cycle (701,801), the bus master A,
Since none of the bus masters B has issued a bus use request signal, the bus arbitration circuit does not permit any bus master to use the bus in the next bus cycle (702, 802).

When only one of the bus masters issues a bus use request signal, the bus arbitration circuit issues a bus use request signal to the bus master. For example, in the second bus cycle (702, 802), only the bus master A issues a bus use request signal, so that the bus master A is permitted to use the bus in the next bus cycle (703, 803).

When two or more bus masters are issuing bus use request signals at the same time, the bus arbitration circuit selects a bus master having a higher priority according to the priority order represented by the priority information, and gives the bus master the priority. In response, a bus use permission signal is issued. For example, the sixth bus cycle (70
6, 806), the bus masters A and B simultaneously issue a bus use request signal, and the bus master B is set to a higher priority than the bus master A. Allowed.

Next, differences between the two arbitration examples will be described.

In the first arbitration example, a bus master has finished issuing a use request signal in a cycle in which a bus use is permitted, and another bus master issues a use request signal in that cycle. In this case, only the other bus master requests use. Therefore, the other bus master A obtains the bus use permission in the next one bus cycle. For example, as shown in FIG. 10, the bus master A has finished issuing the use request signal in the third bus cycle (703) in which the use of the bus is permitted, and the bus master B uses the bus in the bus cycle (703). Since the request signal has been issued, the bus master B
Only the bus master B has been requested to use the bus master B in the next one bus cycle (704).

On the other hand, arbitration example 2 is a case in which a bus master has not finished issuing a use request signal in a bus cycle in which the bus use is permitted, and another bus master issues a use request in the bus cycle. When the signal is issued, the use request from the bus master having the use permission is ignored, and only the use request from the other bus master is accepted. Therefore, the other bus master obtains the bus use permission in the next one bus cycle.
For example, although the bus master A has not finished issuing the use request signal in the third bus cycle (803) in which the bus use is permitted, the bus master B issues the use request signal in the bus cycle (803). In this bus cycle (803), the use request from the bus master A is ignored, and only the use request from the bus master B is accepted. Accordingly, in the next one bus cycle (804), the use of the bus master B is permitted.

In the first arbitration example, when the same bus master continuously makes a bus use request (707, 708), it is possible to continuously grant the same bus master the use permission for two or more bus cycles. is there. For example, bus master A
Are continuously requesting the use of the bus in the seventh and eighth bus cycles (707, 708).
Use is permitted in the bus cycle (708, 709).

On the other hand, in the arbitration example 2, in the bus cycle (808) in which the use permission is given to the bus master,
Since the use request signal from the bus master is ignored, the same bus master cannot be granted use permission for two or more consecutive bus cycles. For example, bus master A
Is used in the eighth bus cycle (808), the use request signal in the bus cycle (808) is ignored, and the use is not permitted in the next bus cycle (809).

Next, a second bus arbitration circuit for arbitrating accesses from a plurality of bus masters to the second bus will be described. This arbitration circuit controls arbitration of four bus masters, and controls arbitration of a second bus including a second address bus, a read / write signal, and a second data bus.
The built-in register is accessed from the first bus.
The bus cycle corresponds to 2 to 8 cycles of the clock signal (however, only an integer), and arbitration is performed every bus cycle.

FIG. 12 schematically shows a main part of the second bus arbitration circuit.

The second bus arbitration circuit comprises an address decoder (217), a fixed / programmable switching control register (21
8), eight fixed priority information storage means (201 to 208),
Eight programmable priority information registers (201 'to 20')
8 '), bus cycle counter (219), selector (22
0), use permission signal generation means (221), data selector (222), three-state buffers (223, 224), and alternative address generation means (225).

Hereinafter, differences from the first bus arbitration circuit will be described.

Since the purpose of the second bus arbitration circuit is to arbitrate the access of each bus master to the second bus, the use permission signal generating means (221) receives the second bus use request signal from each bus master, and Issues a use permission signal for the second bus. The four bus masters to be arbitrated are a bus master A, a bus master B, a bus master C, and a bus master D. As these bus masters, the above-described central processing processor and the like are assumed.

Fixed priority information storage means (201 to 208) and programmable priority information registers (201 'to 20')
8 ') In both cases, the number is eight. Accordingly, the circuit scale of the address decoder (217), the bus cycle counter (219), the selector (220), and the data selector (222) is also the first.
It is smaller than the bus arbitration circuit.

However, the fixed priority information storage means (201 to 2)
08) and the programmable priority information register (201 ')
To 208 ') need not be eight. An optimum value should be used in consideration of the number of bus masters to be arbitrated, the allocation ratio of bus cycles to each bus master, and the circuit scale.

When there is no request signal from the bus masters A, B, C, and D, the three-state buffer (224) transfers the substitute address issued from the substitute address generating means (225) to the second address bus and read / write. Output to signal.

FIG. 13 shows an example of the second bus arbitration. Also in this arbitration example, the bus master C
In addition, no bus use request signal is issued from the bus master D, and the arbitration targets are limited to the two bus masters A and B.

As described above, the second bus has two large areas, and different bus cycles can be set for each area. In this example, one bus cycle in the area accessed by the bus master A corresponds to four cycles of the clock signal, and one bus cycle in the area accessed by the bus master B corresponds to two cycles of the clock signal.

Note that one bus cycle corresponds to one cycle of a clock signal while no bus master is using the bus.

The bus use permission signal indicates a high level to the bus master permitting use of the bus only for one cycle of the first clock signal of one bus cycle. The bus master that has received the bus use permission signal is permitted to use the bus until the bus cycle ends.

The bus cycle end signal indicates a high level only during one cycle of the last clock signal of one bus cycle, and indicates a low level during other periods. A high level is output during a period when no bus master is using the bus. This signal is common to all bus masters.

The bus cycle counter (219) increments the value for each bus cycle and periodically counts a value from 0 to 7.

A bus cycle counter for each bus cycle
The value of the priority information corresponding to the value of (219) on a one-to-one basis is selected. In this example, the priority information has a size of 2 bits and indicates one of four values 0 to 3.

The contents of the priority information in this example are shown in FIG. Here, it is not specified whether this is fixed priority information or programmable priority information, but the present invention is applicable to both cases.

The value of the priority information indicates the order of priority of the corresponding bus master. Here, the setting example shown in FIG. 8 similar to the arbitration example of the first bus is used.

If none of the bus masters has issued the second bus use request signal, the second bus arbitration circuit does not issue the bus use permission signal to any of the bus masters. For example, in the first bus cycle (901), neither the bus master A nor the bus master B issues a bus use request signal, so that the bus arbitration circuit issues a bus request to any bus master in the next bus cycle (902). Do not allow the use of.

When only one of the bus masters issues a bus use request signal, the bus arbitration circuit issues a bus use permission signal to the bus master in the next cycle in which the bus use request signal is received. , Until the bus cycle end signal is issued. For example, in the second bus cycle (902), only the bus master A issues a bus use request signal,
Since the bus use end signal is issued in the middle of the next bus cycle (903), the bus master A is permitted to use the bus in all the periods of the bus cycle (903).

When two or more bus masters are issuing bus use request signals at the same time, the bus arbitration circuit selects a bus master having a higher priority according to the priority order represented by the priority information, and gives the bus master the priority. In response, a bus use permission signal is issued. For example, the sixth bus cycle (90
In (6), the bus masters A and B simultaneously issue a bus use request signal, and the bus master B has a higher priority than the bus master A. Therefore, the bus master B is used in the next bus cycle (907). Allowed.

In this example, the bus master detects the bus use permission signal at the falling edge of the clock signal, and reflects the result in the bus use request signal issued by itself.
In this example, since the shortest bus cycle given to the bus master corresponds to two cycles of the clock signal, the bus master can complete the above operation by the end of the bus cycle. Therefore, the same bus master is allowed to make a bus use request continuously.

When the same bus master issues a bus use request signal at the end of a bus cycle (908) in which a certain bus master is permitted to use, the bus arbitration circuit issues the next bus cycle (909) to the same bus master. ) Again.

Hereinafter, a high-speed multiprocessor according to the present invention will be described.

FIG. 15 shows an outline of a main part of the high-speed multiprocessor. This high-speed multiprocessor according to the present embodiment includes one central processing unit (bus master) (13
01) One graphic processor (bus master) (1302), one sound processor (bus master) (1303), one direct memory transfer (DM
A) Control processor (bus master) (1304), internal memory (bus slave) (1305), first bus arbitration circuit (130
6), second bus arbitration circuit (1307), input / output control circuit (bus slave) (1308), timer circuit (bus slave)
(1309), analog / digital (A / D) converter (bus slave) (1310), PLL circuit ((1311), clock driver (1312), low voltage detection circuit (1313), external memory interface circuit (1314)) DRAM refresh control circuit (bus master) if necessary
(1315).

Further, the first address bus, the read / write signal (1316) and the first data bus (1317) constitute a high-speed first bus, and the second address bus and the second read / write signal (1318). ) And the second data bus (1319) constitute a low-speed second bus.

The second address bus and the read / write signal (1318) correspond to the external address bus and the read / write signal (1313).
20), the second data bus (1319) is connected to the external data bus (1321) through an external memory interface circuit (1314).

Outside the multiprocessor, one or more external read only memories (ROMs) (bus slaves) (1322), and, if necessary, one or more external random access memories (RAMs) (bus slaves) (bus slaves) 1323), an oscillation circuit constituted by a crystal oscillator (1324), and a battery (1325) for holding data in a static memory (SRAM) as required.

The central processing processor (1301) provided in the multiprocessor uses the central processing processor as it is.

The first bus arbitration circuit (1306) and the second bus arbitration circuit (1307) provided in the multiprocessor are provided with the first bus arbitration circuit (1307).
And the second arbitration circuit is used as it is.

The first bus arbitration signal shown in FIG.
The second bus arbitration signal includes a first bus use request signal, a first bus use permission signal, and a second bus use request signal.
It comprises a bus use permission signal and a bus cycle end signal of the second bus.

Here, the bus master A, bus master B, bus master C, and bus master D are a sound processor (1303) and a graphic processor (130
2) Corresponds to the DMA control processor (1304) and the central processing processor (1301), and the privileged bus master is DRAM
This corresponds to the refresh control circuit (1315).

The function of each unit constituting the multiprocessor will be described.

The central processing unit (1301) performs various calculations and controls the entire system according to a program stored in the memory.

The graphic processor (1302)
It synthesizes graphic data and generates video signals suitable for a color television receiver. The graphic data is composed of a graphic element consisting of a two-dimensional array of a set of rectangular pixels having a size that covers the entire screen of the television receiver, and a set of rectangular pixels that can be arranged at any position on the screen. Synthesized from graphic elements. Here, the former is called a text screen, the latter is called a sprite, and each set of rectangular pixels is called a character. The one used in this embodiment can display a maximum of two text screens and a maximum of 256 sprites. From the combined graphic data, a video signal that can be displayed on a receiver conforming to the NTSC standard and the PAL standard is generated.

The sound processor (1303) synthesizes sound data and generates audio signals. The sound data is synthesized by performing pitch conversion and amplitude modulation on PCM (pulse code modulation) data, which is a basic tone color. In the amplitude modulation, in addition to the volume control instructed by the central processing unit (1301),
An envelope control function for reproducing waveforms of musical instruments such as a piano and a drum is provided.

The DMA control processor (1304) has an external R
It manages data transfer from the OM or external RAM to the internal memory.

The internal memory (1305) includes necessary ones of a mask ROM, a static memory (SRAM), and a dynamic memory (DRAM). When data retention by the SRAM battery is required, a battery (1325) is required outside the multiprocessor.
When a DRAM is mounted, an operation called “refresh” for holding stored contents is required periodically.

The first bus arbitration circuit (1306) receives a first bus use request signal from each bus master connected to the first bus, performs arbitration in accordance with the priority information of the first bus, and arbitrates each bus master. Issues a bus permission signal. Since the bus cycle of the first bus in this embodiment corresponds to one cycle of the clock signal, the bus arbitration circuit performs the above operation for each cycle of the clock signal.

The second bus arbitration circuit (1307) receives a request signal for use of the second bus from each processor connected to the second bus, and executes the second bus arbitration circuit in accordance with the priority information of the second bus.
It arbitrates for the bus and issues a bus use permission signal to the processor. Since the bus cycle of the second bus in this embodiment corresponds to 2 to 8 cycles of the clock signal, the bus arbitration circuit performs the above operation for each bus cycle and issues a bus cycle end signal to the processor. Signals the end of a bus cycle.

The input / output control circuit (1308) is mainly used for communication with an external input device for receiving an input from a human or an external semiconductor element.

[0177] The timer circuit (1309) controls the central processing unit (130) based on the time interval set by the program.
For 1), it has a function to generate an interrupt request signal.

The A / D converter (1310) converts an analog level input voltage signal into a digital value.

The PLL circuit (1311) is constituted by a phase locked loop (PLL), and is a high frequency obtained by multiplying a sine wave signal obtained from a crystal oscillator (1324) external to the processor by M / N times (M and N are integers). Generate a clock signal.

The clock driver (1312) amplifies the high frequency signal received from the PLL circuit to a signal strength sufficient to supply a clock signal to each functional block.

The low voltage detection circuit (1313) monitors the power supply voltage, and when the power supply voltage is equal to or lower than the predetermined fixed voltage,
A signal for controlling reset of the L circuit and other resets of the entire system is issued. An SRAM is provided inside or outside the processor, and the SRAM
Has a function of issuing a battery backup control signal when the power supply voltage is equal to or lower than a predetermined fixed voltage when data retention by the battery is required.

External memory interface circuit (1314)
Has a function for connecting the second bus to the external bus, a second bus cycle length control register, and a memory map mode control register.

This high-speed multiprocessor has two types of memory map modes, which can be switched by a control register. In any of the memory map modes, the space of the external bus is largely divided into a ROM area and a ROM / RAM area, and it is possible to specify a different number of clocks of one bus cycle for each. The ROM area corresponds to the second bus area A, and the ROM / RAM space corresponds to the second bus area B.

DRAM refresh control circuit (1315)
Acquires unconditionally the right to use the first bus at regular intervals,
The refresh operation of the DRAM is controlled.

A sound processor (1303), a graphic processor (1302), a DMA control processor (1304), a timer circuit (1309), an input / output control circuit (130
8) The A / D converter (1310) has a function of generating an interrupt request signal for the central processing unit (1301). These correspond to the interrupt request signals A to F shown in FIG.

The first effect when the high-speed multiprocessor is used is that the bus is divided into the first bus and the second bus in accordance with the response speed and the data transfer capability of the bus slave. More efficient use of shared buses,
The processing capability of the high-speed multiprocessor as a whole is to be improved.

The second effect is that each bus master independently has an interface for the first bus and the second bus, and when one bus is used, the other bus is wastefully occupied. Instead, the use efficiency of the shared bus is increased as in the above-described effect.

The third effect is that the bus cycle is not determined by the bus cycle speed of the bus master, but the bus cycle is determined at the highest speed at which the bus slave and the bus itself can operate. Even when a bus master having a low-speed bus cycle accesses as described above, the bus use efficiency does not decrease.

A fourth effect is that a plurality of physical address spaces are arranged on a single logical address space as in the central processing unit shown in the embodiment, whereby the plurality of physical addresses are arranged. It is to be able to handle the space uniformly and continuously in the program.

The fifth effect is that the arrangement of the bus arbitration circuit as described above gives weight to the distribution of the right to use the bus of each bus master, and allows all bus masters to use the bus within a certain period of time. Rights can be guaranteed, and the overall processing capacity of the entire system can be increased by dynamically changing the weight of the bus master's allocation of bus use rights in response to changes in processing content. It is to become.

A sixth effect is that the high-speed multiprocessor shown in this embodiment is realized on a single semiconductor device, so that a plurality of buses are provided, and each bus master independently has an interface for the plurality of buses. The problem is that the number of wirings does not matter, and a high-performance system can be realized with a very simple external circuit.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an outline of a high-speed processor according to the present invention.

FIG. 2 is an explanatory diagram showing a configuration example of a central processing processor used in the high-speed processor.

FIG. 3 is an explanatory view showing a memory map mode 1 of a logical address space of the central processing unit.

FIG. 4 is an explanatory diagram showing a memory map mode 2 of a logical address space of the central processing unit.

FIG. 5 is a timing chart showing an example of using a first bus of the central processing unit.

FIG. 6 is a timing chart showing an example of using a second bus of the central processing unit.

FIG. 7 is a circuit diagram illustrating an outline of a first bus arbitration circuit.

FIG. 8 is a table showing a setting example of priority information in a first bus arbitration circuit.

FIG. 9 is a table showing an example of a priority order represented by priority information.

FIG. 10 is a timing chart showing a first bus arbitration example 1;

FIG. 11 is a timing chart showing a first bus arbitration example 2;

FIG. 12 is a circuit diagram showing an outline of a second bus arbitration circuit.

FIG. 13 is a timing chart showing an example of arbitration of a second bus.

FIG. 14 is a table illustrating a setting example of priority information in a second bus arbitration circuit;

FIG. 15 is a circuit diagram showing an embodiment using a high-speed processor according to the present invention.

FIG. 16 is an explanatory diagram of a conventional bus system.

[Explanation of symbols]

 1 bus master 2 bus master 10 bus 11 bus 20 bus slave 21 bus slave

Claims (11)

[Claims] A bus master having at least one bus master; a plurality of buses having different data transfer capacities; and a plurality of bus slaves corresponding to the transfer capacities of the respective buses. And each of the buses has an independent address bus and data bus, and the bus master directly connects to the address bus and the data bus of each bus. A high-speed processor, which is connected. 2. A system comprising: at least one bus master; a plurality of buses having different operation speeds; and a plurality of bus slaves capable of responding at a speed corresponding to the operation speed of each of the buses. Connected to any one of the buses having an operating speed corresponding to the speed, and each of the buses has an independent address bus and a data bus, and the bus master is connected to each of the buses. A high-speed processor, which is directly connected to an address bus and a data bus. A plurality of bus masters, a plurality of buses having different data transfer capacities, and a plurality of bus slaves corresponding to the transfer capacities of the respective buses, wherein each of the bus slaves has a transfer capacity corresponding thereto. Connected to any one of the buses, each of the buses has an independent address bus and a data bus, and each of the bus masters has an address bus and a data bus of each of the buses. And a bus arbitration circuit for arbitrating access to the buses from the plurality of bus masters for each of the buses. 4. A system comprising: a plurality of bus masters; a plurality of buses having different operation speeds; and a plurality of bus slaves which can respond at a speed corresponding to the operation speed of each of the buses. Connected to any one of the buses having an operation speed, wherein each of the buses has an independent address bus and a data bus, and each of the bus masters has an address of the bus. A high-speed processor directly connected to a bus and a data bus, further comprising a bus arbitration circuit for arbitrating access to the bus from a plurality of bus masters for each of the buses. 5. The bus arbitration circuit outputs a bus use request signal to the bus arbitration circuit, waits for access to the bus until a bus use permission signal is obtained, and assigns an address to the bus. The high-speed processor according to claim 3, wherein the high-speed processor has a function of transmitting data independently for each of the connected buses, and has an independent interface for each of the connected buses. 6. The interface controls output / non-output of an address to the bus.
A plurality of sets of three-state buffers independent for each bus; a plurality of sets of bidirectional three-state buffers independent for each bus for controlling data input / output and connection / disconnection to / from the bus; and a bus from a bus arbitration circuit 6. The high-speed processor according to claim 5, further comprising: means for controlling a three-state buffer based on permission of use. 7. At least one of the processors includes: a means for issuing a logical address within the processor; a decoder for decoding the issued logical address; and a plurality of buses based on the decoded address information. Means for selecting one and outputting a bus use request signal; means for selecting only necessary address information from logical addresses to generate a physical address; or means for converting a logical address to generate a physical address And a plurality of sets of three-state buffers for outputting the generated physical addresses to the bus, whereby the plurality of independent physical address spaces for each bus are converted into a part of a single logical address space. 7. The high-speed processor according to claim 1, wherein the high-speed processor is assigned. 8. The bus arbitration circuit determines a bus cycle time as a longer one of a fastest time in which the bus slave can be accessed and a fastest time in which the bus is operable. The system according to claim 1, further comprising a function of always determining a bus use right and giving a bus use permission to the processor only in one bus cycle unit, wherein the processor has a function of transmitting and receiving data within the bus cycle period. 8. The high-speed processor according to any one of items 3 to 7. 9. A bus arbitration circuit comprising: priority information storage means for storing a plurality of sets of bus master priority information including a set of bus master priority information defining priorities among bus masters; Priority information selecting means for sequentially selecting one set of the bus master priority information for each set of one bus cycle using the plurality of sets of bus master priority information as a repetition unit; and one set of the bus master priority information selected by the selection means. A bus use permission signal for outputting a bus use permission signal to permit the bus master having the highest priority among the bus masters requesting the use of the bus to use the bus for one bus cycle based on the priority information; 9. The high-speed processor according to claim 3, further comprising a signal generation circuit. 10. The semiconductor device according to claim 1, wherein all the components are integrated in a single semiconductor device.
2. A high-speed processor according to claim 1. 11. The processor comprises: one or more central processing processors; a processor having means for performing graphics processing to generate a video signal; and a processor having means for performing sound processing and generating an audio signal. A first bus for controlling data transfer and exchange between a functional block inside a semiconductor device and a high-speed semiconductor memory; and a data transfer and exchange between a peripheral device outside the semiconductor device and a low-speed semiconductor memory. The bus slave includes a semiconductor memory connected to the first bus, and the bus arbitration circuit includes a first bus for arbitrating the first bus.
11. The high-speed processor according to claim 3, further comprising: a bus arbitration circuit for controlling the second bus, and a second bus arbitration circuit for arbitrating the second bus. 12.