WO2011016154A1 - External bus interface, lsi and system - Google Patents

External bus interface, lsi and system Download PDF

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Publication number
WO2011016154A1
WO2011016154A1 PCT/JP2010/000625 JP2010000625W WO2011016154A1 WO 2011016154 A1 WO2011016154 A1 WO 2011016154A1 JP 2010000625 W JP2010000625 W JP 2010000625W WO 2011016154 A1 WO2011016154 A1 WO 2011016154A1
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WO
WIPO (PCT)
Prior art keywords
external
terminal
access
lsi
unit
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PCT/JP2010/000625
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French (fr)
Japanese (ja)
Inventor
三野吉輝
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パナソニック株式会社
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Publication of WO2011016154A1 publication Critical patent/WO2011016154A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40032—Details regarding a bus interface enhancer

Definitions

  • the present invention relates to a characteristic adjustment of an IO terminal that realizes low unnecessary radiation and low power consumption in data transfer between devices connected via an external bus.
  • FIG. 6 is a diagram showing a conventional memory control device described in Patent Document 1. In FIG.
  • the memory control device includes a memory 907, a memory interface unit 906 that drives the memory 907, and a memory control unit that controls writing of data to the memory 907 and reading from the memory 907 via the memory interface unit 906.
  • the memory interface unit 906 is provided with a current switching unit 904 and a voltage switching unit 905, and the memory control unit 903 is provided with a timing generation unit 901, an inspection execution / determination unit 902, and an access status determination unit 931.
  • the inspection execution / determination unit 902 performs an inspection to determine whether the write data to the memory 907 and the read data from the memory 907 match to determine whether or not the inspection data is good. And output to the current switching unit 904 and the voltage switching unit 905.
  • the access status determination unit 931 monitors the access status of the memory 907 and compares it with an arbitrary reference value, determines whether the access status is rough or dense, and outputs the determination result to the timing generation unit 901. Yes.
  • the current switching unit 904 switches the output current of the memory interface unit 906 (drive current of the memory 907) to an arbitrary value in accordance with the test determination result input from the test execution / determination unit 902, and performs the test execution / determination.
  • the output current of the memory interface unit 906 is switched according to the determination result of the unit 902. This optimizes the drive current and drive voltage to the memory 907 while avoiding memory data errors, and reduces power consumption and unnecessary radiation.
  • the present invention solves the above-mentioned conventional problem, and optimizes the electrical characteristics such as current drive capability at the IO terminal even when a plurality of external devices having different electrical characteristics are connected.
  • An object is to provide an interface, an LSI, and an LSI system.
  • an external bus interface is an external bus interface provided in an LSI that accesses a plurality of external devices via an external bus according to an access request, and has a current driving capability. And at least one of the slew rates of the output voltage can be switched by setting, an IO terminal for inputting / outputting a signal to / from the external bus, and setting of the electrical characteristics of the IO terminal in synchronization with the access request And an IO terminal control unit.
  • the IO terminal control unit includes a control pattern holding unit that holds a plurality of control patterns written in advance by the CPU, and the plurality of control patterns correspond to current driving corresponding to each of the plurality of external devices.
  • the IO terminal control unit selects a control pattern corresponding to the external device to be accessed, and the electrical characteristics according to the control pattern. You may make it perform the setting of.
  • an optimal control pattern can be set for each external device.
  • optimal electrical characteristics can be flexibly set for different external devices and different external buses.
  • the external bus interface includes an external device control unit that controls access to an external device according to the access request, and the external device control unit includes a parameter storage unit that stores a plurality of access parameters, You may make it select the said access parameter corresponding to the setting of the electrical property to the said IO terminal of an IO terminal control part, and access the said external device.
  • This configuration enables access to an external device in an access cycle linked to the electrical characteristics of the IO terminal.
  • the IO terminal control unit further includes a measuring unit that measures a predetermined time from the start of switching, and the external device control unit starts access to the external device after the predetermined time elapses. May be.
  • This configuration can cope with the case where it takes time for the characteristics to stabilize when the electrical characteristics of the IO terminal are changed.
  • the IO terminal control unit further includes a register that holds information indicating an external device that is the previous access destination, and a determination unit that determines whether or not the current access destination matches the previous access destination. And a prohibiting unit that prohibits the setting of the electrical characteristics of the IO terminal unit when it is determined by the determining unit that they match.
  • the IO terminal control unit further includes a register holding information indicating current electrical characteristics set in the IO terminal unit, electrical characteristics corresponding to a new access request, and the register.
  • a determination unit that determines whether or not the current electrical characteristics indicated by the stored information match, and a prohibition that prohibits setting of the electrical characteristics of the IO terminal unit when the determination unit determines that the current characteristics match It is good also as a structure provided with a part.
  • the external interface may further include an external IO instruction unit that instructs the external device to set the electrical characteristics of the IO terminal of the external device in synchronization with the access request.
  • This configuration can change the electrical characteristics of the IO terminal of the external device for a specific external device access.
  • An LSI has the same configuration as that of the external bus interface described above, and includes a first bus interface that accesses a plurality of external devices via the first external bus according to an access request, and the external bus interface described above. And the current electrical characteristic setting values at the IO terminals of the second bus interface and the second external bus interface for accessing other external devices via the second external bus according to the access request.
  • This configuration makes it possible to change the electrical characteristics of the IO terminal unit according to the operating status of another external bus interface in the LSI.
  • the LSI further includes a register that can be written from a master inside or outside the LSI, and that holds a control pattern indicating at least one of a current drive capability and an output voltage slew rate corresponding to the external device. And at least one of the first and second external bus interfaces may determine an electrical characteristic to be set in the IO terminal unit in accordance with a control pattern held in the register.
  • the LSI further includes a register that can be written from a master inside or outside the LSI, and has an access parameter that defines an access method to the external device, and the first and second external bus interfaces. At least one of these may access an external device in accordance with an access parameter held in the register.
  • This configuration makes it possible to control the setting of the electrical characteristics of the IO terminal section according to the system conditions.
  • a system includes the above-described LSI and a master inside or outside the LSI, and the master sets an output current or a slew rate to a first value in the first operation mode. And a control pattern for setting the output current or slew rate to a second value smaller than the first value in the second operation mode in which the data transfer rate is lower than that in the first operation mode.
  • a control pattern is set in the register.
  • This configuration makes it possible to control the electrical characteristics of the IO terminal unit according to the data transfer rate.
  • a system includes the above-described LSI and a master inside or outside the LSI, and the master outputs an output current or a slew rate in a first operation mode.
  • a control pattern for setting a value is set in the register, and the output current or the slew rate is set to a second value smaller than the first value in the second operation mode in which the operation is performed with lower power consumption than in the first operation mode.
  • a control pattern for this is set in the register.
  • This configuration makes it possible to control the electrical characteristics of the IO terminal section depending on the power supply status, for example, whether or not it is in the power saving mode.
  • a system including the above-described LSI and a master inside or outside the LSI, wherein the master outputs an output current or a slew rate in a first operation mode.
  • a control pattern for setting a value is set in the register, and in the second operation mode in which the transfer clock frequency of the external bus is lower than that in the first operation mode, the output current or slew rate is smaller than the first value.
  • a control pattern for setting the value is set in the register.
  • the electrical characteristics of the IO terminal unit can be controlled by the transfer clock within the range of the electrical specifications of the bus defined by the transfer clock frequency.
  • the external bus interface of the present invention it is possible to optimize the electrical characteristics of the IO terminal unit for access to any external device among a plurality of external devices.
  • the external bus interface can be easily implemented in different systems.
  • FIG. 1 is a block diagram showing a configuration of an LSI system including an external bus interface according to the first embodiment.
  • FIG. 2 is a block diagram showing a configuration of the LSI system in the first modification example of the first embodiment.
  • FIG. 3 is a block diagram showing a configuration of the LSI system in the second modification example of the first embodiment.
  • FIG. 4 is a block diagram showing a configuration of an LSI system including an external bus interface according to the second embodiment of the present invention.
  • FIG. 5 is a block diagram showing a configuration of the LSI system in the first modification example of the second embodiment.
  • FIG. 6 is a schematic block diagram of a conventional memory control device.
  • an external bus interface provided in an LSI that accesses a plurality of external devices via an external bus according to an access request, and the LSI will be described.
  • the external bus interface can switch an electrical characteristic which is at least one of a current driving capability and an output voltage slew rate by setting, and is synchronized with the access request and an IO terminal unit which inputs / outputs a signal to / from the external bus.
  • an IO terminal unit control unit for setting the electrical characteristics of the IO terminal unit.
  • FIG. 1 is a block diagram showing a configuration of an LSI system having an external bus interface according to the first embodiment of the present invention.
  • the LSI system shown in the figure includes an LSI 1, an external device 2, and an external device 3.
  • the LSI 1 is connected to the external device 2 and the external device 3 via the first external bus 4.
  • LSI 1 is a one-chip semiconductor device and includes an external bus interface 6, a CPU 7, and a bus controller 8.
  • the external bus interface 6 accesses the external device 2 and the external device 3 via the first external bus 4 in accordance with an access request issued from the CPU 7 via the bus controller 8. That is, the external bus interface 6 performs data transfer between the LSI 1 and the external device 2 or the external device 3 according to the access request. Therefore, the external bus interface 6 includes an external device control unit 61, an IO terminal control unit 62, and an IO terminal unit 63.
  • the external device control unit 61 receives an access request from the CPU 7 via the bus controller 8, generates an access command corresponding to the access request and the specifications of the external device 2 or external device 3 to be accessed, and passes through the IO terminal unit 63. Issued to the external device to be accessed. However, the external device control unit 61 suspends issuance of an access command when an access start delay instruction is issued from the IO terminal control unit 62, and an access command is issued when the access start delay instruction is canceled from the IO terminal control unit 62. Start issuing.
  • the IO terminal control unit 62 sets the electrical characteristics of the IO terminal unit 63 in synchronization with the access request. That is, an access request issued from the CPU 7 to the external device control unit 61 via the bus controller 8 is fetched, an access start delay instruction is issued to the external device control unit 61, and electrical characteristics corresponding to the access request are set. The IO terminal unit 63 is set, and the access start delay instruction is canceled.
  • the IO terminal unit 63 can switch an electrical characteristic which is at least one of current drive capability and output voltage slew rate by setting, and outputs an access command or data from the external device control unit 61 to the first external bus 4. Then, data from the first external bus 4 is input.
  • the slew rate of the output voltage indicates the amount of change per unit time of the output voltage, and represents the steepness (rate of change) of the rise or fall of the output voltage.
  • the switchable electrical characteristics are not limited to the current drive capability and the output voltage slew rate, but may be the amplitude of the output voltage, the output impedance, the input impedance, or the like.
  • the IO terminal unit 63 includes the same number of sets of the receiver 632, the driver 633, the driver 634, and the through adjustment unit 635 as the number of bits of the first external bus 4.
  • the number of bits of the first external bus 4 here includes all of the data bus, the address bus, and various control signals.
  • the receiver 632 receives a 1-bit signal from the first external bus 4.
  • the two drivers 633 and 634 can switch the current drive capability by switching whether only one outputs a signal or both output signals simultaneously.
  • a 1-bit signal is output to the first external bus 4.
  • the driver 633 and the driver 634 may have the same current driving capability or different driving capabilities. In the former case, the current driving capability can be switched in two stages, and in the latter case, switching can be performed in three stages. Further, in order to easily realize switching of the current driving capability at three or more stages, a configuration in which one or more drivers are further connected in parallel to the driver 633 and the driver 634 may be employed.
  • the through adjustment unit 635 adjusts the slew rate of the output signal of the driver 633 and / or the driver 634.
  • the IO terminal control unit 62 includes an access start delay control unit 621, an IO control information generation unit 622, and a first access information register 624.
  • the access start delay control unit 621 When an access request is issued from the CPU 7 via the bus controller 8, the access start delay control unit 621 outputs an access start delay instruction to the external device control unit 61, and the setting of the electrical characteristics of the IO terminal control unit 62 is performed. Release access start delay instruction when completed.
  • the first access information register 624 is a register that holds the content of an access request (hereinafter referred to as access information) issued from the CPU 7 to the external device control unit 61 via the bus controller 8.
  • the access information includes, for example, an address, R / W (read or write), data size, and the like.
  • the IO control information generation unit 622 has an IO control pattern holding unit 6221 inside.
  • the IO control pattern holding unit 6221 holds a plurality of control patterns written in advance by the CPU 7.
  • the plurality of control patterns indicate at least one of current drive capability and output voltage slew rate (that is, electrical characteristics to be set) corresponding to each of the plurality of external devices.
  • the IO control information generation unit 622 determines an access destination (external device 2 or external device 3) by referring to the access information, and refers to the IO control pattern holding unit 6221. A control pattern corresponding to the access destination is selected, IO control information for setting the electrical characteristics is generated according to the control pattern, and the electrical characteristics of the IO terminal unit 63 are set according to the IO control information.
  • the LSI 1 has a CPU 7, a bus controller 8, and an external bus interface 6 as basic configurations, and performs data transfer with the external device 2 and the external device 3 via the first external bus 4.
  • the external bus interface 6 has an external device control unit 61 for generating an access control signal to an external device and an IO terminal unit 63 for inputting / outputting a signal to / from the first external bus 4 as a basic configuration.
  • the IO terminal unit 63 can change the output current amount and the slew rate by setting from the IO terminal control unit 62.
  • the operation when the system operation mode is boot loading and the boot code is stored in the external device 2 will be described.
  • the CPU 7 registers in the IO control pattern holding unit 6221 via the internal bus as an access destination where the output current and the slew rate should be set large as the electrical characteristics of the IO terminal.
  • the CPU 7 starts access to the external device 2 in order to transfer the boot code to the LSI.
  • the bus controller 8 accesses the external bus interface 6, and the external device controller 61 notifies the IO terminal controller 62 that access to the external device 2 is started before starting access to the external device 2. To do.
  • the IO terminal control unit 62 holds in the first access information register 624 that the current access is an access to the external device 2, notifies the IO control information generation unit 622, and the access start delay control unit 621 stores the external device
  • the control unit 61 is notified to suspend the start of access to the external device 2.
  • the IO control information generation unit 622 refers to the first access information register 624 and the IO control pattern holding unit 6221. It is detected that the access to the external device 2 is an access in which the output current and the slew rate should be increased, and the output current control and the slew rate are set to be large for the IO terminal unit 63.
  • the access start delay control unit 621 notifies the external device control unit 61 of cancellation of the suspension of access to the external device 2.
  • the external device control unit 61 outputs a signal for an external bus to the IO terminal unit 63, and the IO terminal unit 63 drives the first external bus 4 with electrical characteristics that increase the output current and the slew rate.
  • the external device 2 is accessed.
  • the IO terminal control unit 62 resets the output current and the slew rate of the IO terminal unit 63 to be small.
  • the output current and the slew rate of the IO terminal unit 63 become large only for the access to the external device 2. Therefore, boot code transfer from the external device 2 can be realized at a high data transfer rate, the boot time can be shortened, and unnecessary radiation and bus current consumption that occur when accessing the external device 3 can be suppressed.
  • the first modification will be described.
  • the external bus interface in the LSI not only the external bus interface in the LSI but also the IO terminal in the external device can be changed by setting the electrical characteristics, and the external interface is synchronized with the access request.
  • a configuration for instructing the external device to set the electrical characteristics of the IO terminal of the external device will be described.
  • FIG. 2 is a block diagram showing the configuration of the LSI system in the first modification example of the first embodiment.
  • the LSI system of FIG. 2 is different from that of FIG. 1 in that an external IO control unit 9 and an IO control bus 5 are added, and an external device 2 includes an IO terminal unit 21, an IO terminal unit 22, and an IO terminal control unit 23.
  • the external IO control unit 24 is different from the external device 3 in that the external device 3 includes an IO terminal unit 31, an IO terminal unit 32, an IO terminal control unit 33, and an external IO control unit 34. Explanation of the same points is omitted, and different points will be mainly described below.
  • the external IO control unit 9 includes an external IO control register 91, an IO switching counting unit 92, and an IO terminal unit 93, and receives an instruction indicating a control pattern corresponding to an external device to be accessed from the IO terminal control unit 62. Via the bus 5, the external device is instructed to set the electrical characteristics of the IO terminal of the external device.
  • the external IO control register 91 stores IO terminal discrimination information for each external device.
  • the IO switching counting unit 92 counts the stabilization time required for changing the electrical characteristics of the IO terminal of the external device, and notifies the IO terminal control unit 62 when the stabilization time has elapsed.
  • the IO terminal unit 93 is connected to the IO control bus 5.
  • the IO control bus 5 is a dedicated bus for instructing electrical characteristics to an external device, and may have a bus width of several bits.
  • the output current and slew rate of the IO terminal in the external device can be set via the IO control bus 5 in synchronization with the access request to the external device. Further, by providing the IO switching counting unit 92, it is possible to count the stabilization time of the change of the electrical characteristics of the IO terminal in the external device on the LSI 1 side, and to ensure the stable period, that is, to complete the change of the electrical characteristics without fail. it can.
  • an LSI system that secures the time when it takes time to determine the change in the electrical characteristics of the IO terminal unit 63 will be described. Furthermore, when the current access destination matches the previous access destination, the setting of the electrical characteristics of the IO terminal unit 63 can be omitted, and an external device is accessed in an access cycle linked to the electrical characteristics of the IO terminal. An LSI system that can be used will be described.
  • FIG. 3 is a block diagram showing a configuration of the LSI system in the second modification example of the first embodiment.
  • the LSI system of FIG. 3 includes an IO switching counting unit 623, a switching stability notification unit 631, a second access information register 625, a determination unit 6222, a prohibition unit 6223 and an IO control synchronous access parameter register 611. Is different. Explanation of the same points is omitted, and different points will be mainly described below.
  • the IO switching counting unit 623 includes a counter 6231 as a measuring unit that measures a predetermined time from the start of switching of the IO terminal unit 63, and a selector.
  • the selector selects either the timeout notification of the counter 6231 or the switching completion notification from the switching stability notification unit 631.
  • the fixed time is a time required for switching the electrical characteristics of the IO terminal unit 63.
  • the IO terminal control unit 62 cancels the access start delay instruction to the external device control unit 61 when receiving a notification that a certain time has passed or a switching completion notification from the IO switching counting unit 623. With this cancellation, the external device control unit 61 starts access to the external device.
  • the switching stability notification unit 631 outputs a completion notification notifying that the switching of the electrical characteristics of the IO terminal unit 63 has been completed to the IO terminal control unit 62.
  • the second access information register 625 is a register that holds the previous access information, that is, holds information indicating the external device of the previous access destination.
  • the determination unit 6222 determines whether or not the current access destination matches the previous access destination.
  • the prohibition unit 6223 prohibits the setting of the electrical characteristics of the IO terminal unit 63 when it is determined by the determination unit 6222 that they match.
  • the IO control information generation unit 622 cancels the access start delay instruction to the external device control unit 61 when the determination unit 6222 determines that they match, and sets the electrical characteristics for the IO terminal unit 63. Do not start.
  • the setting of the electrical characteristics of the IO terminal unit 63 can be omitted, and the access delay caused by setting the electrical characteristics of the IO terminal unit 63 Can be reduced.
  • the IO control synchronous access parameter register 611 is a parameter holding unit that holds a plurality of access parameters.
  • the external device control unit 61 selects an access parameter corresponding to the setting of the electrical characteristics to the IO terminal unit 63 of the IO terminal control unit 62 from the IO control synchronous access parameter register 611, and accesses the external device according to the access parameter.
  • the access parameter indicates an access control signal assert cycle, an address cycle, or the like.
  • the external device control unit 61 synchronizes access parameters such as an access control signal assert cycle and an address cycle with the IO terminal control unit 62 when the output current and slew rate of the IO terminal unit 63 are changed for the external device. And an IO control synchronous access parameter register 611 that is referred to when the change is made.
  • the bus controller 8 when a plurality of masters access the same external device, the bus controller 8 notifies the master bus identification information to the external bus interface 6, and when the master is a specific master, The device control unit 61 may change the setting of the access parameter, and the IO terminal control unit 62 may perform control such as changing the setting of the output current and the slew rate of the IO terminal unit 63.
  • a counter 6231 is provided in the IO switching counter 623 in the IO terminal controller 62 as means for measuring the stabilization time of the electrical characteristics of the IO terminal 63, and the IO terminal 63 is further provided with a counter 6231.
  • the switching stability notification unit 631 having the same function is provided, either one may be used.
  • the second access information register 625 holds access information corresponding to the previous access request. Instead, the external device control unit 61 receives information on the next access of the current access. It is good also as a structure which hold
  • the output current and the slew rate of the IO terminal unit 63 are not set small each time the access is completed, and higher-speed data transfer can be realized. it can.
  • the second access information register 625 holds information indicating the current electrical characteristics set in the IO terminal unit 63, and the determination unit 6222 holds the electrical characteristics corresponding to a new access request and the register. It is determined whether or not the current electrical characteristics indicated by the received information match, and the setting of the electrical characteristics of the IO terminal unit 63 is prohibited when the prohibition unit determines that they match by the determination unit. Also good.
  • the external device control unit 61 is provided with an IO control command IF 612 instead of the external IO control unit 9 and the IO control bus 5, and an external device is inserted by a method such as inserting a command between accesses via the first external bus 4. May be notified of IO terminal setting information.
  • the IO control bus 5 can be dispensed with.
  • a plurality of external bus interfaces as described above (first external interface and second external interface) and setting information indicating the current setting value of the electrical characteristics at the IO terminal of the second external bus interface are stored.
  • the first external bus interface synchronizes the electrical characteristics of the IO terminal portion of the first external bus interface with the access request in accordance with the setting information held in the setting information register. To decide.
  • the electrical characteristics of the IO terminal unit can be changed according to the operation status of another external bus interface in the LSI. For example, avoiding a situation in which both the first external interface and the second external interface are unfavorable in terms of power consumption and unnecessary radiation, such as accessing with a large current drive capability and a high slew rate at the same time. Enable.
  • FIG. 4 is a block diagram showing a configuration of the LSI system according to the second embodiment of the present invention.
  • the LSI system of FIG. 4 includes an LSI 1, an external device 2 and an external device 11 connected to the first external bus 4, and an external device 12 and an external device 13 connected to the second external bus 10.
  • the LSI 1 includes an external bus interface 6, an external bus interface 15, a CPU 7, a bus controller 8, an IO control information sharing register 14, a DSP 16, and a memory control unit 17.
  • the memory control unit 17 is connected to the memory 42.
  • External bus interfaces 6 and 15 have the same configuration as the external bus interface described in the first embodiment.
  • the LSI 1 includes a plurality of external bus interfaces.
  • the external bus interface 15 is connected to the external devices 12 and 13 via the second external bus 10.
  • the CPU 7 and the data processing DSP 16 in the LSI 1 use the memory 42 as a local memory.
  • the memory control unit 17 arbitrates a memory access request from the CPU 7 or a memory access request from the DSP 16 via the bus controller 8.
  • the IO control information sharing register 14 is a register for storing IO control information for an external device connected to the external bus interface.
  • the external bus interface is referred to when setting the electrical characteristics of the IO terminal when accessing the external device. Determine the value.
  • the operation mode of the system shifts from boot loading to the normal mode, and the pre-processing data of the DSP 16 is stored in the external device 12 in the normal mode.
  • boot loading data transfer of the boot code stored in the external device 2 is mainly performed.
  • the output current and the slew rate are largely controlled as electrical characteristics of the IO terminal, and the output current and the slew rate are large as control information for the external bus interface 6 of the IO control information sharing register 14. Is output.
  • the external bus interface 15 When the external bus interface 15 starts accessing the external device 12 during the access, the external bus interface 15 refers to the IO control information sharing register 14 and the external bus interface 6 outputs the output current and slew rate to the IO terminal. Therefore, the output current to the IO terminal and the slew rate are set to be small.
  • the access frequency to the external device 2 decreases, and data transfer of pre-processing data stored in the external device 12 is mainly performed. While accessing the external device 12, the output current and the slew rate are largely controlled as the electrical characteristics of the IO terminal, and the output current and the slew rate are large as the control information of the external bus interface 15 of the IO control information sharing register 14. Output.
  • the external bus interface 6 When the external bus interface 6 starts accessing the external device 2 during the access, the external bus interface 6 refers to the IO control information sharing register 14 and the external bus interface 15 outputs the output current and slew rate to the IO terminal. Therefore, the output current to the IO terminal and the slew rate are set to be small.
  • Other modes that are distinguished from the normal mode as the system operation mode include a sleep mode and a standby mode in which functions other than those necessary for the restart are suspended until a restart instruction is given from the outside. In these modes, there is little access to external devices. In this case, the output current to the IO terminal and the slew rate are set small.
  • the plurality of external bus interfaces controls the electrical characteristics of the IO terminal for each access of the external device, and at the same time performs adjustment so that the output current and the slew rate are not set large. Unwanted radiation and power consumption can be reduced.
  • the external bus interface may set the setting frequency information of the electrical characteristics of the IO terminal together.
  • the setting condition may be set according to the operation mode of the LSI 1 alone.
  • the CPU 7 may set the information based on the information set in the system register 20 by the system control CPU 43 according to the operation status of the system.
  • the external bus interface 6 is set to a high setting frequency
  • the external bus interface 15 is set to a low setting frequency.
  • the external bus interface 6 sets the electrical characteristics of the IO terminal to a large value except for the output current and the slew rate for two times in 10 accesses, and the external bus interface 15 is set to a small value for 10 times.
  • the electrical characteristics of the IO terminal are set to a large value except for the output current and the slew rate.
  • the output current and the slew rate of the IO terminal of the other external interface are set to be small.
  • the external bus interface can set together the setting frequency information of the electrical characteristics of the IO terminal for each external interface, and reduction adjustment of unnecessary radiation and power consumption for each external device can be performed. .
  • FIG. 5 is a block diagram showing a configuration of an LSI system according to the first modification of the second embodiment.
  • the system control CPU 43 controls the LSI 1 by performing reset control and power supply control for each device, and exchanging control information with the internal CPU 7 of the LSI 1 via the external communication interface 41 of the LSI 1.
  • the LSI 1 may be configured to include the IO toggle rate calculation unit 18. That is, for each IO used by the external bus interface, the information of the IO toggle rate calculation unit 18 that calculates the toggle rate that is a ratio of switching the setting of the electrical property is used, and the electrical property of the IO terminal for each external bus interface.
  • the setting frequency information may be set together.
  • the external bus interface can set the setting frequency information of the electrical characteristics of the IO terminal for each external interface based on the actual usage status of the IO.
  • a power supply monitor 44 is provided on the system board to detect the fluctuation level of the supply current on the system board, and the system control CPU 43 notifies the power supply status register 19 of the fluctuation degree of the supply current on the system board. If it is large, the IO control information supply register may be set to set the output current and slew rate of the IO terminal to be small, and the external bus interface may be controlled to set the output current and slew rate of the IO terminal to be small.
  • the external bus interface detects the frequency of the synchronous bus clock.
  • the output current and the slew rate may be controlled to be set large.
  • the synchronous bus clock may be input as a bus master by the LSI 1 or an external master.
  • a handshake signal is used as a protocol with the external master, the output of the handshake signal to the external master may be delayed until the electrical characteristics of the IO terminal are switched stably.
  • the electrical specifications of the external bus are specified with respect to the frequency of the synchronous bus clock, and the unnecessary radiation is set by setting the output current and the slew rate of the electrical characteristics of the IO terminal to be small within a range not exceeding the specification. And current consumption can be reduced.
  • An external bus interface is an external device having different transfer rates required in an operation mode, or a system in which a plurality of external devices having different required transfer rates are connected via a shared bus. Since it has a control unit that switches the electrical characteristics of the connection IO for each operation mode or external device, it is useful for application to a system LSI or the like that is required to reduce unnecessary radiation or power consumption.

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Abstract

An external bus interface (6) is provided to an LSI, which performs access to a plurality of external devices through an external bus according to an access request, and is provided with an I/O terminal unit (63) that can switch an electrical property, which is either the current drive capability and/or the throughput of output voltage, according to a setting and which performs input and output of signals with respect to the external bus; and an I/O terminal controller (62) for performing setting of the electrical property of the I/O terminal in synchronization with the access request. The I/O terminal controller (62), upon receiving the access request, selects a control pattern corresponding to an external device of the access destination, and can perform setting of the electrical property according to the control pattern.

Description

外部バスインタフェース、ＬＳＩおよびシステムExternal bus interface, LSI and system
　本発明は外部バスを経由して接続されたデバイス間のデータ転送において低不要輻射および低消費電力を実現するＩＯ端子の特性調整に関するものである。 The present invention relates to a characteristic adjustment of an IO terminal that realizes low unnecessary radiation and low power consumption in data transfer between devices connected via an external bus.
　従来、デバイス間の接続で使用する端子に対してＩＯ端子の特性を調整する技術としては、転送エラーを検出してエラーを発生させないレベルでのＩＯ端子の出力電流の低減による不要輻射の削減を行っているものがある（例えば、特許文献１参照）。図６は、前記特許文献１に記載された従来のメモリ制御装置を示す図である。 Conventionally, as a technique for adjusting the characteristics of an IO terminal with respect to a terminal used for connection between devices, it is possible to reduce unnecessary radiation by reducing the output current of the IO terminal at a level at which a transfer error is detected and no error is generated. There is something that is done (see, for example, Patent Document 1). FIG. 6 is a diagram showing a conventional memory control device described in Patent Document 1. In FIG.
　図６において、メモリ制御装置は、メモリ９０７と、メモリ９０７を駆動するメモリインターフェース部９０６と、メモリインターフェース部９０６を介してメモリ９０７へのデータの書き込みおよびメモリ９０７からの読み出しを制御するメモリ制御部９０３を備え、メモリインターフェース部９０６に電流切換部９０４および電圧切換部９０５を設け、メモリ制御部９０３にタイミング生成部９０１、検査実施／判定部９０２およびアクセス状況判定部９３１を設けている。 In FIG. 6, the memory control device includes a memory 907, a memory interface unit 906 that drives the memory 907, and a memory control unit that controls writing of data to the memory 907 and reading from the memory 907 via the memory interface unit 906. 903, the memory interface unit 906 is provided with a current switching unit 904 and a voltage switching unit 905, and the memory control unit 903 is provided with a timing generation unit 901, an inspection execution / determination unit 902, and an access status determination unit 931.
　検査実施／判定部９０２は、メモリ９０７への書き込みデータとメモリ９０７からの読み出しデータが一致するかどうかの検査を実施してその良否を判定し、検査の良否の判定結果を、タイミング生成部９０１と電流切換部９０４と電圧切換部９０５へ出力している。また前記アクセス状況判定部９３１は、メモリ９０７のアクセス状況を監視して任意の基準値と比較し、アクセス状況が粗かどうか密かどうかを判定し、その判定結果をタイミング生成部９０１へ出力している。 The inspection execution / determination unit 902 performs an inspection to determine whether the write data to the memory 907 and the read data from the memory 907 match to determine whether or not the inspection data is good. And output to the current switching unit 904 and the voltage switching unit 905. The access status determination unit 931 monitors the access status of the memory 907 and compares it with an arbitrary reference value, determines whether the access status is rough or dense, and outputs the determination result to the timing generation unit 901. Yes.
　また前記電流切換部９０４は、検査実施／判定部９０２から入力する検査の判定結果に応じて、メモリインターフェース部９０６の出力電流（メモリ９０７の駆動電流）を任意の値に切り換え、検査実施／判定部９０２の判定結果に応じて、メモリインターフェース部９０６の出力電流を切り換えている。これにより、メモリデータエラーを回避しながらメモリ９０７への駆動電流と駆動電圧を最適化し、消費電力や不要輻射を減少させる。 The current switching unit 904 switches the output current of the memory interface unit 906 (drive current of the memory 907) to an arbitrary value in accordance with the test determination result input from the test execution / determination unit 902, and performs the test execution / determination. The output current of the memory interface unit 906 is switched according to the determination result of the unit 902. This optimizes the drive current and drive voltage to the memory 907 while avoiding memory data errors, and reduces power consumption and unnecessary radiation.
特開２００６－９１９４０号公報JP 2006-91940 A 特開２００６－２５１８３７号公報JP 2006-251837 A
　しかしながら、前記従来の構成では、メモリーエラーを回避できる出力電流条件の探索のために検査サイクルをメモリに行う必要があり、メモリバスの転送帯域を消費すること、また、メモリ接続は１対１を想定しているため、さまざまな電気的特性を有する複数デバイスをバスで接続したシステムには適用できないという問題がある。 However, in the conventional configuration, it is necessary to perform a test cycle in the memory in order to search for an output current condition that can avoid a memory error, which consumes a transfer bandwidth of the memory bus, and the memory connection is 1: 1. Therefore, there is a problem that it cannot be applied to a system in which a plurality of devices having various electrical characteristics are connected by a bus.
　本発明は、前記従来の課題を解決するもので、ＩＯ端子における電流駆動能力等の電気的特性の最適化を、電気的特性の異なる複数の外部デバイスが接続されている場合でも実施する外部バスインタフェース、ＬＳＩおよびＬＳＩシステムを提供することを目的とする。 The present invention solves the above-mentioned conventional problem, and optimizes the electrical characteristics such as current drive capability at the IO terminal even when a plurality of external devices having different electrical characteristics are connected. An object is to provide an interface, an LSI, and an LSI system.
　前記従来の課題を解決するために、本発明の１側面における外部バスインタフェースは、アクセス要求に従って外部バスを介して複数の外部デバイスにアクセスするＬＳＩに備えられる外部バスインタフェースであって、電流駆動能力および出力電圧のスルーレートの少なくとも一方である電気的特性を設定により切り替え可能であり前記外部バスに信号を入出力するＩＯ端子と、前記アクセス要求に同期して前記ＩＯ端子の電気的特性の設定を行うＩＯ端子制御部とを備える。 In order to solve the above-described conventional problems, an external bus interface according to one aspect of the present invention is an external bus interface provided in an LSI that accesses a plurality of external devices via an external bus according to an access request, and has a current driving capability. And at least one of the slew rates of the output voltage can be switched by setting, an IO terminal for inputting / outputting a signal to / from the external bus, and setting of the electrical characteristics of the IO terminal in synchronization with the access request And an IO terminal control unit.
　本構成によって、アクセス要求に同期してＩＯ端子の電気的特性の設定を行うので、ＩＯ端子の電気的特性の最適化を、複数の外部デバイスのうちの何れの外部デバイスへのアクセスに対しても実施することができる。 With this configuration, since the electrical characteristics of the IO terminal are set in synchronization with the access request, optimization of the electrical characteristics of the IO terminal can be performed with respect to any external device among a plurality of external devices. Can also be implemented.
　ここで、前記ＩＯ端子制御部は、予めＣＰＵによって書き込まれた複数の制御パターンを保持する制御パターン保持部を有し、前記複数の制御パターンは、前記複数の外部デバイスのそれぞれに対応する電流駆動能力および出力電圧のスルーレートの少なくとも一方を示し、前記ＩＯ端子制御部は、前記アクセス要求を受けたとき、アクセス先の外部デバイスに対応する制御パターンを選択し、当該制御パターンに従って前記電気的特性の設定を行うようにしてもよい。 Here, the IO terminal control unit includes a control pattern holding unit that holds a plurality of control patterns written in advance by the CPU, and the plurality of control patterns correspond to current driving corresponding to each of the plurality of external devices. When the access request is received, the IO terminal control unit selects a control pattern corresponding to the external device to be accessed, and the electrical characteristics according to the control pattern. You may make it perform the setting of.
　この構成によれば、外部デバイス毎に最適な制御パターンを設定することができる。また、異なる外部デバイスおよび異なる外部バスに対しても最適な電気的特性を柔軟に設定することができる。 According to this configuration, an optimal control pattern can be set for each external device. In addition, optimal electrical characteristics can be flexibly set for different external devices and different external buses.
　ここで、前記外部バスインタフェースは、前記アクセス要求に従って外部デバイスへのアクセスを制御する外部デバイス制御部を備え、前記外部デバイス制御部は、複数のアクセスパラメータを保持するパラメータ保持部を有し、前記ＩＯ端子制御部の前記ＩＯ端子への電気的特性の設定に対応した前記アクセスパラメータを選択し、前記外部デバイスへアクセスするようにしてもよい。 Here, the external bus interface includes an external device control unit that controls access to an external device according to the access request, and the external device control unit includes a parameter storage unit that stores a plurality of access parameters, You may make it select the said access parameter corresponding to the setting of the electrical property to the said IO terminal of an IO terminal control part, and access the said external device.
　本構成によって、ＩＯ端子の電気的特性に連動したアクセスサイクルで外部デバイスにアクセスすることができる。 This configuration enables access to an external device in an access cycle linked to the electrical characteristics of the IO terminal.
　ここで、前記ＩＯ端子制御部は、さらに、切り替え開始から一定時間を計測する計測手段を備え、前記外部デバイス制御部は、前記一定時間の経過後に、前記外部デバイスへのアクセスを開始するようにしてもよい。 Here, the IO terminal control unit further includes a measuring unit that measures a predetermined time from the start of switching, and the external device control unit starts access to the external device after the predetermined time elapses. May be.
　本構成によって、ＩＯ端子の電気的特性を変更した場合に特性が安定する時間を要する場合に対応することができる。 This configuration can cope with the case where it takes time for the characteristics to stabilize when the electrical characteristics of the IO terminal are changed.
　ここで、前記ＩＯ端子制御部は、さらに、前回のアクセス先の外部デバイスを示す情報を保持するレジスタと、今回のアクセス先と前回のアクセス先とが一致するか否かを判定する判定部と、前記判定部により一致すると判定されたとき、前記ＩＯ端子部の電気的特性の設定を禁止する禁止部とを備えるようにしてもよい。 Here, the IO terminal control unit further includes a register that holds information indicating an external device that is the previous access destination, and a determination unit that determines whether or not the current access destination matches the previous access destination. And a prohibiting unit that prohibits the setting of the electrical characteristics of the IO terminal unit when it is determined by the determining unit that they match.
　本構成によって、今回のアクセス先と前回のアクセス先とが一致する場合には、前記ＩＯ端子部の電気的特性の設定を禁止するので、ＩＯ端子の電気的特性の設定対象の外部デバイスのアクセス毎にＩＯ端子の電気的特性の安定する時間分の外部アクセスの遅延時間を削減することができる。 According to this configuration, when the current access destination matches the previous access destination, the setting of the electrical characteristics of the IO terminal unit is prohibited, so the access of the external device to be set with the electrical characteristics of the IO terminal is prohibited. It is possible to reduce the external access delay time corresponding to the time during which the electrical characteristics of the IO terminal are stabilized.
　ここで、前記ＩＯ端子制御部は、さらに、前記ＩＯ端子部に設定されている現在の電気的特性を示す情報を保持するレジスタと、新たなアクセス要求に対応する電気的特性と、前記レジスタに保持された情報が示す現在の電気的特性とが一致するか否かを判定する判定部と、前記判定部により一致すると判定されたとき、前記ＩＯ端子部の電気的特性の設定を禁止する禁止部とを備える構成としてもよい。 Here, the IO terminal control unit further includes a register holding information indicating current electrical characteristics set in the IO terminal unit, electrical characteristics corresponding to a new access request, and the register. A determination unit that determines whether or not the current electrical characteristics indicated by the stored information match, and a prohibition that prohibits setting of the electrical characteristics of the IO terminal unit when the determination unit determines that the current characteristics match It is good also as a structure provided with a part.
　この構成によれば、新たなアクセス要求に対応する電気的特性と、現在設定されている電気的特性とが一致する場合には、前記ＩＯ端子部の電気的特性の設定を禁止するので、ＩＯ端子の電気的特性の安定する時間分の外部アクセスの遅延時間を削減することができる。 According to this configuration, when the electrical characteristic corresponding to the new access request matches the currently set electrical characteristic, the setting of the electrical characteristic of the IO terminal unit is prohibited. It is possible to reduce the external access delay time corresponding to the time when the electrical characteristics of the terminal are stabilized.
　ここで、前記外部インタフェースは、さらに、前記アクセス要求に同期して、前記外部デバイスに対して、外部デバイスのＩＯ端子の電気的特性の設定を指示する外部ＩＯ指示部を備える構成としてもよい。 Here, the external interface may further include an external IO instruction unit that instructs the external device to set the electrical characteristics of the IO terminal of the external device in synchronization with the access request.
　本構成によって、特定の外部デバイスアクセスに対して外部デバイスのＩＯ端子の電気的特性を変更することができる。 This configuration can change the electrical characteristics of the IO terminal of the external device for a specific external device access.
　また、本発明の１側面におけるＬＳＩは、上記の外部バスインタフェースと同じ構成であり、アクセス要求に従って第１外部バスを介して複数の外部デバイスにアクセスする第１バスインタフェースと、上記の外部バスインタフェースと同じ構成であり、アクセス要求に従って第２外部バスを介して他の複数の外部デバイスにアクセスする第２バスインタフェースと、第２外部バスインタフェースのＩＯ端子における現在の電気的特性の設定値を示す設定情報を保持する設定情報レジスタとを備え、前記第１外部バスインタフェースは、前記設定情報レジスタに保持された設定情報に応じて、第１外部バスインタフェースのＩＯ端子部における電気的特性を前記アクセス要求に同期して決定する。 An LSI according to one aspect of the present invention has the same configuration as that of the external bus interface described above, and includes a first bus interface that accesses a plurality of external devices via the first external bus according to an access request, and the external bus interface described above. And the current electrical characteristic setting values at the IO terminals of the second bus interface and the second external bus interface for accessing other external devices via the second external bus according to the access request. A setting information register for holding setting information, wherein the first external bus interface accesses the electrical characteristics of the IO terminal portion of the first external bus interface according to the setting information held in the setting information register. Determine synchronously with the request.
　本構成によって、ＬＳＩ内の別の外部バスインタフェースの稼動状況に応じてＩＯ端子部の電気的特性を変更することができる。 This configuration makes it possible to change the electrical characteristics of the IO terminal unit according to the operating status of another external bus interface in the LSI.
　ここで、前記ＬＳＩは、さらに、前記ＬＳＩ内部又は前記ＬＳＩ外部のマスタから書き込み可能であり、外部デバイスに対応する電流駆動能力および出力電圧のスルーレートの少なくとも一方を示す制御パターンを保持するレジスタを有し、前記第１および第２外部バスインタフェースの少なくとも一方は、前記レジスタに保持された制御パターンに従って、ＩＯ端子部に設定すべき電気的特性を決定するようにしてもよい。 Here, the LSI further includes a register that can be written from a master inside or outside the LSI, and that holds a control pattern indicating at least one of a current drive capability and an output voltage slew rate corresponding to the external device. And at least one of the first and second external bus interfaces may determine an electrical characteristic to be set in the IO terminal unit in accordance with a control pattern held in the register.
　ここで、前記ＬＳＩは、さらに、ＬＳＩ内部もしくはＬＳＩ外部のマスタから書き込み可能であり、外部デバイスへのアクセス方法を規定するアクセスパラメータを保持するレジスタを有し、前記第１および第２外部バスインタフェースの少なくとも一方は、前記レジスタに保持されたアクセスパラメータに従って外部デバイスにアクセスするようにしてもよい。 Here, the LSI further includes a register that can be written from a master inside or outside the LSI, and has an access parameter that defines an access method to the external device, and the first and second external bus interfaces. At least one of these may access an external device in accordance with an access parameter held in the register.
　本構成によって、システム条件によってＩＯ端子部の電気的特性の設定を制御することができる。 This configuration makes it possible to control the setting of the electrical characteristics of the IO terminal section according to the system conditions.
　また、本発明の１側面におけるシステムは、上記のＬＳＩと、前記ＬＳＩ内部もしくはＬＳＩ外部のマスタとを備え、前記マスタは、第１の動作モードでは出力電流もしくはスルーレートを第１の値にするための制御パターンを前記レジスタに設定し、第１の動作モードよりもデータ転送レートが低い第２の動作モードでは出力電流もしくはスルーレートが第１の値よりも小さい第２の値にするための制御パターンを前記レジスタに設定する。 A system according to one aspect of the present invention includes the above-described LSI and a master inside or outside the LSI, and the master sets an output current or a slew rate to a first value in the first operation mode. And a control pattern for setting the output current or slew rate to a second value smaller than the first value in the second operation mode in which the data transfer rate is lower than that in the first operation mode. A control pattern is set in the register.
　本構成によって、データ転送レートによってＩＯ端子部の電気的特性を制御することができる。 This configuration makes it possible to control the electrical characteristics of the IO terminal unit according to the data transfer rate.
　また、本発明の他の１側面におけるシステムは、上記ののＬＳＩと、前記ＬＳＩ内部もしくはＬＳＩ外部のマスタとを備え、前記マスタは、第１の動作モードでは出力電流もしくはスルーレートを第１の値にするための制御パターンを前記レジスタに設定し、第１の動作モードよりも省電力で動作する第２の動作モードでは出力電流もしくはスルーレートが第１の値よりも小さい第２の値にするための制御パターンを前記レジスタに設定する。 A system according to another aspect of the present invention includes the above-described LSI and a master inside or outside the LSI, and the master outputs an output current or a slew rate in a first operation mode. A control pattern for setting a value is set in the register, and the output current or the slew rate is set to a second value smaller than the first value in the second operation mode in which the operation is performed with lower power consumption than in the first operation mode. A control pattern for this is set in the register.
　本構成によって、電源供給状況例えば省電力モードか否かによってＩＯ端子部の電気的特性を制御することができる。 This configuration makes it possible to control the electrical characteristics of the IO terminal section depending on the power supply status, for example, whether or not it is in the power saving mode.
　また、本発明のさらに他の１側面におけるシステムは、上記のＬＳＩと、前記ＬＳＩ内部もしくはＬＳＩ外部のマスタとを備え、前記マスタは、第１の動作モードでは出力電流もしくはスルーレートを第１の値にするための制御パターンを前記レジスタに設定し、第１の動作モードよりも外部バスの転送クロック周波数が低い第２の動作モードでは出力電流もしくはスルーレートが第１の値よりも小さい第２の値にするための制御パターンを前記レジスタに設定する。 According to still another aspect of the present invention, there is provided a system including the above-described LSI and a master inside or outside the LSI, wherein the master outputs an output current or a slew rate in a first operation mode. A control pattern for setting a value is set in the register, and in the second operation mode in which the transfer clock frequency of the external bus is lower than that in the first operation mode, the output current or slew rate is smaller than the first value. A control pattern for setting the value is set in the register.
　本構成によって、転送クロック周波数で定義されたバスの電気的仕様の範囲で転送クロックによってＩＯ端子部の電気的特性を制御することができる。 With this configuration, the electrical characteristics of the IO terminal unit can be controlled by the transfer clock within the range of the electrical specifications of the bus defined by the transfer clock frequency.
　本発明の外部バスインタフェースによれば、ＩＯ端子部の電気的特性の最適化を、複数の外部デバイスのうちの何れの外部デバイスへのアクセスに対しても実施することができる。 According to the external bus interface of the present invention, it is possible to optimize the electrical characteristics of the IO terminal unit for access to any external device among a plurality of external devices.
　さらに、電気的特性の設定変更時にＩＯ端子部の電気的特性が安定する時間を確保することができる。 Furthermore, it is possible to secure time for the electrical characteristics of the IO terminal section to stabilize when the electrical characteristics settings are changed.
　また、外部のマスタの制御の下でシステム条件に適した制御パターンを設定するので、外部バスインターフェースを異なるシステムに容易に実装することができる。 Also, since a control pattern suitable for system conditions is set under the control of an external master, the external bus interface can be easily implemented in different systems.
図１は、実施の形態１における外部バスインタフェースを備えるＬＳＩシステムの構成を示すブロック図である。FIG. 1 is a block diagram showing a configuration of an LSI system including an external bus interface according to the first embodiment. 図２は、実施の形態１における第１の変形例におけるＬＳＩシステムの構成を示すブロック図である。FIG. 2 is a block diagram showing a configuration of the LSI system in the first modification example of the first embodiment. 図３は、実施の形態１における第２の変形例におけるＬＳＩシステムの構成を示すブロック図である。FIG. 3 is a block diagram showing a configuration of the LSI system in the second modification example of the first embodiment. 図４は、本発明の実施の形態２における外部バスインタフェースを備えるＬＳＩシステムの構成を示すブロック図である。FIG. 4 is a block diagram showing a configuration of an LSI system including an external bus interface according to the second embodiment of the present invention. 図５は、実施の形態２における第１の変形例におけるＬＳＩシステムの構成を示すブロック図である。FIG. 5 is a block diagram showing a configuration of the LSI system in the first modification example of the second embodiment. 図６は、従来のメモリ制御装置の概略ブロック図である。FIG. 6 is a schematic block diagram of a conventional memory control device.
　以下本発明の実施の形態について、図面を参照しながら説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　（実施の形態１）
　本実施の形態では、アクセス要求に従って外部バスを介して複数の外部デバイスにアクセスするＬＳＩに備えられる外部バスインタフェースと、ＬＳＩについて説明する。特に、外部バスインタフェースは、電流駆動能力および出力電圧のスルーレートの少なくとも一方である電気的特性を設定により切り替え可能であり前記外部バスに信号を入出力するＩＯ端子部と、前記アクセス要求に同期して前記ＩＯ端子部の電気的特性の設定を行うＩＯ端子部制御部とを備える。これにより、ＩＯ端子の電気的特性の最適化を、複数の外部デバイスのうちの何れの外部デバイスへのアクセスに対しても可能にしている。 (Embodiment 1)
In the present embodiment, an external bus interface provided in an LSI that accesses a plurality of external devices via an external bus according to an access request, and the LSI will be described. In particular, the external bus interface can switch an electrical characteristic which is at least one of a current driving capability and an output voltage slew rate by setting, and is synchronized with the access request and an IO terminal unit which inputs / outputs a signal to / from the external bus. And an IO terminal unit control unit for setting the electrical characteristics of the IO terminal unit. As a result, optimization of the electrical characteristics of the IO terminal is made possible for access to any of the plurality of external devices.
　図１は本発明の実施の形態１における外部バスインタフェースを備えるＬＳＩシステムの構成を示すブロック図である。 FIG. 1 is a block diagram showing a configuration of an LSI system having an external bus interface according to the first embodiment of the present invention.
　同図のＬＳＩシステムは、ＬＳＩ１と、外部デバイス２と、外部デバイス３とを備える。ＬＳＩ１は、第１外部バス４を介して外部デバイス２および外部デバイス３と接続される。 The LSI system shown in the figure includes an LSI 1, an external device 2, and an external device 3. The LSI 1 is connected to the external device 2 and the external device 3 via the first external bus 4.
　ＬＳＩ１は、１チップの半導体装置であり、外部バスインタフェース６、ＣＰＵ７、バスコントローラ８を備える。 LSI 1 is a one-chip semiconductor device and includes an external bus interface 6, a CPU 7, and a bus controller 8.
　外部バスインタフェース６は、ＣＰＵ７からバスコントローラ８を介して発行されるアクセス要求に従って、第１の外部バス４を介して外部デバイス２および外部デバイス３にアクセスする。つまり、外部バスインタフェース６は、アクセス要求に従ってＬＳＩ１と外部デバイス２または外部デバイス３との間でデータ転送を行う。そのため外部バスインタフェース６は、外部デバイス制御部６１、ＩＯ端子制御部６２、ＩＯ端子部６３を備える。 The external bus interface 6 accesses the external device 2 and the external device 3 via the first external bus 4 in accordance with an access request issued from the CPU 7 via the bus controller 8. That is, the external bus interface 6 performs data transfer between the LSI 1 and the external device 2 or the external device 3 according to the access request. Therefore, the external bus interface 6 includes an external device control unit 61, an IO terminal control unit 62, and an IO terminal unit 63.
　外部デバイス制御部６１は、ＣＰＵ７からバスコントローラ８を介してアクセス要求を受け、アクセス要求およびアクセス先の外部デバイス２または外部デバイス３の仕様に応じたアクセスコマンドを生成し、ＩＯ端子部６３を介してアクセス先の外部デバイスに発行する。ただし、外部デバイス制御部６１は、ＩＯ端子制御部６２からアクセス開始遅延指示があったときアクセスコマンドの発行を保留し、ＩＯ端子制御部６２からアクセス開始遅延指示の解除があったときアクセスコマンドの発行を開始する。 The external device control unit 61 receives an access request from the CPU 7 via the bus controller 8, generates an access command corresponding to the access request and the specifications of the external device 2 or external device 3 to be accessed, and passes through the IO terminal unit 63. Issued to the external device to be accessed. However, the external device control unit 61 suspends issuance of an access command when an access start delay instruction is issued from the IO terminal control unit 62, and an access command is issued when the access start delay instruction is canceled from the IO terminal control unit 62. Start issuing.
　ＩＯ端子制御部６２は、アクセス要求に同期してＩＯ端子部６３の電気的特性の設定を行う。すなわち、ＣＰＵ７からバスコントローラ８を介して外部デバイス制御部６１に発行されるアクセス要求を取り込み、外部デバイス制御部６１にアクセス開始遅延指示を出し、当該アクセス要求に対応する電気的特性にするようにＩＯ端子部６３を設定し、アクセス開始遅延指示を解除する。 The IO terminal control unit 62 sets the electrical characteristics of the IO terminal unit 63 in synchronization with the access request. That is, an access request issued from the CPU 7 to the external device control unit 61 via the bus controller 8 is fetched, an access start delay instruction is issued to the external device control unit 61, and electrical characteristics corresponding to the access request are set. The IO terminal unit 63 is set, and the access start delay instruction is canceled.
　ＩＯ端子部６３は、電流駆動能力および出力電圧のスルーレートの少なくとも一方である電気的特性を設定により切替可能であり、外部デバイス制御部６１からのアクセスコマンドまたはデータを第１外部バス４に出力し、第１外部バス４からのデータを入力する。ここで、出力電圧のスルーレートとは、出力電圧の単位時間当たりの変化量を示し、出力電圧の立ち上がりまたは立ち下がりの急峻さ（変化率）を表す。また、切替可能な電気的特性は、電流駆動能力、出力電圧のスルーレートに限らず、出力電圧の振幅、出力インピーダンス、入力インピーダンスなどでもよい。 The IO terminal unit 63 can switch an electrical characteristic which is at least one of current drive capability and output voltage slew rate by setting, and outputs an access command or data from the external device control unit 61 to the first external bus 4. Then, data from the first external bus 4 is input. Here, the slew rate of the output voltage indicates the amount of change per unit time of the output voltage, and represents the steepness (rate of change) of the rise or fall of the output voltage. The switchable electrical characteristics are not limited to the current drive capability and the output voltage slew rate, but may be the amplitude of the output voltage, the output impedance, the input impedance, or the like.
　ＩＯ端子部６３は、レシーバ６３２、ドライバ６３３、ドライバ６３４、スルー調整部６３５のセットを、第１外部バス４のビット数と同数備える。ここでいう第１外部バス４のビット数は、データバス、アドレスバス、各種制御信号の全てを含む。 The IO terminal unit 63 includes the same number of sets of the receiver 632, the driver 633, the driver 634, and the through adjustment unit 635 as the number of bits of the first external bus 4. The number of bits of the first external bus 4 here includes all of the data bus, the address bus, and various control signals.
　レシーバ６３２は、第１外部バス４から１ビットの信号を入力する。 The receiver 632 receives a 1-bit signal from the first external bus 4.
　２つのドライバ６３３および６３４は、どちらか一方のみが信号を出力するか両方が同時に信号を出力するかを切り替えることにより、電流駆動能力を切替可能である。第１外部バス４に１ビットの信号を出力する。ドライバ６３３とドライバ６３４は同じ電流駆動能力であっても、異なる駆動能力であってもよい。前者の場合は電流駆動能力を２段階で切替可能に、後者の場合は３段階で切替が可能になる。また、電流駆動能力の３段階以上の切替を容易に実現するためには、ドライバ６３３およびドライバ６３４にさらに１つ以上のドライバを並列に接続した構成としてもよい。 The two drivers 633 and 634 can switch the current drive capability by switching whether only one outputs a signal or both output signals simultaneously. A 1-bit signal is output to the first external bus 4. The driver 633 and the driver 634 may have the same current driving capability or different driving capabilities. In the former case, the current driving capability can be switched in two stages, and in the latter case, switching can be performed in three stages. Further, in order to easily realize switching of the current driving capability at three or more stages, a configuration in which one or more drivers are further connected in parallel to the driver 633 and the driver 634 may be employed.
　スルー調整部６３５は、ドライバ６３３および／またはドライバ６３４の出力信号のスルーレートを調整する。 The through adjustment unit 635 adjusts the slew rate of the output signal of the driver 633 and / or the driver 634.
　上記のＩＯ端子制御部６２について、さらに具体的に説明する。上記のＩＯ端子制御部６２は、具体的には、アクセス開始遅延制御部６２１、ＩＯ制御情報生成部６２２、第１アクセス情報レジスタ６２４を備える。 The above-described IO terminal control unit 62 will be described more specifically. Specifically, the IO terminal control unit 62 includes an access start delay control unit 621, an IO control information generation unit 622, and a first access information register 624.
　アクセス開始遅延制御部６２１は、ＣＰＵ７からバスコントローラ８を介してアクセス要求が発行されたとき、アクセス開始遅延指示を外部デバイス制御部６１に出力し、ＩＯ端子制御部６２の電気的特性の設定が完了したときにアクセス開始遅延指示を解除する。 When an access request is issued from the CPU 7 via the bus controller 8, the access start delay control unit 621 outputs an access start delay instruction to the external device control unit 61, and the setting of the electrical characteristics of the IO terminal control unit 62 is performed. Release access start delay instruction when completed.
　第１アクセス情報レジスタ６２４は、ＣＰＵ７からバスコントローラ８を介して外部デバイス制御部６１に発行されたアクセス要求の内容（以下アクセス情報と呼ぶ）を保持するレジスタである。アクセス情報には、例えば、アドレス、Ｒ／Ｗ（リードかライトか）、データサイズ等が含まれる。 The first access information register 624 is a register that holds the content of an access request (hereinafter referred to as access information) issued from the CPU 7 to the external device control unit 61 via the bus controller 8. The access information includes, for example, an address, R / W (read or write), data size, and the like.
　ＩＯ制御情報生成部６２２は、内部にＩＯ制御パターン保持部６２２１を有する。ＩＯ制御パターン保持部６２２１は、予めＣＰＵ７によって書き込まれた複数の制御パターンを保持する。ここで、複数の制御パターンは、前記複数の外部デバイスのそれぞれに対応する電流駆動能力および出力電圧のスルーレートの少なくとも一方（つまり設定すべき電気的特性）を示す。 The IO control information generation unit 622 has an IO control pattern holding unit 6221 inside. The IO control pattern holding unit 6221 holds a plurality of control patterns written in advance by the CPU 7. Here, the plurality of control patterns indicate at least one of current drive capability and output voltage slew rate (that is, electrical characteristics to be set) corresponding to each of the plurality of external devices.
　ＩＯ制御情報生成部６２２は、アクセス要求が発行されたとき、アクセス情報を参照することによりアクセス先（外部デバイス２か外部デバイス３か）を判別し、ＩＯ制御パターン保持部６２２１を参照することにより当該アクセス先に対応する制御パターンを選択し、当該制御パターンに従って前記電気的特性の設定を行うためのＩＯ制御情報を生成し、当該ＩＯ制御情報に従ってＩＯ端子部６３の電気的特性を設定する。 When an access request is issued, the IO control information generation unit 622 determines an access destination (external device 2 or external device 3) by referring to the access information, and refers to the IO control pattern holding unit 6221. A control pattern corresponding to the access destination is selected, IO control information for setting the electrical characteristics is generated according to the control pattern, and the electrical characteristics of the IO terminal unit 63 are set according to the IO control information.
　以上説明してきたように、図１において、ＬＳＩ１は、ＣＰＵ７およびバスコントローラ８および外部バスインタフェース６を基本構成としており、第１外部バス４を介して外部デバイス２および外部デバイス３とデータ転送を行う。外部バスインタフェース６は、外部デバイスへのアクセス制御信号を生成するための外部デバイス制御部６１と、第１外部バス４に対し信号を入出力するためのＩＯ端子部６３を基本構成としている。ＩＯ端子部６３は、出力電流量やスルーレートをＩＯ端子制御部６２からの設定により変更可能である。 As described above, in FIG. 1, the LSI 1 has a CPU 7, a bus controller 8, and an external bus interface 6 as basic configurations, and performs data transfer with the external device 2 and the external device 3 via the first external bus 4. . The external bus interface 6 has an external device control unit 61 for generating an access control signal to an external device and an IO terminal unit 63 for inputting / outputting a signal to / from the first external bus 4 as a basic configuration. The IO terminal unit 63 can change the output current amount and the slew rate by setting from the IO terminal control unit 62.
　システムの動作モードがブートローディングであって、外部デバイス２にブートコードが格納されている場合の動作について説明する。ＣＰＵ７は内部バス経由でＩＯ制御パターン保持部６２２１に外部デバイス２はＩＯ端子の電気的特性として出力電流およびスルーレートを大に設定すべきアクセス先と登録する。ＣＰＵ７はブートコードをＬＳＩへ転送するために外部デバイス２へのアクセスを開始する。 The operation when the system operation mode is boot loading and the boot code is stored in the external device 2 will be described. The CPU 7 registers in the IO control pattern holding unit 6221 via the internal bus as an access destination where the output current and the slew rate should be set large as the electrical characteristics of the IO terminal. The CPU 7 starts access to the external device 2 in order to transfer the boot code to the LSI.
　まず、バスコントローラ８は外部バスインタフェース６にアクセスし、外部デバイス制御部６１は外部デバイス２へのアクセスを開始する前に、ＩＯ端子制御部６２へ外部デバイス２へのアクセスを開始する旨を通知する。 First, the bus controller 8 accesses the external bus interface 6, and the external device controller 61 notifies the IO terminal controller 62 that access to the external device 2 is started before starting access to the external device 2. To do.
　ＩＯ端子制御部６２は第１アクセス情報レジスタ６２４に今回のアクセスが外部デバイス２へのアクセスであることを保持し、ＩＯ制御情報生成部６２２に通知するとともに、アクセス開始遅延制御部６２１は外部デバイス制御部６１に外部デバイス２へのアクセス開始を保留するよう通知する。ＩＯ制御情報生成部６２２は、第１アクセス情報レジスタ６２４とＩＯ制御パターン保持部６２２１を参照する。外部デバイス２へのアクセスが出力電流およびスルーレートが大にすべきアクセスであることを検出し、ＩＯ端子部６３に対して出力電流制御およびスルーレートを大に設定する。設定完了後、アクセス開始遅延制御部６２１は外部デバイス制御部６１に外部デバイス２へのアクセスの保留の解除を通知する。これにより、外部デバイス制御部６１はＩＯ端子部６３に外部バス用の信号を出力し、ＩＯ端子部６３は出力電流およびスルーレートが大となる電気的特性で第１の外部バス４をドライブすることにより外部デバイス２にアクセスする。外部デバイス制御部から外部デバイスアクセスが終了した場合は、ＩＯ端子制御部６２は、ＩＯ端子部６３の出力電流およびスルーレートを小に再設定しておく。 The IO terminal control unit 62 holds in the first access information register 624 that the current access is an access to the external device 2, notifies the IO control information generation unit 622, and the access start delay control unit 621 stores the external device The control unit 61 is notified to suspend the start of access to the external device 2. The IO control information generation unit 622 refers to the first access information register 624 and the IO control pattern holding unit 6221. It is detected that the access to the external device 2 is an access in which the output current and the slew rate should be increased, and the output current control and the slew rate are set to be large for the IO terminal unit 63. After the setting is completed, the access start delay control unit 621 notifies the external device control unit 61 of cancellation of the suspension of access to the external device 2. As a result, the external device control unit 61 outputs a signal for an external bus to the IO terminal unit 63, and the IO terminal unit 63 drives the first external bus 4 with electrical characteristics that increase the output current and the slew rate. Thus, the external device 2 is accessed. When the external device access from the external device control unit is completed, the IO terminal control unit 62 resets the output current and the slew rate of the IO terminal unit 63 to be small.
　かかる構成によれば、外部デバイス２と外部デバイス３のアクセスが混在した場合には、外部デバイス２へのアクセスに対してのみＩＯ端子部６３の出力電流およびスルーレートが大となる。このため、外部デバイス２からのブートコード転送を高いデータ転送レートで実現し、ブート時間を短くするとともに、外部デバイス３へのアクセス時に発生する不要輻射およびバスの消費電流を抑制することができる。 According to such a configuration, when the access of the external device 2 and the external device 3 is mixed, the output current and the slew rate of the IO terminal unit 63 become large only for the access to the external device 2. Therefore, boot code transfer from the external device 2 can be realized at a high data transfer rate, the boot time can be shortened, and unnecessary radiation and bus current consumption that occur when accessing the external device 3 can be suppressed.
　なお、本実施形態におけるＬＳＩシステムは、図１の構成に対して種々の変形が可能である。以下、変形例について説明する。 It should be noted that the LSI system in this embodiment can be variously modified with respect to the configuration of FIG. Hereinafter, modified examples will be described.
　まず、第１の変形例について説明する。第１の変形例におけるＬＳＩシステムでは、ＬＳＩ内の外部バスインタフェースだけでなく、外部デバイス内のＩＯ端子部も電気的特性を設定により変更可能であり、外部インタフェースが、前記アクセス要求に同期して、前記外部デバイスに対して、外部デバイスのＩＯ端子の電気的特性の設定を指示する構成について説明する。 First, the first modification will be described. In the LSI system in the first modification, not only the external bus interface in the LSI but also the IO terminal in the external device can be changed by setting the electrical characteristics, and the external interface is synchronized with the access request. A configuration for instructing the external device to set the electrical characteristics of the IO terminal of the external device will be described.
　図２は、実施の形態１における第１の変形例におけるＬＳＩシステムの構成を示すブロック図である。 FIG. 2 is a block diagram showing the configuration of the LSI system in the first modification example of the first embodiment.
　図２のＬＳＩシステムは、図１と比較して、外部ＩＯ制御部９およびＩＯ制御バス５が追加された点と、外部デバイス２がＩＯ端子部２１、ＩＯ端子部２２、ＩＯ端子制御部２３、外部ＩＯ制御部２４を備える点と、外部デバイス３がＩＯ端子部３１、ＩＯ端子部３２、ＩＯ端子制御部３３、外部ＩＯ制御部３４を備える点が異なっている。同じ点は説明を省略して、以下異なる点を中心に説明する。 The LSI system of FIG. 2 is different from that of FIG. 1 in that an external IO control unit 9 and an IO control bus 5 are added, and an external device 2 includes an IO terminal unit 21, an IO terminal unit 22, and an IO terminal control unit 23. The external IO control unit 24 is different from the external device 3 in that the external device 3 includes an IO terminal unit 31, an IO terminal unit 32, an IO terminal control unit 33, and an external IO control unit 34. Explanation of the same points is omitted, and different points will be mainly described below.
　外部ＩＯ制御部９は、外部ＩＯ制御レジスタ９１、ＩＯ切替計数部９２、ＩＯ端子部９３を備え、ＩＯ端子制御部６２からアクセス先の外部デバイスに対応する制御パターンを示す指示を受け、ＩＯ制御バス５を介して、当該外部デバイスに対して、外部デバイスのＩＯ端子の電気的特性の設定を指示する。 The external IO control unit 9 includes an external IO control register 91, an IO switching counting unit 92, and an IO terminal unit 93, and receives an instruction indicating a control pattern corresponding to an external device to be accessed from the IO terminal control unit 62. Via the bus 5, the external device is instructed to set the electrical characteristics of the IO terminal of the external device.
　外部ＩＯ制御レジスタ９１は、外部デバイス毎のＩＯ端子の判別情報を格納する。 The external IO control register 91 stores IO terminal discrimination information for each external device.
　ＩＯ切替計数部９２は、外部デバイスのＩＯ端子の電気的特性の変更に要する安定時間を計数し、当該安定時間を経過した時点でＩＯ端子制御部６２に通知する。 The IO switching counting unit 92 counts the stabilization time required for changing the electrical characteristics of the IO terminal of the external device, and notifies the IO terminal control unit 62 when the stabilization time has elapsed.
　ＩＯ端子部９３は、ＩＯ制御バス５に接続される。 The IO terminal unit 93 is connected to the IO control bus 5.
　ＩＯ制御バス５は、外部デバイスに電気的特性を指示するための専用のバスであり、数ビットのバス幅があればよい。 The IO control bus 5 is a dedicated bus for instructing electrical characteristics to an external device, and may have a bus width of several bits.
　以上のように、外部デバイスへのアクセス要求に同期して外部デバイス内のＩＯ端子の出力電流およびスルーレートをＩＯ制御バス５を介して設定することができる。さらにＩＯ切替計数部９２を設けることにより、外部デバイス内のＩＯ端子の電気的特性の変更の安定時間をＬＳＩ１側で計数し、安定期間を確保つまり電気的特性の変更を確実に完了させることができる。 As described above, the output current and slew rate of the IO terminal in the external device can be set via the IO control bus 5 in synchronization with the access request to the external device. Further, by providing the IO switching counting unit 92, it is possible to count the stabilization time of the change of the electrical characteristics of the IO terminal in the external device on the LSI 1 side, and to ensure the stable period, that is, to complete the change of the electrical characteristics without fail. it can.
　次に、第２の変形例について説明する。第２の変形例では、ＩＯ端子部６３の電気的特性の変更が確定するまでに時間を要する場合に、当該時間を確保するＬＳＩシステムについて説明する。さらに、今回のアクセス先と前回のアクセス先とが一致する場合に、ＩＯ端子部６３の電気的特性の設定を省略可能であり、ＩＯ端子の電気的特性に連動したアクセスサイクルで外部デバイスにアクセスすることが可能なＬＳＩシステムについて説明する。 Next, a second modification will be described. In the second modification, an LSI system that secures the time when it takes time to determine the change in the electrical characteristics of the IO terminal unit 63 will be described. Furthermore, when the current access destination matches the previous access destination, the setting of the electrical characteristics of the IO terminal unit 63 can be omitted, and an external device is accessed in an access cycle linked to the electrical characteristics of the IO terminal. An LSI system that can be used will be described.
　図３は、実施の形態１における第２の変形例におけるＬＳＩシステムの構成を示すブロック図である。 FIG. 3 is a block diagram showing a configuration of the LSI system in the second modification example of the first embodiment.
　図３のＬＳＩシステムは、図２と比較して、ＩＯ切替計数部６２３、切替安定通知部６３１、第２アクセス情報レジスタ６２５、判定部６２２２、禁止部６２２３およびＩＯ制御同期アクセスパラメータレジスタ６１１が追加された点が異なっている。同じ点は説明を省略して、以下異なる点を中心に説明する。 Compared with FIG. 2, the LSI system of FIG. 3 includes an IO switching counting unit 623, a switching stability notification unit 631, a second access information register 625, a determination unit 6222, a prohibition unit 6223 and an IO control synchronous access parameter register 611. Is different. Explanation of the same points is omitted, and different points will be mainly described below.
　ＩＯ切替計数部６２３は、ＩＯ端子部６３の切り替え開始から一定時間を計測する計測手段としてのカウンタ６２３１と、セレクタとを有する。セレクタは、カウンタ６２３１のタイムアウト通知、切替安定通知部６３１からの切替完了通知の何れかを選択する。ここで、一定時間は、ＩＯ端子部６３の電気的特性の切替に要する時間である。 The IO switching counting unit 623 includes a counter 6231 as a measuring unit that measures a predetermined time from the start of switching of the IO terminal unit 63, and a selector. The selector selects either the timeout notification of the counter 6231 or the switching completion notification from the switching stability notification unit 631. Here, the fixed time is a time required for switching the electrical characteristics of the IO terminal unit 63.
　ＩＯ端子制御部６２は、ＩＯ切替計数部６２３から一定時間が経過したことの通知または切替完了通知を受けると、外部デバイス制御部６１に対してアクセス開始遅延指示を解除する。この解除により、外部デバイス制御部６１は、外部デバイスへのアクセスを開始する。 The IO terminal control unit 62 cancels the access start delay instruction to the external device control unit 61 when receiving a notification that a certain time has passed or a switching completion notification from the IO switching counting unit 623. With this cancellation, the external device control unit 61 starts access to the external device.
　切替安定通知部６３１は、ＩＯ端子部６３の電気的特性の切り替えが完了したことを通知する完了通知をＩＯ端子制御部６２に出力する。 The switching stability notification unit 631 outputs a completion notification notifying that the switching of the electrical characteristics of the IO terminal unit 63 has been completed to the IO terminal control unit 62.
　これにより、ＩＯ端子部６３の電気的特性の変更が確定するまでに時間を要する場合に、当該時間を確保することができる。 Thereby, when it takes time until the change of the electrical characteristics of the IO terminal unit 63 is confirmed, the time can be secured.
　第２アクセス情報レジスタ６２５は、前回のアクセス情報を保持つまり前回のアクセス先の外部デバイスを示す情報を保持するレジスタである。 The second access information register 625 is a register that holds the previous access information, that is, holds information indicating the external device of the previous access destination.
　判定部６２２２は、今回のアクセス先と前回のアクセス先とが一致するか否かを判定する。 The determination unit 6222 determines whether or not the current access destination matches the previous access destination.
　禁止部６２２３は、判定部６２２２により一致すると判定されたとき、ＩＯ端子部６３の電気的特性の設定を禁止する。その結果、ＩＯ制御情報生成部６２２は、判定部６２２２により一致すると判定された時点で外部デバイス制御部６１に対してアクセス開始遅延指示を解除し、ＩＯ端子部６３に対して電気的特性の設定を開始しない。 The prohibition unit 6223 prohibits the setting of the electrical characteristics of the IO terminal unit 63 when it is determined by the determination unit 6222 that they match. As a result, the IO control information generation unit 622 cancels the access start delay instruction to the external device control unit 61 when the determination unit 6222 determines that they match, and sets the electrical characteristics for the IO terminal unit 63. Do not start.
　これにより、今回のアクセス先と前回のアクセス先とが一致する場合に、ＩＯ端子部６３の電気的特性の設定を省略可能であり、ＩＯ端子部６３の電気的特性を設定するため生じるアクセス遅延を低減することができる。 Thereby, when the current access destination matches the previous access destination, the setting of the electrical characteristics of the IO terminal unit 63 can be omitted, and the access delay caused by setting the electrical characteristics of the IO terminal unit 63 Can be reduced.
　ＩＯ制御同期アクセスパラメータレジスタ６１１は、複数のアクセスパラメータを保持するパラメータ保持部である。外部デバイス制御部６１は、ＩＯ端子制御部６２のＩＯ端子部６３への電気的特性の設定に対応したアクセスパラメータをＩＯ制御同期アクセスパラメータレジスタ６１１から選択し、アクセスパラメータに従って外部デバイスへアクセスする。ここで、アクセスパラメータは、アクセス制御信号のアサートサイクルやアドレスサイクル等を示す。 The IO control synchronous access parameter register 611 is a parameter holding unit that holds a plurality of access parameters. The external device control unit 61 selects an access parameter corresponding to the setting of the electrical characteristics to the IO terminal unit 63 of the IO terminal control unit 62 from the IO control synchronous access parameter register 611, and accesses the external device according to the access parameter. Here, the access parameter indicates an access control signal assert cycle, an address cycle, or the like.
　外部デバイス制御部６１は、外部デバイスに対しＩＯ端子部６３の出力電流およびスルーレートの変更を行った場合にアクセス制御信号のアサートサイクルやアドレスサイクル等のアクセスパラメータをＩＯ端子制御部６２と同期して変更するときに参照するＩＯ制御同期アクセスパラメータレジスタ６１１を備える。 The external device control unit 61 synchronizes access parameters such as an access control signal assert cycle and an address cycle with the IO terminal control unit 62 when the output current and slew rate of the IO terminal unit 63 are changed for the external device. And an IO control synchronous access parameter register 611 that is referred to when the change is made.
　かかる構成によれば、ＩＯ端子部６３の出力電流およびスルーレートを変更した場合に外部デバイス制御部６１に対してアクセスパラメータをソフトウェアで再設定する必要がなくなる。仮に、ソフトウェアで再設定する場合には、ＩＯ端子への変更とアクセスパラメータの変更タイミングをソフトウェア制御で同期させる必要があり、切り替えに要するサイクルにより転送効率が低下する。 According to such a configuration, when the output current and the slew rate of the IO terminal unit 63 are changed, it is not necessary to reset the access parameters to the external device control unit 61 by software. If it is reset by software, it is necessary to synchronize the change to the IO terminal and the change timing of the access parameter by software control, and the transfer efficiency is lowered due to the cycle required for switching.
　なお、図示はしていないが、複数のマスタから同一の外部デバイスへのアクセスを行う場合に、バスコントローラ８がマスタの識別情報を外部バスインタフェース６に通知し、特定マスタであるときに、外部デバイス制御部６１は、アクセスパラメータの設定を変更し、ＩＯ端子制御部６２は、ＩＯ端子部６３の出力電流やスルーレートの設定を変更するといった制御を行ってもよい。 Although not shown, when a plurality of masters access the same external device, the bus controller 8 notifies the master bus identification information to the external bus interface 6, and when the master is a specific master, The device control unit 61 may change the setting of the access parameter, and the IO terminal control unit 62 may perform control such as changing the setting of the output current and the slew rate of the IO terminal unit 63.
　かかる構成によれば、ＣＰＵから外部デバイスへのアクセスのみＩＯ端子の出力電流およびスルーレートを大にしてレイテンシ性能を向上させ、以外のマスタからの場合には、データ転送より性能不要輻射および消費電力低減を優先させるといった制御を行うことができる。 According to such a configuration, only the access from the CPU to the external device increases the output current and the slew rate of the IO terminal to improve the latency performance, and in the case of from other masters, the unnecessary radiation and power consumption than the data transfer. Control that prioritizes reduction can be performed.
　なお、第２の変形例において、ＩＯ端子部６３の電気的特性の安定時間を計測する手段としてＩＯ端子制御部６２内のＩＯ切替計数部６２３にカウンタ６２３１を設け、さらに、ＩＯ端子部６３に同様の機能を有する切替安定通知部６３１を設けているが、どちらか一方でよい。 In the second modification, a counter 6231 is provided in the IO switching counter 623 in the IO terminal controller 62 as means for measuring the stabilization time of the electrical characteristics of the IO terminal 63, and the IO terminal 63 is further provided with a counter 6231. Although the switching stability notification unit 631 having the same function is provided, either one may be used.
　また、第２の変形例において、第２アクセス情報レジスタ６２５は、前回のアクセス要求に対応するアクセス情報を保持しているが、この代わりに、外部デバイス制御部６１より今回アクセスの次アクセスの情報を予め保持する構成としてもよい。これはＣＰＵ７からパイプラインアクセスが発生し、バスコントローラ８から外部バスインタフェース６に次アクセスが発生するシステムを想定している。 In the second modification, the second access information register 625 holds access information corresponding to the previous access request. Instead, the external device control unit 61 receives information on the next access of the current access. It is good also as a structure which hold | maintains beforehand. This assumes a system in which a pipeline access occurs from the CPU 7 and a next access occurs from the bus controller 8 to the external bus interface 6.
　かかる構成によれば、外部デバイス２の連続アクセスであっても、アクセス終了毎にＩＯ端子部６３の出力電流およびスルーレートを小に設定することがなく、さらなる高速なデータ転送を実現することができる。 According to such a configuration, even when the external device 2 is continuously accessed, the output current and the slew rate of the IO terminal unit 63 are not set small each time the access is completed, and higher-speed data transfer can be realized. it can.
　かかる構成によれば、ＬＳＩ１側のＩＯ端子からの出力電流およびスルーレートを要因とする不要輻射および消費電流の量のみならず、外部デバイス含めシステム全体で不要輻射および消費電流量を抑制することができる。 According to such a configuration, not only the amount of unnecessary radiation and current consumption caused by the output current from the IO terminal on the LSI 1 side and the slew rate, but also the amount of unnecessary radiation and current consumption in the entire system including the external device can be suppressed. it can.
　なお、第２アクセス情報レジスタ６２５がＩＯ端子部６３に設定されている現在の電気的特性を示す情報を保持し、判定部６２２２が新たなアクセス要求に対応する電気的特性と、前記レジスタに保持された情報が示す現在の電気的特性とが一致するか否かを判定し、禁止部が、判定部により一致すると判定されたとき、ＩＯ端子部６３の電気的特性の設定を禁止する構成としてもよい。 The second access information register 625 holds information indicating the current electrical characteristics set in the IO terminal unit 63, and the determination unit 6222 holds the electrical characteristics corresponding to a new access request and the register. It is determined whether or not the current electrical characteristics indicated by the received information match, and the setting of the electrical characteristics of the IO terminal unit 63 is prohibited when the prohibition unit determines that they match by the determination unit. Also good.
　なお、外部ＩＯ制御部９とＩＯ制御バス５のかわりに外部デバイス制御部６１にＩＯ制御コマンドＩＦ６１２を設け、第１外部バス４を経由し、アクセス間のコマンドを挿入する等の方法で外部デバイスにＩＯ端子の設定情報を通知してもよい。 The external device control unit 61 is provided with an IO control command IF 612 instead of the external IO control unit 9 and the IO control bus 5, and an external device is inserted by a method such as inserting a command between accesses via the first external bus 4. May be notified of IO terminal setting information.
　かかる構成によれば、ＩＯ制御バス５を不要とすることができる。 According to this configuration, the IO control bus 5 can be dispensed with.
　（実施の形態２）
　実施の形態２では、上記のような外部バスインタフェースを複数（第１外部インタフェースと第２外部インタフェース）と、第２外部バスインタフェースのＩＯ端子における現在の電気的特性の設定値を示す設定情報を保持する設定情報レジスタとを備え、前記第１外部バスインタフェースは、設定情報レジスタに保持された設定情報に応じて、第１外部バスインタフェースのＩＯ端子部における電気的特性を前記アクセス要求に同期して決定する。 (Embodiment 2)
In the second embodiment, a plurality of external bus interfaces as described above (first external interface and second external interface) and setting information indicating the current setting value of the electrical characteristics at the IO terminal of the second external bus interface are stored. The first external bus interface synchronizes the electrical characteristics of the IO terminal portion of the first external bus interface with the access request in accordance with the setting information held in the setting information register. To decide.
　これによれば、ＬＳＩ内の別の外部バスインタフェースの稼動状況に応じてＩＯ端子部の電気的特性を変更することができる。例えば、第１外部インタフェースおよび第２外部インタフェースの両方が同時に、電流駆動能力を大、スルーレートを高く設定した状態でアクセスするなどの、消費電力および不要輻射の観点で好ましくない状況を回避することを可能にする。 According to this, the electrical characteristics of the IO terminal unit can be changed according to the operation status of another external bus interface in the LSI. For example, avoiding a situation in which both the first external interface and the second external interface are unfavorable in terms of power consumption and unnecessary radiation, such as accessing with a large current drive capability and a high slew rate at the same time. Enable.
　図４は、本発明の実施の形態２のＬＳＩシステムの構成を示すブロック図である。図４のＬＳＩシステムは、ＬＳＩ１と、第１外部バス４に接続された外部デバイス２および外部デバイス１１と、第２外部バス１０に接続された外部デバイス１２および外部デバイス１３とを備える。ＬＳＩ１は、外部バスインタフェース６、外部バスインタフェース１５、ＣＰＵ７、バスコントローラ８、ＩＯ制御情報共有レジスタ１４、ＤＳＰ１６、メモリ制御部１７を備える。メモリ制御部１７は、メモリ４２に接続されている。 FIG. 4 is a block diagram showing a configuration of the LSI system according to the second embodiment of the present invention. The LSI system of FIG. 4 includes an LSI 1, an external device 2 and an external device 11 connected to the first external bus 4, and an external device 12 and an external device 13 connected to the second external bus 10. The LSI 1 includes an external bus interface 6, an external bus interface 15, a CPU 7, a bus controller 8, an IO control information sharing register 14, a DSP 16, and a memory control unit 17. The memory control unit 17 is connected to the memory 42.
　外部バスインタフェース６および１５は、実施の形態１で説明した外部バスインタフェースと同様の構成である。 External bus interfaces 6 and 15 have the same configuration as the external bus interface described in the first embodiment.
　図４において、図１と同じ構成要素については同じ符号を用い、説明を省略する。 4, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.
　図４において、ＬＳＩ１は、外部バスインタフェースを複数備えている。外部バスインタフェース６に加え、外部バスインタフェース１５は第２外部バス１０を介して外部デバイス１２および１３と接続されている。ＬＳＩ１内のＣＰＵ７およびデータ処理用のＤＳＰ１６は、メモリ４２をローカルメモリとして使用する。メモリ制御部１７は、バスコントローラ８を経由したＣＰＵ７からのメモリアクセス要求もしくはＤＳＰ１６からのメモリアクセス要求を調停する。ＩＯ制御情報共有レジスタ１４は外部バスインタフェースが接続した外部デバイスへのＩＯ制御情報を格納するレジスタで、外部バスインタフェース
は外部デバイスにアクセスする際のＩＯ端子の電気的特性の設定時に参照し、設定値を決定する。 In FIG. 4, the LSI 1 includes a plurality of external bus interfaces. In addition to the external bus interface 6, the external bus interface 15 is connected to the external devices 12 and 13 via the second external bus 10. The CPU 7 and the data processing DSP 16 in the LSI 1 use the memory 42 as a local memory. The memory control unit 17 arbitrates a memory access request from the CPU 7 or a memory access request from the DSP 16 via the bus controller 8. The IO control information sharing register 14 is a register for storing IO control information for an external device connected to the external bus interface. The external bus interface is referred to when setting the electrical characteristics of the IO terminal when accessing the external device. Determine the value.
　本実施の形態２において、システムの動作モードがブートローディングから通常モードに移行し、通常モードにおいて外部デバイス１２にＤＳＰ１６の処理前データが格納されている場合について説明する。ブートローディング中は、外部デバイス２に格納されたブートコードのデータ転送が主に行われる。外部デバイス２へのアクセス中は、ＩＯ端子の電気的特性として出力電流およびスルーレートを大に制御するとともに、ＩＯ制御情報共有レジスタ１４の外部バスインタフェース６の制御情報として出力電流およびスルーレートが大と出力する。同アクセス中に、外部バスインタフェース１５が外部デバイス１２へのアクセスを開始した場合に外部バスインタフェース１５はＩＯ制御情報共有レジスタ１４を参照し、外部バスインタフェース６がＩＯ端子への出力電流およびスルーレートを大で使用しているため、ＩＯ端子への出力電流およびスルーレートを小に設定する。次に通常モードに移行すると、外部デバイス２へのアクセス頻度が減少し、外部デバイス１２に格納された処理前データのデータ転送が主に行われる。外部デバイス１２へのアクセス中はＩＯ端子の電気的特性として出力電流およびスルーレートを大に制御するとともに、ＩＯ制御情報共有レジスタ１４の外部バスインタフェース１５の制御情報として出力電流およびスルーレートが大と出力する。同アクセス中に、外部バスインタフェース６が外部デバイス２へのアクセスを開始した場合に外部バスインタフェース６はＩＯ制御情報共有レジスタ１４を参照し、外部バスインタフェース１５がＩＯ端子への出力電流およびスルーレートを大で使用しているため、ＩＯ端子への出力電流およびスルーレートを小に設定する。尚、他にシステム動作モードとして通常モードと区別されるモードとしては、外部より再開指示があるまで再開に必要な機能以外を休止しておくスリープおよびスタンバイモードがある。これらのモードでは外部デバイスへのアクセスは少ない。この場合、ＩＯ端子への出力電流およびスルーレートを小に設定しておく。 In the second embodiment, a case will be described in which the operation mode of the system shifts from boot loading to the normal mode, and the pre-processing data of the DSP 16 is stored in the external device 12 in the normal mode. During boot loading, data transfer of the boot code stored in the external device 2 is mainly performed. While the external device 2 is being accessed, the output current and the slew rate are largely controlled as electrical characteristics of the IO terminal, and the output current and the slew rate are large as control information for the external bus interface 6 of the IO control information sharing register 14. Is output. When the external bus interface 15 starts accessing the external device 12 during the access, the external bus interface 15 refers to the IO control information sharing register 14 and the external bus interface 6 outputs the output current and slew rate to the IO terminal. Therefore, the output current to the IO terminal and the slew rate are set to be small. Next, when shifting to the normal mode, the access frequency to the external device 2 decreases, and data transfer of pre-processing data stored in the external device 12 is mainly performed. While accessing the external device 12, the output current and the slew rate are largely controlled as the electrical characteristics of the IO terminal, and the output current and the slew rate are large as the control information of the external bus interface 15 of the IO control information sharing register 14. Output. When the external bus interface 6 starts accessing the external device 2 during the access, the external bus interface 6 refers to the IO control information sharing register 14 and the external bus interface 15 outputs the output current and slew rate to the IO terminal. Therefore, the output current to the IO terminal and the slew rate are set to be small. Other modes that are distinguished from the normal mode as the system operation mode include a sleep mode and a standby mode in which functions other than those necessary for the restart are suspended until a restart instruction is given from the outside. In these modes, there is little access to external devices. In this case, the output current to the IO terminal and the slew rate are set small.
　かかる構成によれば、複数の外部バスインタフェースが、外部デバイスのアクセス毎にＩＯ端子の電気的特性を制御し、同時に出力電流やスルーレートを大に設定しないように調整を行うため、ＬＳＩとしての不要輻射や消費電力の低減を行うことができる。 According to such a configuration, the plurality of external bus interfaces controls the electrical characteristics of the IO terminal for each access of the external device, and at the same time performs adjustment so that the output current and the slew rate are not set large. Unwanted radiation and power consumption can be reduced.
　なお、本実施形態におけるＬＳＩシステムは、図４の構成に対して種々の変形が可能である。以下、変形例について説明する。 Note that the LSI system in this embodiment can be variously modified with respect to the configuration of FIG. Hereinafter, modified examples will be described.
　ＩＯ制御情報共有レジスタ１４に、外部バスインタフェースがＩＯ端子の電気的特性の設定頻度情報を合わせて設定してもよい。設定条件はＬＳＩ１単独の動作モードに従い設定してもよい。もしくは、図５に示すように、システムの動作状況に応じて、システム制御ＣＰＵ４３よりシステムレジスタ２０に設定した情報を基にＣＰＵ７が設定してもよい。ＩＯ制御情報として外部バスインタフェース６は設定頻度大と設定し、外部バスインタフェース１５は設定頻度小と設定する。例として、外部バスインタフェース６は、１０回のアクセスにおいて２回についてはＩＯ端子の電気的特性を出力電流およびスルーレートを大に、以外は小に設定し、外部バスインタフェース１５は、１０回のアクセスにおいて８回についてはＩＯ端子の電気的特性を出力電流およびスルーレートを大に、以外は小に設定する。外部バスインタフェース６と外部バスインタフェース１５のアクセスが同時に発生した場合には、他方の外部インタフェースのＩＯ端子の出力電流およびスルーレートは小に設定する。 In the IO control information sharing register 14, the external bus interface may set the setting frequency information of the electrical characteristics of the IO terminal together. The setting condition may be set according to the operation mode of the LSI 1 alone. Alternatively, as shown in FIG. 5, the CPU 7 may set the information based on the information set in the system register 20 by the system control CPU 43 according to the operation status of the system. As the IO control information, the external bus interface 6 is set to a high setting frequency, and the external bus interface 15 is set to a low setting frequency. As an example, the external bus interface 6 sets the electrical characteristics of the IO terminal to a large value except for the output current and the slew rate for two times in 10 accesses, and the external bus interface 15 is set to a small value for 10 times. For the eight accesses, the electrical characteristics of the IO terminal are set to a large value except for the output current and the slew rate. When the external bus interface 6 and the external bus interface 15 are simultaneously accessed, the output current and the slew rate of the IO terminal of the other external interface are set to be small.
　かかる構成によれば、外部インタフェース毎に外部バスインタフェースがＩＯ端子の電気的特性の設定頻度情報を合わせて設定することができ、外部デバイス毎の不要輻射や消費電力の低減調整を行うことができる。 According to such a configuration, the external bus interface can set together the setting frequency information of the electrical characteristics of the IO terminal for each external interface, and reduction adjustment of unnecessary radiation and power consumption for each external device can be performed. .
　図５は実施の形態２における第１の変形例におけるＬＳＩシステムの構成を示すブロック図である。システム制御ＣＰＵ４３は、各デバイスへのリセット制御、電源制御を行うとともに、ＬＳＩ１の外部通信インタフェース４１を介してＬＳＩ１の内部ＣＰＵ７と制御情報のやりとりを行うことにより、ＬＳＩ１を制御している。本システム構成において、ＬＳＩ１は、ＩＯトグル率算出部１８を備える構成としてもよい。すなわち、外部バスインタフェースが使用するＩＯ毎に、電気的特性の設定を切り替える割り合いであるトグル率を算出するＩＯトグル率算出部１８の情報を用い、外部バスインタフェース毎のＩＯ端子の電気的特性の設定頻度情報を合わせて設定してもよい。 FIG. 5 is a block diagram showing a configuration of an LSI system according to the first modification of the second embodiment. The system control CPU 43 controls the LSI 1 by performing reset control and power supply control for each device, and exchanging control information with the internal CPU 7 of the LSI 1 via the external communication interface 41 of the LSI 1. In this system configuration, the LSI 1 may be configured to include the IO toggle rate calculation unit 18. That is, for each IO used by the external bus interface, the information of the IO toggle rate calculation unit 18 that calculates the toggle rate that is a ratio of switching the setting of the electrical property is used, and the electrical property of the IO terminal for each external bus interface. The setting frequency information may be set together.
　かかる構成によれば実際のＩＯの使用状況を踏まえて外部インタフェース毎に外部バスインタフェースがＩＯ端子の電気的特性の設定頻度情報を合わせて設定することができる。 According to such a configuration, the external bus interface can set the setting frequency information of the electrical characteristics of the IO terminal for each external interface based on the actual usage status of the IO.
　また、システムボード上に電源モニタ４４を備え、システムボード上の供給電流の変動度を検出し、システム制御ＣＰＵ４３が電源状況レジスタ１９にシステムボード上の供給電流の変動度を通知し、変動度が大きい場合にＩＯ端子の出力電流およびスルーレートを小に設定するようＩＯ制御情報供給レジスタに設定し、外部バスインタフェースが、ＩＯ端子の出力電流およびスルーレートを小に設定するよう制御してもよい。 Also, a power supply monitor 44 is provided on the system board to detect the fluctuation level of the supply current on the system board, and the system control CPU 43 notifies the power supply status register 19 of the fluctuation degree of the supply current on the system board. If it is large, the IO control information supply register may be set to set the output current and slew rate of the IO terminal to be small, and the external bus interface may be controlled to set the output current and slew rate of the IO terminal to be small. .
　かかる構成によれば、システムボード上の電源変動による不要輻射や消費電流の変動を低く抑えるよう設定することができる。 According to such a configuration, it is possible to set so as to suppress unnecessary radiation and fluctuations in current consumption due to power fluctuations on the system board.
　なお、図示はしていないが、外部バスが同期バスクロック信号を伴っている場合、外部バスインタフェースが同期バスクロックの周波数を検出して、高い周波数の場合には、ＩＯ端子の電気的特性の出力電流およびスルーレートを大に設定するように制御してもよい。 Although not shown, when the external bus is accompanied by a synchronous bus clock signal, the external bus interface detects the frequency of the synchronous bus clock. The output current and the slew rate may be controlled to be set large.
　同期バスクロックはＬＳＩ１がバスマスタとして出力する場合や外部マスタとして入力する場合もある。外部マスタとのプロトコルとしてハンドシェイク信号を用いている場合には、ＩＯ端子の電気的特性の切り替え安定までを外部マスタへのハンドシェイク信号の出力を遅らせるようにしてもよい。 The synchronous bus clock may be input as a bus master by the LSI 1 or an external master. When a handshake signal is used as a protocol with the external master, the output of the handshake signal to the external master may be delayed until the electrical characteristics of the IO terminal are switched stably.
　かかる構成によれば、外部バスの電気的仕様を同期バスクロックの周波数に対して規定し、ＩＯ端子の電気的特性の出力電流およびスルーレートを規定を越えない範囲で小さく設定することにより不要輻射や消費電流を低減することができる。 According to this configuration, the electrical specifications of the external bus are specified with respect to the frequency of the synchronous bus clock, and the unnecessary radiation is set by setting the output current and the slew rate of the electrical characteristics of the IO terminal to be small within a range not exceeding the specification. And current consumption can be reduced.
　本発明の１側面にかかる外部バスインタフェースは、動作モードにおいて要求される転送レートが異なる外部デバイスか、もしくは要求される転送レートの異なる複数の外部デバイスが共有バスを経由して接続されるシステムにおいて、動作モードもしくは外部デバイス毎に接続ＩＯの電気的特性を切り替える制御部を有するため、不要輻射や消費電力の低減が要求されるシステムＬＳＩ等に適用するのに有用である。 An external bus interface according to one aspect of the present invention is an external device having different transfer rates required in an operation mode, or a system in which a plurality of external devices having different required transfer rates are connected via a shared bus. Since it has a control unit that switches the electrical characteristics of the connection IO for each operation mode or external device, it is useful for application to a system LSI or the like that is required to reduce unnecessary radiation or power consumption.
　１　ＬＳＩ
　２　外部デバイス
　４　第１外部バス
　５　ＩＯ制御バス
　６、１５　外部バスインタフェース
　７　ＣＰＵ
　８　バスコントローラ
　９　外部ＩＯ制御部
　１４　ＩＯ制御情報共有レジスタ
　１６　ＤＳＰ
　１７　メモリ制御部
　１８　ＩＯトグル率算出部
　１９　電源状況レジスタ
　２１、２２、３１、３２、６３　ＩＯ端子部
　２３、３３　ＩＯ端子制御部
　２４、３４　外部ＩＯ制御部
　４３　システム制御ＣＰＵ
　４４　電源モニタ
　６１　外部デバイス制御部
　６２　ＩＯ端子制御部
　９１　外部ＩＯ制御レジスタ
　９２　ＩＯ切替計数部
　９３　ＩＯ端子部
　６１１　ＩＯ制御同期アクセスパラメータレジスタ
　６１２　ＩＯ制御コマンドインタフェース
　６２１　アクセス開始遅延制御部
　６２２　ＩＯ制御情報生成部
　６２３　ＩＯ切替計数部
　６２４　第１アクセス情報レジスタ
　６２５　第２アクセス情報レジスタ
　６３１　切替安定通知部
　６３２　レシーバ
　６３３、６３４　ドライバ
　６３５　スルー調整部 1 LSI
2 External device 4 First external bus 5 IO control bus 6, 15 External bus interface 7 CPU
8 Bus controller 9 External IO control unit 14 IO control information sharing register 16 DSP
17 Memory control unit 18 IO toggle rate calculation unit 19 Power supply status register 21, 22, 31, 32, 63 IO terminal unit 23, 33 IO terminal control unit 24, 34 External IO control unit 43 System control CPU
44 Power Supply Monitor 61 External Device Control Unit 62 IO Terminal Control Unit 91 External IO Control Register 92 IO Switching Count Unit 93 IO Terminal Unit 611 IO Control Synchronous Access Parameter Register 612 IO Control Command Interface 621 Access Start Delay Control Unit 622 IO Control Information Generation Unit 623 IO switching counting unit 624 first access information register 625 second access information register 631 switching stability notification unit 632 receiver 633, 634 driver 635 thru adjustment unit

Claims (13)

  1. 　アクセス要求に従って外部バスを介して複数の外部デバイスにアクセスするＬＳＩに備えられる外部バスインタフェースであって、
    　電流駆動能力および出力電圧のスルーレートの少なくとも一方である電気的特性を設定により切り替え可能であり前記外部バスに信号を入出力するＩＯ端子と、
    　前記アクセス要求に同期して前記ＩＯ端子の電気的特性の設定を行うＩＯ端子制御部とを備える外部バスインタフェース。     An external bus interface provided in an LSI that accesses a plurality of external devices via an external bus according to an access request,
    An IO terminal capable of switching an electrical characteristic which is at least one of a current driving capability and an output voltage slew rate by setting and inputting / outputting a signal to / from the external bus;
    An external bus interface comprising: an IO terminal control unit configured to set electrical characteristics of the IO terminal in synchronization with the access request.
  2. 　前記ＩＯ端子制御部は、予めＣＰＵによって書き込まれた複数の制御パターンを保持する制御パターン保持部を有し、
    　前記複数の制御パターンは、前記複数の外部デバイスのそれぞれに対応する電流駆動能力および出力電圧のスルーレートの少なくとも一方を示し、
    　前記ＩＯ端子制御部は、前記アクセス要求を受けたとき、アクセス先の外部デバイスに対応する制御パターンを選択し、当該制御パターンに従って前記電気的特性の設定を行う
    請求項１に記載の外部バスインタフェース。     The IO terminal control unit has a control pattern holding unit that holds a plurality of control patterns written in advance by the CPU,
    The plurality of control patterns indicate at least one of a current driving capability and an output voltage slew rate corresponding to each of the plurality of external devices,
    2. The external bus interface according to claim 1, wherein when receiving the access request, the IO terminal control unit selects a control pattern corresponding to an external device to be accessed, and sets the electrical characteristics according to the control pattern. .
  3. 　前記外部バスインタフェースは、前記アクセス要求に従って外部デバイスへのアクセスを制御する外部デバイス制御部を備え、
    　前記外部デバイス制御部は、複数のアクセスパラメータを保持するパラメータ保持部を有し、前記ＩＯ端子制御部の前記ＩＯ端子への電気的特性の設定に対応した前記アクセスパラメータを選択し、前記外部デバイスへアクセスする
    請求項１に記載の外部バスインタフェース。     The external bus interface includes an external device control unit that controls access to an external device according to the access request,
    The external device control unit includes a parameter holding unit that holds a plurality of access parameters, selects the access parameter corresponding to the setting of electrical characteristics of the IO terminal control unit to the IO terminal, and the external device The external bus interface according to claim 1, wherein the external bus interface is accessed.
  4. 　前記ＩＯ端子制御部は、さらに、
    　切り替え開始から一定時間を計測する計測手段を備え、
    　前記外部デバイス制御部は、前記一定時間の経過後に、前記外部デバイスへのアクセスを開始する
    請求項１に記載の外部バスインタフェース。     The IO terminal control unit further includes:
    With measuring means to measure a certain time from the start of switching,
    The external bus interface according to claim 1, wherein the external device control unit starts access to the external device after the predetermined time has elapsed.
  5. 　前記ＩＯ端子制御部は、さらに、
    　前回のアクセス先の外部デバイスを示す情報を保持するレジスタと、
    　今回のアクセス先と前回のアクセス先とが一致するか否かを判定する判定部と、
    　前記判定部により一致すると判定されたとき、前記ＩＯ端子部の電気的特性の設定を禁止する禁止部とを備える
    請求項１に記載の外部バスインタフェース。     The IO terminal control unit further includes:
    A register holding information indicating the external device of the previous access destination;
    A determination unit that determines whether or not the current access destination and the previous access destination match,
    2. The external bus interface according to claim 1, further comprising: a prohibiting unit that prohibits setting of an electrical characteristic of the IO terminal unit when it is determined by the determining unit that they match.
  6. 　前記ＩＯ端子制御部は、さらに、
    　前記ＩＯ端子部に設定されている現在の電気的特性を示す情報を保持するレジスタと、
    　新たなアクセス要求に対応する電気的特性と、前記レジスタに保持された情報が示す現在の電気的特性とが一致するか否かを判定する判定部と、
    　前記判定部により一致すると判定されたとき、前記ＩＯ端子部の電気的特性の設定を禁止する禁止部とを備える
    請求項１に記載の外部バスインタフェース。     The IO terminal control unit further includes:
    A register holding information indicating current electrical characteristics set in the IO terminal unit;
    A determination unit that determines whether or not an electrical characteristic corresponding to a new access request matches a current electrical characteristic indicated by the information held in the register;
    The external bus interface according to claim 1, further comprising: a prohibiting unit that prohibits setting of the electrical characteristics of the IO terminal unit when it is determined by the determination unit that they match.
  7. 　前記外部インタフェースは、さらに、
    　前記アクセス要求に同期して、前記外部デバイスに対して、外部デバイスのＩＯ端子の電気的特性の設定を指示する外部ＩＯ指示部を備える
    請求項１に記載の外部バスインタフェース。     The external interface further includes:
    The external bus interface according to claim 1, further comprising an external IO instruction unit that instructs the external device to set an electrical characteristic of an IO terminal of the external device in synchronization with the access request.
  8. 　ＬＳＩであって、
    　請求項１に記載の外部バスインタフェースと同じ構成であり、アクセス要求に従って第１外部バスを介して複数の外部デバイスにアクセスする第１バスインタフェースと、
    　請求項１に記載の外部バスインタフェースと同じ構成であり、アクセス要求に従って第２外部バスを介して他の複数の外部デバイスにアクセスする第２バスインタフェースと、
    　第２外部バスインタフェースのＩＯ端子における現在の電気的特性の設定値を示す設定情報を保持する設定情報レジスタと
    　を備え、
    　前記第１外部バスインタフェースは、前記設定情報レジスタに保持された設定情報に応じて、第１外部バスインタフェースのＩＯ端子における電気的特性を前記アクセス要求に同期して決定する
    ＬＳＩ。     LSI,
    A first bus interface that has the same configuration as the external bus interface according to claim 1 and accesses a plurality of external devices via the first external bus according to an access request;
    A second bus interface having the same configuration as the external bus interface according to claim 1, wherein the second bus interface accesses a plurality of other external devices via the second external bus according to an access request;
    A setting information register for holding setting information indicating a setting value of the current electrical characteristic at the IO terminal of the second external bus interface;
    The LSI, wherein the first external bus interface determines an electrical characteristic at an IO terminal of the first external bus interface in synchronization with the access request in accordance with setting information held in the setting information register.
  9. 　前記ＬＳＩは、さらに、
    　前記ＬＳＩ内部又は前記ＬＳＩ外部のマスタから書き込み可能であり、外部デバイスに対応する電流駆動能力および出力電圧のスルーレートの少なくとも一方を示す制御パターンを保持するレジスタを有し、
    　前記第１および第２外部バスインタフェースの少なくとも一方は、前記レジスタに保持された制御パターンに従って、ＩＯ端子に設定すべき電気的特性を決定する
    請求項８に記載のＬＳＩ。     The LSI further comprises:
    Writable from a master inside the LSI or outside the LSI, and having a register that holds a control pattern indicating at least one of current drive capability and output voltage slew rate corresponding to an external device,
    9. The LSI according to claim 8, wherein at least one of the first and second external bus interfaces determines an electrical characteristic to be set for the IO terminal according to a control pattern held in the register.
  10. 　前記ＬＳＩは、さらに、
    　ＬＳＩ内部もしくはＬＳＩ外部のマスタから書き込み可能であり、外部デバイスへのアクセス方法を規定するアクセスパラメータを保持するレジスタを有し、
    　前記第１および第２外部バスインタフェースの少なくとも一方は、前記レジスタに保持されたアクセスパラメータに従って外部デバイスにアクセスする
    請求項８に記載のＬＳＩ。     The LSI further comprises:
    Writable from a master inside or outside the LSI, and having a register that holds an access parameter that defines an access method to an external device,
    9. The LSI according to claim 8, wherein at least one of the first and second external bus interfaces accesses an external device in accordance with an access parameter held in the register.
  11. 　請求項９に記載のＬＳＩと、
    　前記ＬＳＩ内部もしくはＬＳＩ外部のマスタと
    　を備え、
    　前記マスタは、第１の動作モードでは出力電流もしくはスルーレートを第１の値にするための制御パターンを前記レジスタに設定し、第１の動作モードよりもデータ転送レートが低い第２の動作モードでは出力電流もしくはスルーレートが第１の値よりも小さい第２の値にするための制御パターンを前記レジスタに設定する
    システム。     An LSI according to claim 9;
    Including a master inside or outside the LSI,
    In the first operation mode, the master sets a control pattern for setting the output current or the slew rate to the first value in the register, and the data transfer rate is lower than that in the first operation mode. Then, a system in which a control pattern for setting the output current or slew rate to a second value smaller than the first value is set in the register.
  12. 　請求項９に記載のＬＳＩと、
    　前記ＬＳＩ内部もしくはＬＳＩ外部のマスタと
    　を備え、
    　前記マスタは、第１の動作モードでは出力電流もしくはスルーレートを第１の値にするための制御パターンを前記レジスタに設定し、第１の動作モードよりも省電力で動作する第２の動作モードでは出力電流もしくはスルーレートが第１の値よりも小さい第２の値にするための制御パターンを前記レジスタに設定する
    システム。     An LSI according to claim 9;
    Including a master inside or outside the LSI,
    In the first operation mode, the master sets a control pattern for setting the output current or the slew rate to the first value in the register, and operates in a second operation mode in which the power consumption is lower than that in the first operation mode. Then, a system in which a control pattern for setting the output current or the slew rate to a second value smaller than the first value is set in the register.
  13. 　請求項９に記載のＬＳＩと、
    　前記ＬＳＩ内部もしくはＬＳＩ外部のマスタと
    　を備え、
    　前記マスタは、第１の動作モードでは出力電流もしくはスルーレートを第１の値にする
    ための制御パターンを前記レジスタに設定し、第１の動作モードよりも外部バスの転送クロック周波数が低い第２の動作モードでは出力電流もしくはスルーレートが第１の値よりも小さい第２の値にするための制御パターンを前記レジスタに設定する
    システム。     An LSI according to claim 9;
    Including a master inside or outside the LSI,
    In the first operation mode, the master sets a control pattern for setting the output current or the slew rate to the first value in the register, and the transfer clock frequency of the external bus is lower than that in the first operation mode. In this operation mode, the control pattern for setting the output current or the slew rate to a second value smaller than the first value is set in the register.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109508315A (en) * 2017-09-15 2019-03-22 株式会社东芝 The fault detection method of system LSI and system LSI

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08129439A (en) * 1994-10-31 1996-05-21 Nec Corp Bus driver
JPH10307790A (en) * 1997-05-06 1998-11-17 Shinsedai Kk High-speed processor
JP2003337640A (en) * 2002-05-21 2003-11-28 Mitsubishi Electric Corp Bus control apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08129439A (en) * 1994-10-31 1996-05-21 Nec Corp Bus driver
JPH10307790A (en) * 1997-05-06 1998-11-17 Shinsedai Kk High-speed processor
JP2003337640A (en) * 2002-05-21 2003-11-28 Mitsubishi Electric Corp Bus control apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109508315A (en) * 2017-09-15 2019-03-22 株式会社东芝 The fault detection method of system LSI and system LSI

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