JP3327900B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data processing device for efficiently processing a plurality of data transfer requests.

[0002]

2. Description of the Related Art In recent years, various types of multimedia-related products such as DVD playback devices and digital satellite broadcast receiving devices have appeared on the consumer electronics market, and competition between manufacturers developing them has been intensifying. . Against this background, designers engaged in signal processing application fields are making various efforts to develop general-purpose signal processors that efficiently perform parallel processing of a plurality of media processes. The difficulty in parallelizing multi-media processing is that in the development of such products, in addition to MPEG streams in which video and audio data are multiplexed, data such as computer graphics is also used. This is because whether the products are processed simultaneously efficiently greatly affects the market value of these products. Here, there are various types of media processing such as video decoding processing, audio decoding processing, video output processing, computer graphics drawing processing, and the like.

[0003] Such media processing is characterized by the fact that there are very many opportunities to execute a plurality of independent DMA transfers at the same time statistically as compared with other data processing, and the type of processing of each DMA transfer. The characteristic that the bandwidth is different depending on the type is noticeable. Here, DMA (Direct Memory Acce
ss) means that data is transferred between a plurality of master devices and a memory without the intervention of a central processing unit (CPU).

In one example of the above-mentioned media processing, each master device performs video decoding processing, audio decoding processing,
An application program for implementing any of video output processing, computer graphics drawing processing, and the like, and hardware for operating this program. In an example of media processing, the memory is used by these application programs. It stores video data, audio data, and computer graphics data.

The bandwidth of the DMA transfer is a unit expressed by a product between the bit width of each master device and the read / write port of the memory and the operating frequency of the master device and the memory. As an example of an approximate value, the application program of the video decoding process needs to perform the DMA transfer of the reference image at the time of motion compensation.
Requires a bandwidth on the order of te / s. An application program for audio data and computer / graphics data requires a bandwidth of the order of 50 Mbyte / s, and an application program for video output processing is called “128 Mbyte / s × number of planes”. Request bandwidth on order. The reason why the required number of bandwidths differs in each media processing is that the data size to be processed and the lightness and weight of the data decoding load are different in each media processing.

Hereinafter, a description will be given of a comparison between a DMA transfer system that performs general DMA transfer and a DMA transfer system that has been improved specifically for media processing. The former system configuration diagram is shown in FIG. 29, and the latter system configuration diagram is shown in FIG. 29, the data processing device includes a memory 51, a memory controller 52, an arbiter 53, a bus 54, and master devices 45, 46, and 47.

[0007] The master devices 45, 46, 47 operate application programs for media processing. When each application program requests a DMA transfer, it issues a bus request to the memory controller 52. When the bus request is issued, the arbiter 53 sends the master device 45 and the master device 4
6. Arbitration between the master devices 47 is performed, and as a result of the arbitration,
The use right is assigned to any one of the master device 45, the master device 46, and the master device 47. If the right to use the bus cannot be obtained, it waits for the start of data transfer, and after the right to use is given, starts data transfer.

As described above, it is necessary to allocate an optimum bandwidth to each application program for media processing. In such a bandwidth allocation technique, a bit width obtained by dividing a bus into a plurality of buses is used as a master. There is a method of assigning each of the devices 45 to the master device 47. For example, when the bit width of the read / write port and bus of the memory 51 is 128 bits,
It is divided into 64 bits-32 bits-32 bits, and these are divided into master devices 45 on which each application program operates.
To the master device 47. FIG. 30 is a diagram illustrating an example of a bandwidth allocation technique realized by bit width division. In FIG. 30, 12
The 8-bit bus is divided into 64 bits, 32 bits, and 32 bits, and the bit widths obtained by the division are divided into master devices 45 to 45.
Assigned to the master device 47.

At this time, the read / write port in the memory 51 is divided according to the division width of the bus, and the memory controller performs access control inside the memory in parallel. That is, 64-bit, 32-bit, and 32-bit data are read from the memory in parallel, and 64-bit, 32-bit, and 32-bit data are written in the memory in parallel. In order to parallelize such access control, a control circuit (“64bi” in the figure) for simultaneously accessing 64 bits, 32 bits, and 32 bits data
t access controll, 32bit access controll, 32bi
t access controll) must be provided in the memory controller, but in this method of dividing the bit width, the division of the bus does not cause contention between the master device 45 and the master device 47, and the bus lock of the memory bus does not occur. Does not occur.

Here, it is assumed that the master device 45 performs a video decoding process, and allocates a bit width of 64 bits. The reason why the higher bit width is assigned to the master device 45 is that the video decoding process requires a higher bandwidth than other media processes. In other words, in the media processing, the bandwidths enough to maintain the real-time property are different from each other,
In this method of dividing the bit width, the division ratio of the bit width must be determined according to the bandwidth required by each application program.

Finally, a memory device to be used in the data processing device will be described. The above-mentioned signal processing application fields require memory devices having a larger capacity and a higher bandwidth, and various technical innovations have been made in semiconductor processes and packaging technologies in order to meet such demands. As a result, high-performance memory devices are appearing in the electronic component market one after another, and model changes are being made very frequently. Here, examples of the memory device include SDRAM and RAMBUS specification memory. Sync
The hronus Dynamic Random Access Memory (SDRAM) is a memory that realizes burst transfer of data and has improved transfer capability as compared with DRAM. The RAMBUS specification memory is a memory in which the specification of the interface with the bus is strictly specified including the mounting method, and it is possible to obtain a higher bandwidth than SDRAM.
There is something called M. In addition, it has become possible to perform a semiconductor process so that a data processing device and a relatively large-capacity DRAM are mounted on the same semiconductor chip (generally referred to as on-chip).

If a large number of memory devices have appeared and model changes are frequent, the designer will be confused by how to design the memory architecture. The major factors in making such a determination are the bandwidth and the manufacturing cost, but it is also necessary to design the data processing device in consideration of its future potential. The design of a memory architecture in consideration of the future is to generalize the memory architecture so that memory devices having various hardware specifications can be adopted.

[0013]

The first method of dividing the bit width and allocating the optimum bandwidth is to increase the bit width allocated to each of the master device 45 to the master device 47. In order to reduce or reduce the bit width, there is a first problem that such a change in the allocation of the bit width spreads to a change in the design of the entire device.

The change of the bandwidth allocation is necessary when a data processing device provided in a certain device is diverted to another device. Such diversion is often found when developing a plurality of products having a common function of decoding an MPEG stream in parallel. Here, diversion of the data processing device will be described assuming the following situation. The data processing device shown in FIG. 30 is an MPEG stream decoding device, and it is assumed that the MPEG stream decoding device has been developed on the premise that it is mounted on a playback device of an optical disk until then. This device was originally intended to be mounted on a disc playback device, but due to the product development strategy of the manufacturer, this decoding device may be diverted to other devices such as a receiver for digital satellite broadcasting. Shall be ordered. When the diversion of the decoding device is ordered for the above reasons, the designer of the device has to take measures such as allocating the bit width allocated to the media processing specific to the reproducing apparatus to the media processing specific to the receiving apparatus.
In order to deal with this, in the conventional data processing device, rewiring of the bus (1), redesign of the read / write port of the memory device (2), and redesign of the read / write port of the master device 45 to the master device 47 are performed. It is necessary to consider (3) and redesign of the memory controller (4).

For example, in the example shown in FIG. 30, the memory controller reads out 64-bit, 32-bit, and 32-bit data in parallel from the memory, and reads the 64-bit, 32-bit, and 32-bi data.
Control is performed such that the data of t is written in the memory in parallel.
If you try to change the bit width allocation to 64 bits, 24 bits, or 8 bits, the memory controller
Since it is necessary to read out t, 24 bit, and 8 bit data from the memory in parallel, and to write 64 bit, 24 bit, and 8 bit data in the memory in parallel, the control of the memory controller shown in FIG. Need to be redesigned. In addition, the master device 46 to
Since the bit width of the interface of the master device 47 changes, these must be replaced with another one, and the wiring connection between the interfaces of the master device 46 to the master device 47 and the bus must be newly performed.

The rewiring and redesign of (1) to (4) impose a heavy burden on the designer, and the designer has to assign different bandwidths to each media processing. Equal effort must be paid in redesigning the device. Also, as explained second,
It is desirable to design the memory architecture of the data processing device so that various memory devices can be adopted, but generally the memory devices to be connected have operating frequencies that can exhibit their maximum performance. The operating frequency of the data processing device is set to a value that can exhibit such maximum performance, so when replacing a memory device with another one, the value that can exhibit the maximum performance of the new memory device However, there is a problem that the operating frequency of the data processing device must be reset. In other words, if one of a plurality of memory devices is adopted from the viewpoint of the manufacturing cost of the data processing device, the capacity of the memory, etc. Since the operating frequency of the data processing device must be changed every time, there is a problem that a heavy load is imposed on the designer.

In addition, when a memory is formed on a semiconductor chip on which a data processing device is mounted, one of the on-chip memory and the memory device cannot provide the maximum performance. There is a problem. When the memory controller 52-the master device 45 to the master device 47 and the memory 51 are mounted on the same chip, they need to be operated at the same operating frequency. In this case, it is quite possible that the operating frequency at which the maximum performance of the memory device is exhibited is different from the operating frequency at which the maximum performance of the on-chip memory is exhibited. In this case, if the data processing device is operated at an operating frequency at which the maximum performance of one of the two sides is exhibited, the other side cannot exhibit the maximum performance. Further, in video-related media processing, it is desirable to set the operating frequency of the data processing device based on the operating frequency of the display device, but in this way, the operating frequency of the data processing device is set based on the operating frequency of the display device. In this case, the maximum performance of the memory device cannot be exhibited.

In order to achieve the first object, an object of the present invention is to provide a data processing apparatus having high versatility so as to cope with a change in bandwidth allocation for each media processing in the future. An object of the present invention to achieve the second object is to provide a highly versatile data processing apparatus that can deal with future replacement of memory devices and on-chip memory.

The first and second objects are to provide a plurality of master data.
Device and one memory device
Transfer data between the device and each master device.
Data processing device that has two points.
Connected to a memory device at one point
Memory buses, each with two or more points
Have at least one of each master
Multiple local buses connected to devices and memory
Data read from device and memory device
Write data to each local bus
Is the data at the transfer rate required by each master device.
Transfer, and a memory device is required on the memory bus.
Transfer controller that performs data transfer at the transfer rate required.
Roller and the other point of the memory bus and each row
Multiple buffs connected at one point in Calvas
And a transfer level between the memory bus and the local bus.
Multiple data input / output to absorb differences
Local buffer means, each local buffer
All means have the same configuration, and local
Bus can be connected, and the memory device
Synchronous clock with an operating frequency different from the operating frequency of the
Signal is supplied and the data processing device is updated.
One port is connected to the memory device via a memory bus.
Connected to the read / write port of the
Connected to the plurality of local buffer means,
Operating frequency in re-device and inside data processing device
Memory bus to absorb the difference from the operating frequency
Input / output of data between the server and multiple local buffer means
Features a dual-port memory device that performs
This is achieved by a data processing device.

The second object is that one port is connected to the read / write port of the memory device and the other port is connected to the plurality of local buffer means, and the operating frequency and data processing in the memory device The present invention is achieved by a data processing apparatus including a dual-port memory device for inputting and outputting data between a memory bus and a plurality of local buffer means so as to absorb a difference in operating frequency inside the apparatus.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a data processing apparatus will be described below with reference to the drawings. Note that if the functions of the data processing apparatus are described together, the description may be significantly complicated. Therefore, the functions of the data processing apparatus will be described step by step in a plurality of embodiments.

(First Embodiment) The first embodiment relates to a data processing apparatus configured so that the allocation of bandwidth to a plurality of master devices can be changed with little effort. FIG. 1 shows a data processing device. As shown in FIG. 1, the data processing device is a one-chip LSI, and is used by being assembled into a multimedia-related product together with the external memory device 2. FIG. 2 shows a data processing apparatus configured with the gist of "simple bit width allocation change work". The configuration diagram of FIG. 2 illustrates only the components necessary for the above-described gist among the components of the data processing device, and the illustration of the components that are not related to such a gist is omitted. In FIG. 2, a frame indicated by a one-dot chain line indicates a part that is made into one chip as a data processing device. 2, the data processing device includes a memory controller 3, a master device 4, a master device 5, a master device 6, a local memory 7, a local memory 8, a local memory 9, a bus 10, and a bus 11 , A local buffer 13, a local buffer 14, a local buffer 15, an arbiter 16, a local controller 17, a local controller 18, a local controller 19, and connection circuits 20, 21, and 22. , A 128-bit bus 1 and an external memory device 2.

In this embodiment and the following embodiments, the transfer rate (bandwidth) required by each master device is as follows:
It depends on the bit width of the bus and the frequency of use required by each master device. That is, when there are two buses having the same bit width, the master device requests data transfer with high frequency on one bus, and the master device requests data transfer with low frequency on the other bus.
This means that “the transfer rate requested by the former master device is higher than the transfer rate requested by the latter master device”. The transfer frequency required by each master device is expressed only by the bit width of the read / write port without considering the frequency of use.)

In performing media processing, there is an optimum value for the bit width of each read / write port.
Since the description may be complicated if these are concretely illustrated, the bit width and the bandwidth of the bus 1, the bus 10, the bus 11, and the bus 12 are set to 128 bits and 64 bits.
The description will be made assuming that t, 32 bits, and 32 bits are used. The local buffer 13, the local controller 17, the connection circuit 2
Since 0 is a peripheral circuit associated with the master device 4, these are collectively referred to as “peripheral circuits of the master device 4” in the following description. Similarly, the local buffer 14,
The local controller 18 and the connection circuit 21 are collectively called “peripheral circuits of the master device 5”
5, the local controller 19 and the connection circuit 22 are collectively referred to as "peripheral circuits of the master device 6".

The 128-bit bus 1 is connected to the external memory device 2
And data transfer between the local buffer 13-the local buffer 14-the local buffer 15. In the present embodiment, the bit width of the read / write port of the external memory device 2 is 128 bits, and the bit width of the read / write port on one side of the local buffers 13 to 15 is 128 bits.
It is performed at an 8-bit transfer rate.

FIG. 3 is a timing chart showing the relationship between the bus 1 and the input / output of the external memory device 2. Bus 1
Is shown in the third row of FIG.
Data (Ptr. 4) in the figure indicates that the master device 4 has requested to read from or write to the memory.
Data (Ptr. 5) and Data (Ptr. 6) are 128-bit data requested by the master device 5 and the master device 6 to read from or write to the memory, respectively.
Data.

Referring to this figure, the cycles c1, c3, c5, c7, c9
Data (Ptr.4) is transferred in the cycle c2, c6, c10, Data (Ptr.5) in cycle c4, c8, Data (Ptr.4).
It can be seen that 6) has been transferred. This is Data (Ptr.
4) is transferred once every two cycles, and Data (Pt
r.5) and Data (Ptr.6) indicate that data is transferred once every four cycles. As shown in the figure, the bus 1 transfers data for the master device 4 to the master device 6 in a time-division manner.

The external memory device 2 has a work area to be used by the master device 4, the master device 5, and the master device 6 and a 128-bit read / write port. When the data length to be read is specified,
The data is output to the bus 1. On the other hand, when a write command and a write destination address are specified from the memory controller 3, the data output to the bus 1 is written to the write destination address.

The memory controller 3 controls data reading from the external memory device 2 and data writing to the external memory device 2. The data read control by the memory controller 3 issues a read destination address, a read command, and a data length to be read to the external memory device 2 and transmits data stored together with the read destination address and thereafter to the external memory device. This is performed by reading data from the device 2 to the bus 1.
In the write control, a write destination address, a write command, and a data length to be written are issued to the external memory device 2, and the data transferred to the bus 1 is written in the external memory device 2. This is performed by writing data after the destination address. Memory controller 3
Are performed in accordance with read requests / write requests from master devices 4 to 6. Therefore, the memory controller 3 has a plurality of pointers and an incrementer. Each of the plurality of pointers is a master device 4,
The master device 5 and the master device 6 are associated with each other and store read destination / write destination addresses issued from the master devices 4 to 5. When the incrementer issues a read command and a write command for any one of the master devices 4 to 6, the incrementer increments the address stored in the pointer corresponding to the master device.

Next, the timing at which the read request / write request for the master device 4 to the master device 6 is issued to the external memory device 2 will be described with reference to the timing chart of FIG. The first tier in this figure shows the address output to the external memory device 2, and the second tier shows the data output from the external memory device 2. Referring to these, Data (Ptr. 4) must be transferred once every two cycles, and Data (Ptr. 5), Data (Ptr.
tr.6) must be transferred once every four cycles, so the memory controller 3 uses the cycle c0, c2, c4, c6, c8, c
At 10, the read destination address and the read command for the address Ptr. 4 are output to the external memory device 2, and the read destination address and the read command for the address Ptr. 5 are output at cycles c 1, c 5, and c 9. I have. In cycles c3 and c7, a read destination address and a read command for address Ptr.6 are output.

The master device 4 has a local memory 7
And a 64-bit read / write port, and issues an access command requesting data read / write to the memory controller 3. When a data read is requested, an access command indicating a request to read data stored in the external memory device 2 is issued to the memory controller 3, and the external memory device 2-bus 1-local buffer 13-bus 10 And wait for the data to be transferred. When the data is transferred, the data is sequentially fetched and stored in the local memory 7.

When requesting data writing, an access command indicating that data writing is requested to the external memory device 2 is issued to the memory controller 3, and data to be written to the external memory device 2 is transferred from the local memory 7 to the bus 10. Output sequentially. The output data is
The data is sequentially written to the external memory device 2 via the bus 10, the local buffer 13, and the bus 1.

The master device 5 has a local memory 8
And a 32-bit read / write port, and requests the memory controller 3 to read / write data like the master device 4. The difference from the master device 4 is a data transfer path when reading / writing data. That is, while the master device 4 reads / writes data on the path of the external memory device 2-bus 1-local buffer 13-bus 10, the master device 5 receives the external memory device 2-bus 1-local buffer Data read / write is performed through the path of 14-bus 11.

The master device 6 has a local memory 9
And a 32-bit read / write port, and requests the memory controller 3 to read / write data like the master device 4. The difference from the master device 4 is a data transfer path when reading / writing data. That is, the master device 4 reads / writes the route data of the external memory device 2-bus 1-local buffer 13-bus 10 while the master device 6 reads / writes the external memory device 2-bus 1-local buffer 15 Reading of path data of the bus 12 /
Write.

The bus 10 is a bus connected to the read / write port of the master device 4 and the other side read / write port of the local buffer 13. The bus 11 is a bus connected to the read / write port of the master device 5 and the other side read / write port of the local buffer 14. Bus 1
Reference numeral 2 denotes a bus connected to the read / write port of the master device 6 and the other side read / write port of the local buffer 15.

The local buffer 13 is a buffer in which a 128-bit bus 1 is connected to a read / write port on one side and a bus 10 is connected to a read / write port on the other side via a connection circuit 20. The data output to the bus 1 is fetched at the read / write port, and transferred using the bus 10. Conversely, it takes in the data transferred to the bus 10 and outputs it to the bus 1. Here, the bit width of the other side read / write port in the local buffer 13 is 128 bits at the maximum, but the connection circuit 2
Through 0, the bit width of the other side read / write port is set to the same bit width as the read / write port of the master device 4, that is, 64 bits. Since the read / write port of the master device 4 is 64 bits and the read / write port of the local buffer 13 is set to 64 bits, the transfer on the bus 10 is performed at a transfer rate of 64 bits.

Next, the input / output of the local buffer 13 will be described with reference to FIGS. FIG. 4 is a timing chart showing an operation timing when the local buffer 13 outputs data to the external memory device 2, and FIG. 6 is a timing chart showing the operation timing at the time.

Referring to FIG. 4, first, local buffer 1
Next, a process at the time of writing data from the memory device 3 to the external memory device 2 will be described. In the cycle c2, the data "data d0,1" transferred at 64 bits on the bus 10 is captured by the local buffer 13, and subsequently, at the cycle c3, the data "data d transferred at 64 bits on the bus 10".
The local buffer 13 takes in 2 and 3. The data d0, 1, 2, and 3 thus fetched are transferred to the bus 1 in cycle c4.

In the cycle c3, the memory controller 3
Outputs the write destination Ptr.4 for the master device 4, so that the data d0, 1, 2, and 3 transferred to the bus 1 in the cycle c4 are written to the write destination.
Similarly, in the cycle c4, the data d4,5 transferred on the bus 10 is captured, and in the cycle c5, the data "data d6,7" is captured by the local buffer 13. When the data is transferred to the bus 1 in the cycle c6, the data d4, 5, 6, 7 are transferred to the write destination address Ptr.
Is written to.

Next, a process for reading data from the external memory device 2 to the local buffer 13 will be described with reference to FIG. In cycle c3, the memory controller 3 sets the read destination address Ptr.
4 is output, data d0,1,
A few are transferred to bus 1. In a cycle c4, the local buffer 13 takes in the data d0, 1, 2, and 3 transferred in 128 bits on the bus 1. Subsequently, in cycle c5, of the data d0,1,2,3 thus fetched, data d0,1 is transferred to bus 10 in cycle c5, and data d2,3 is transferred to bus 10 in cycle c6. .

In cycle c5, the memory controller 3
Outputs the read destination Ptr.4 for the master device 4, so that the bus 1 stores the data stored in the read destination.
d4,5,6,7 have been transferred. In cycle c6, the local buffer 13 takes in the data "data d4, 5, 6, 7 transferred on the bus 1. Among the data d4, 5, 6, 7 thus taken, the data d4, 5 The data is transferred to the bus 10 in cycle c7, and the data d is transferred in cycle c8.
6 and 7 are transferred to the bus 10.

As described above, data output from the local buffer 13 to the bus 1 and data output from the bus 1 to the local buffer 1
It can be seen that it takes two cycles to fetch data into 3. The reason that the memory controller 3 performs memory access so that Data (Ptr. 4) is transferred to the bus 1 once every two cycles is because two cycles are required for data output and data fetch in the local buffer 13. It is. It can be seen that the difference between the transfer speed of the bus 1 and the transfer speed of the bus 10 is absorbed by the input and output of the local buffer 13.

In the local buffer 14 and the local buffer 15, the 128-bit bus 1 is connected to the read / write port on one side, and the bus 11 and the bus 12 are connected to the read / write port on the other side via the connection circuit 21 and the connection circuit 22. The buffer is a buffer that captures data output from the external memory device 2 to the bus 1 and transfers the data using the bus 11 and the bus 12. Conversely, it takes in the data transferred to the bus 11 and the bus 12 and outputs it to the bus 1. Here, the bit width of the other side read / write port in the local buffer 14 and the local buffer 15 is up to 128 bits,
Through the connection circuit 21 and the connection circuit 22, the bit width of the read / write port on the other side is set to the same bit width as the read / write port of the master device 5 and the master device 6, that is, 32 bits. As described above, the read / write ports of the master device 5 and the master device 6 have already been set to 32 bits, and the read / write ports of the local buffers 14 and 15 have been set to 32 bits. It is performed at the transfer rate.

Next, the input / output timing of the local buffer 14 will be described with reference to FIGS. FIG. 6 is a timing chart showing the operation timing when the local buffer 14 writes data to the external memory device 2. FIG.
5 is a timing chart showing operation timing when data is read from the external memory device 2.

Referring first to FIG.
4 will be described when data is written to the external memory device 2. In cycle c2, data d0 transferred in 32 bits on the bus 11 is fetched, and in cycle c3, data d1 is fetched. Similarly, cycle c4, c
At 5, data d2 and d3 are fetched. The data d0, 1, 2, 3 fetched as described above are transferred to the bus 1 in cycle c6.

In the cycle c5, the memory controller 3 outputs the write destination "Ptr.5" for the master device 4, so that the data d0, 1, 2, 3 transferred to the bus 1 in the cycle c6. The data is written to the write destination "Ptr.5". Similarly, in the cycles c6 and c7, the data d4 and d5 transferred on the bus 11 are used.
The local buffer 14 fetches 6,7. When the data d4, 5, 6, 7 thus fetched are transferred to the bus 1 in cycle c10, the data d4, 5, 6, 7 are written to the write destination address Ptr.

Next, a process for reading data from the external memory device 2 to the local buffer 14 will be described with reference to FIG. In the cycle c3, the memory controller 3 outputs the read destination “Ptr.5” for the master device 5, so in the cycle c4, the data d0,1,
A few are transferred to bus 1. In the cycle c4, the data “data d0, 1, 2,.
3 is taken into the local buffer 14. Then cycle c
In 5, the data d0 among the data d0, 1, 2, and 3 thus fetched is transferred to the bus 11, and in cycle c6, the data d1 is transferred. Data d2 is output in cycle c7, and data d3 is output in cycle c8.

Since the memory controller 3 outputs the read destination "Ptr. 5" for the master device 4 in cycle c7, the data d4, 5, 6, 7 are transferred to the bus 1 in cycle c8. The local buffer 14 takes in the data d4, 5, 6, 7 thus transferred. Then, in cycle c9,
The data d4 among the data d4, 5, 6, and 7 thus acquired is transferred to the bus 11, and in cycle c10, the data d5
To transfer. In cycle c11, data d6 is written, and in cycle c12
Then, data d7 is output.

As described above, data output from the local buffer 14 to the bus 1 and data output from the bus 1 to the local buffer 1
It can be seen that it takes four cycles to take in data into 4. The reason that the memory controller 3 performs memory access so that Data (Ptr. 5) is transferred to the bus 1 once every four cycles is because four cycles are required for data output and data fetch in the local buffer 14. It is. It can be seen that the difference between the transfer speed of the bus 1 and the transfer speed of the bus 11 is absorbed by the input and output of the local buffer 14.

The arbiter 16 arbitrates the use of the bus 1 when a conflict regarding the use of the bus 1 occurs between a plurality of master devices. As a result of the arbitration, an acknowledgment signal is output to the master device that is determined to use the bus 1. On the other hand, when the use of the bus is denied, the acknowledge signal is set to inactive or a hold signal is output. As a result, writing to the buffer or reading from the buffer is delayed, and bus transfer is delayed.

As described above, in the present embodiment, two of the four cycles are allocated to the data transfer of Data (Ptr. 4), and one of the remaining two cycles is one cycle.
Since data (Ptr.5) data transfer and Data (Ptr.6) data transfer are assigned, it is effective for any of the master devices 4 to 6 to wait for the use of the bus 1. Absent.

The local controller 17 controls the local buffer 13 to input / output data transferred to the bus 1 and data transferred to the bus 10. When writing data to the memory, the local controller 17 has a write pointer that points to the internal area of the local buffer 13, and transfers the 64-bit data transferred to the bus 10 to the local pointer indicated by the write pointer. The data is stored in the area of the buffer 13. After the output, the write pointer is incremented by 64 bits, and the next 64 bits are stored in the area indicated by the incremented write pointer. If such updating of the write pointer and storage of data in units of 64 bits are repeated for all data output to the bus 10, 128 bits of data are stored in the local buffer 13. After storing the 128-bit data in this manner, the data is output to the bus 1. After sending out 128 bits to the external memory device 2, it waits for the next 64 bits of data to be transferred to the bus 10, and if it is transferred, repeats the same procedure.

When reading data from the memory, the local controller 17 stores the data transferred to the bus 1 in the local buffer 13 and uses the read pointer of the 128-bit data read to the buffer. 64 bits from the designated portion are output to the bus 10. After the output, the read pointer is incremented by 64 bits, and the next 64 bits are output to the bus 10. If such updating of the read pointer and output of data in 64-bit units are repeated for all data read to the local buffer 13, the local buffer 13
Are transmitted to the master device 4. After sending out the 128-bit data to the master device 4, the process waits for the next 128-bit data to be transferred to the bus 1, and repeats the same procedure if it is transferred.

The local controllers 18, 19 are 64 bi
Although there is a difference between t and 32bit, the local controller 17
Similarly, the data transferred to the bus 1 and the buses 11 to
The local buffer 14 to the local buffer 15 are controlled so as to perform input / output with data transferred to the bus 12. The connection circuits 20, 21, and 22 are connected to the local buffer 1
3 to the local buffer 15 and the buses 10 to 12, respectively. The connection circuits 20 to 22 have a common circuit configuration. Even if there is a need to change the bit width of the read / write port for each of the buses 10 to 12, it is necessary to set the input / output of a plurality of selectors. Thus, the bit width of the read / write port can be easily changed. As described above, the connection circuits 20 to 22
Indicates the bit width of the read / write port of the local buffer 13 to the local buffer 15, respectively.
The bit width is set to be the same as the bit width of the read / write port of the master device 6. These bit widths are set by setting the input / output of a plurality of selectors provided in the connection circuits 20 to 22. More switching is possible.

Further, if there is a possibility that a bus lock may occur on the bus 1 with the current bandwidth, the external memory device 2 having an interface having a wider bandwidth is required.
By increasing the bit width of bus 1,
There is an effect that the bus lock can be easily prevented without changing the master device 4 to the master device 6 and the bus 10 to the bus 12.

As described above, according to the present embodiment, the bus 1 is connected to the external memory device 2 and the buses 10 to 12 are connected to the master device 4 to the master device 6, respectively. Since the local buffer 15 performs input / output of these buses, if it is desired to change the bandwidth to be allocated to the master device 4 to the master device 6, the master device 4 to the master device 6 and the bus 10 to the bus 12, the local buffer 1
Since it is only necessary to change the read / write port on one side of the local buffer 15, the external memory device 2, the memory controller 3, and the bus 1 do not need to be redesigned. Since the allocation of the bandwidth in the master device 4 to the master device 6 can be changed without changing the external memory device 2-the memory controller 3-the bus 1, even if the bandwidth needs to be changed in the future, the design can be made. Does not pay much effort.

(Application Example of First Embodiment) In this application example, 32
This proposes a circuit configuration when the bit buffers 61 to 32 bits, the buses 10 to 12, and the connection circuits 20 to 22 are shared. FIG. 8 shows 32-bit buffers 61 to 3
2 bit buffer 64, bus 10 to bus 12, connection circuit 20
It is a figure which shows the circuit structure at the time of sharing the circuit structure of No.-22. In FIG. 8, a 32-bit bus 57, a 32-bit bus 5
The 8, 32 bit bus 59 and the 32 bit bus 60 constitute the bus 10 to the bus 12, and have 32 bit buffers 61 to 32 bit.
Each of the buffers 64 constitutes a 128-bit buffer 13 to a 128-bit buffer 15. The four-input / one-output selector 65, the two-input / one-output selector 66, the gate 67, the gate 68, the selector 71, the selector 72, the selector 73, and the selector 74 all constitute the connection circuits 20 to 22. FIG. 9A is a diagram illustrating the selectors shown in FIG.
FIG. 9B shows only those used when reading to the bus 57 to 32 bit bus 60. FIG. 9B shows the selectors shown in FIG.
FIG. 7 is a diagram illustrating only those used when writing to the bit buffers 61 to 32 bits buffer 64;

The 32-bit bus 57, the 32-bit bus 58, the 32-bit bus 59, and the 32-bit bus 60 are buses having a bit width of 32 bits, respectively, and are connected to the master devices 4 to 6, respectively. When data transfer is performed by 64 bits, the 32-bit bus 57 to 32 bit bus 58 is used for transfer. When data transfer is performed by 32 bits, only the 32-bit bus 57 is used for transfer.

A 32-bit buffer 61, a 32-bit buffer 62,
The 32-bit buffer 63 and the 32-bit buffer 64 are buffers for holding 32-bit data, and are 32-bit buffers 61 to 3.
The entire 2-bit buffer 64 holds 128-bit bus data. The four-input / one-output selector 65, the two-input / one-output selector 66, the gate 67, the gate 68, the selector 71, the selector 72, the selector 73, and the selector 74 transfer data on the 32-bit bus 57 to the 32-bit bus 60 by 32 bits and 64 bits.
Input / output selection switching is performed so as to be performed with any bit width of t and 128 bits.

FIGS. 10 (a) and 10 (b) show input / output correspondence tables for these selectors and gates.
FIG. 10A shows the bit width and the 4-input / 1-output selector 65.
FIG. 7 is a diagram showing correspondence with connection lines selected by a gate 68. Referring to the column with a bit width of 32 bits, only the connection line A, connection line B, connection line
It can be seen that C and connection line D are described. This is 32
In the case of a bit transfer rate, the 4-input / 1-output selector 65
This indicates that the first to fourth 32-bit data are transferred onto the bus 57 via the connection lines A to D.

Referring to the column with a bit width of 64 bits, 4 inputs
It can be seen that the connection line A and the connection line C are described in the column for the -1 output selector 65, and the connection line B and the connection line D are described only in the column for the 2-input-1 output selector 66. This means that in the case of a transfer rate of 64 bits, the first and third 32-bit data are transferred onto the bus 57 via the connection lines A and C, and the second and third data are transferred via the connection lines B and D. 4th 32bit
It shows that data is transferred onto the bus 58.

Referring to the column with a bit width of 128 bits, the connection line A, 2 input-1
In the column for the output selector 66, the connection line B and the gate 67
It can be seen that the connection line C is described in the column for (1) and the connection line D is described in the column for the gate 68. This is 128bit
, The first to fourth 32-bit data are transferred to the bus 5 via the connection line A, the connection line B, the connection line C, and the connection line D.
7, bus 58, bus 59, and bus 60.

Subsequently, the four-input / one-output selector 65, the two-input / one-output selector 66, the gate 67,
The input and output of the gate 68 will be sequentially described. The 4-input / 1-output selector 65 selectively outputs the connection line A, the connection line B, the connection line C, and the connection line D to the bus 57 so that the data stored in the 32 bit buffers 61 to 32 bit buffer 64 can be stored. The data is sequentially transferred to the bus 57.

In the following description, the partial bits of the 128-bit data, which are located from the m-th high-order bit to the n-th high-order bit, are referred to in units of bits [m: n]. FIG. 11A is a timing chart when the bit width is 32 bits. When the transfer rate is only 32 bits, data transfer needs to be performed only by the bus 57.
Therefore, in the cycle c11 of FIG. 11A, the 4-input / 1-output selector 65 selects and outputs the connection line A to output the first 32-bit data. In the following cycle c12
The 4-input / 1-output selector 65 selects and outputs the connection line B for outputting the second 32-bit data, and selectively outputs the connection line C for outputting the third 32-bit data in the cycle c13. The 4-input / 1-output selector 65 selectively outputs the connection line D to output the fourth 32-bit data in the cycle c14.

FIG. 11B is a timing chart when the bit width is 64 bits. 64bit transfer rate
, The data transfer is performed by using the bus 57 and the bus 58 simultaneously. Therefore, the 4-input / 1-output selector 65 selectively outputs the connection line A to output the upper 32 bits of the first 64-bit data in the cycle c11 in FIG. 11B. 4 inputs in the next cycle c12-
The one output selector 65 selects the upper 32 bits of the second 64 bit data.
Selectively output connection line C to output bit data.

FIG. 11C is a timing chart when the transfer rate is 128 bits. Transfer rate 128b
In the case of it, the data transfer is performed by using the bus 57, the bus 58, the bus 59, and the bus 60 at the same time. Therefore, the 4-input / 1-output selector 65 sets the cycle c11
, The data of the connection line A is output so that the data stored in the 32-bit buffer 61 is transferred to the bus 57 by spending one cycle.

The two-input / one-output selector 66 selectively outputs the connection line B and the connection line D to the bus 57, thereby forming a 32-bit signal.
The data stored in the buffer 62 and the 32-bit buffer 64 are sequentially transferred to the bus 57. When the transfer rate is 64 bits as shown in FIG.
This is executed by using the bus 57 and the bus 58 simultaneously. Therefore, the 2-input / 1-output selector 66 sets the cycle c
In step 11, the connection line B is selectively output to output the lower 32 bits of the first 64 bits. Next cycle c12
In the 2 input-1 output selector 66, the second 64 bit
Select and output the connection line D to output the lower 32 bits of data. When the transfer rate is 128 bits, the data transfer is performed by using the bus 57, the bus 58, the bus 59, and the bus 60 simultaneously. Therefore, the 2-input / 1-output selector 66 sets the cycle c1 as shown in FIG.
In step 1, the connection line B is selectively output to output bits [95:64] of the 128-bit data.

The gate 67 sequentially transfers the data stored in the 32-bit buffer 63 to the bus 59 via the connection line C. The transfer rate is 128 bits as shown in FIG.
, The data transfer is performed by using the bus 57, the bus 58, the bus 59, and the bus 60 at the same time. For this reason, the gate 67 sets 128bi in cycle c11.
Select and output connection line C to output bits [63:32] of t data.

The gate 68 selectively outputs the data transferred to the connection line D to the bus 60, and
The data stored in the t buffer 64 is sequentially transferred to the bus 60.
To transfer. When the transfer rate is 128 bits, the data transfer is performed by using the bus 57, the bus 58, the bus 59, and the bus 60 simultaneously. Therefore, FIG.
As shown in (c), the gate 68 outputs a connection line for outputting bits [31: 0] of 128-bit data in cycle c11.
Select and output D.

Subsequently, the selector 71 shown in FIG.
Each of the selector 72, the selector 73, and the selector 74 will be described. FIG. 10B shows the bit width and the first
FIG. 21 is a diagram showing which connection lines are selectively output by selectors 71 to 74 in combination with connection lines to which the fourth data is transferred.

When the transfer rate is 32 bits, since the data transfer is performed only using the bus 57, the transfer rate is
Referring to the 32-bit column, it can be seen that the first, second, third, and fourth 32-bit data are all described as connection lines E. This means that in the case of a 32-bit transfer rate, the first to fourth 32-bit data are transferred to the 32-bit buffer 61, the 32-bit buffer 62, the 32-bit buffer 63, and the 32-bit buffer via the connection line E.
This indicates that the data is taken into the t buffer 64.

When the transfer rate is 64 bits, the data transfer is performed using the upper 32 bits on the bus 57 and the lower 32 bits on the bus 5.
8, the upper 32 bits of the first and second 64 bit data are described as connection lines E, and the lower 32 bits of the first and second 64 bit data are referred to in the column of the transfer rate of 64 bit. Is described as a connection line F. This means that, when the transfer rate is 64 bits, the first 64-bit data is transferred to the 32-bit buffers 61 and 3 via the connection lines E and F.
The second 64-bit data is taken into the 2-bit buffer 62, and the second 64-bit data is supplied to the 32-bit buffers 63 and 32 via the connection lines E and F.
This indicates that the data is taken into the bit buffer 64.

When the transfer rate is 128 bits, the data transfer is performed simultaneously using the buses 57, 58, 59, and 60.
Bits [127: 96] of the it data are described as connection line E, and
t [95:64] of data is connection line F, bit [6
3:32] is connection line G, and bits [31: 0] of 128-bit data are connection line
It is understood that H is described. This means that if the transfer rate is 128 bits, the 128-bit data is
32 bit buffer 61 via connection line G and connection line H respectively
3232 bit buffer 64.

The selector 71 takes the first data transferred on the bus 57 out of the 128-bit data transferred from the buses 57 to 60 into the 32-bit buffer 61. FIG. 12A shows the first 32
bit data, 2nd 32bit data, 3rd 32bit
It is a timing chart which shows the case where data and the 4th 32-bit data are transferred. In this figure, it can be seen that the selector 71 takes in only the first 32-bit data into the 32-bit buffer 61. FIG. 12 (b)
The upper 32 bits of the first 64-bit data and the second
6 is a timing chart showing a case where the upper 32 bits of the 64th data are transferred, and the lower 32 bits of the first 64 bit data and the lower 32 bits of the second 64 bit data are transferred on the bus 58. Also in this figure, the selector 7
1 indicates that only the upper 32-bit data of the first 64-bit data transferred by the bus 57 is taken into the 32-bit buffer 61. FIG. 12C shows a state in which the 12
Bits [127: 96] of the 8-bit data are transferred, and bus 5
8 bits [95:64] on 128, 128 bits on bus 59
6 is a timing chart showing a case where bits [63:32] of bit data and bits [31: 0] of 128-bit data are transferred onto a bus 60. Also in this figure, the selector 71
It can be seen that only [127: 96] of the 128-bit data transferred by the t bus 57 is taken into the 32-bit buffer 61.

The two-input / one-output selector 72 is connected to the bus 57 to
Of the 128-bit data transferred by the bus 60,
The connection line E and the connection line F are selected so that the bits [95:64] are taken into the 32-bit buffer 62, and are output to the buffer 62.
In FIG. 12A, the second 32 bits are transferred to the 32b via the connection line E.
In FIG. 12B, the lower 32 bits of the first 64-bit data are transferred to the it buffer 62 via the connection line F in the 32-bit buffer 62.
In FIG. 12C, [95:64] of the 128-bit data is taken into the 32-bit buffer 62 via the connection line F.

The selector 73 selects the bits [63: 3] of the 128-bit data transferred through the buses 57 to 60.
The connection lines E and G are selected so that the data corresponding to [2] is taken into the 32-bit buffer 63, and is output to the 32-bit buffer 63. 12C, the selector 73 converts the bits [63:32] of the 128-bit data transferred to the bus 59 to the connection line G.
It can be seen that the data is taken into the 32-bit buffer 63 via the.

The selector 74 selects the bits [31: 0] of the 128-bit data transferred through the buses 57 to 60.
The connection line E, the connection line F, and the connection line H are selected so that the data corresponding to the above is taken into the 32-bit buffer 64 and output to the 32-bit buffer 64. In FIG. 12C, the selector 74
Is the bit [3] of the 128-bit data transferred to the bus 60.
1: 0] is taken into the 32-bit buffer 64 via the connection line H.

In this application example, the 32-bit buffer 6
Since the bit widths of the 1, 32 bit buffer 62, 32 bit buffer 63, and 32 bit buffer 64 are all 32 bits, the transfer rate (bit width) can be changed in integer multiples of 32 bit data. If,
The transfer rate (bit width) can be changed in integral multiples of 8 bits. If all of these buffers are 16 bits, the transfer rate (bit width) can be changed in integral multiples of 16 bits. Thus, the bit width of the buffers 61 to 64 is
What is necessary is just to set according to how to set the transfer rate about each master device.

(Second Embodiment) In the first embodiment, each of the master device 4 to the master device 6 has a bus 10
Although each of the buses 12 is provided in a one-to-one ratio, the second embodiment is an embodiment in which a plurality of master devices are provided on the bus 10. FIG. 13 is a diagram illustrating a data processing device in which a plurality of master devices are provided on the bus 10.
In the figure, a master device 24 is provided on the bus 10 in addition to the master device 4.

The master device 24 is the master device 4
An application program that requests a DMA transfer with the same bandwidth as that described above is operating, and outputs a DMA transfer request to the local controller 17 when accessing the external memory device 2. When the master device 4 and the master device 24 output the DMA transfer request, the arbiter 25
Arbitration of these DMA transfer requests is performed, and an acknowledgment signal is sent to the master device to one of the master device 4 and the master device 24 so that the bus 1 is transmitted.
0 access right is granted. The master device 4 and the master device 24 that have obtained the access right perform the DMA transfer to the external memory device 2 as in the first embodiment. On the other hand, when the access right cannot be acquired, the acknowledgment signal is set to inactive or a hold signal is output. This delays the transfer to the bus. Instead of determining the access right of the bus 10 between the master device 4 and the master device 24 by the arbiter 25 for controlling all the buses, an arbiter dedicated to controlling each bus (here, the bus 10) is provided, and the arbiter is used by the arbiter. The same effect can be obtained with the mechanism for controlling the access right, and the arbiter mechanism can be simplified.

As described above, according to the present embodiment, for a plurality of master devices that perform media processing classified into subsystems, such as audio data, sub-pictures, OSDs, etc. Since the bus 10 and the local buffer 13 are associated with each other, the system can be simplified even when there are many media processes belonging to the subsystem.

(Third Embodiment) The third embodiment is an embodiment for realizing asynchronous control between the data processing device and the external memory device 2. Here, the asynchronous control between the data processing device and the external memory device 2 is required for the following reason. That is, when the master device 4 to the master device 6 perform media processing, the data processing device needs to realize synchronous control with the display device. , The local controller 17 to the local controller 19 must operate at an operating frequency based on the display period of the display device. On the other hand, the external memory device 2 must operate at the operating frequency because the optimal operating frequency is determined in the hardware specification. As described above, since the data processor and the external memory device 2 have different operation frequencies optimal for their operations, asynchronous control is required.

FIG. 14 shows the configuration of a data processing device capable of asynchronous control. What is new in FIG. 14 is that a dual port memory 26 is provided. The dual port memory 26 has one port connected to the external memory device 2 and the other port connected to the local buffer 1.
3 to the local buffer 15, and stores data read from the external memory device 2 and data output from the local buffers 13 to 15.

In the third embodiment, the master devices 4 to
The master device 6 obtains the data of the external memory device 2 through a two-stage read request. The first stage is reading from the external memory device 2 to the dual port memory 26. At this time, the master device 4 to the master device 6 output a read request to the memory controller 3 via the local controllers 17 to 19, and cause the memory controller 3 to read data from the external memory device 2 to the dual port memory 26. The second stage is reading from the dual port memory 26 to the DMA masters 4 to 6 via the local buffers 13 to 15. When necessary data is read from the dual port memory 26, the local controllers 17 to 19
, A read acknowledge signal is output from the memory controller 3 to the local controllers 17 to 19.
, Upon receiving this acknowledge signal, performs data transfer from the dual port memory 26 to the master device 4 to the master device 6 via the local buffer 13 to the local buffer 15 as in the first embodiment.

On the other hand, master device 4 to master device 6
Writes data to the external memory device 2 through a two-step write request. The first stage write request is the same write as in the first embodiment, and the master device 4 to the master device 6 store data to be written under the control of the local controller of the corresponding bus in the local buffer 1.
3 to write to the dual port memory 26 via the local buffer 15. The second stage is a write request from the dual port memory 26 to the external memory device 2,
Local controller 1 for memory controller 3
7 to 19 request writing.

In the third embodiment, when a request to read data from the external memory device 2 is issued from the master device 4 to the master device 6, the memory controller 3 issues a request to acquire a read / write port of the dual port memory 26 and acquires the data. At this stage, a read command is issued to the external memory device 2. Thus, data is read from the external memory device 2 to the dual port memory 26. The memory controller 3 waits for the data reading to be completed, and
When the necessary data is read out, a read acknowledge signal is returned to the local controllers 17 to 19. Further, the memory controller 3 includes the master devices 4 to
When data writing is requested from the master device 6 and data to be written to the external memory device 2 is accumulated in the dual port memory 26, a write command is issued to the external memory device 2 when the data is accumulated. Thereby, data writing from the dual port memory 26 to the external memory device 2 is performed.

In the third embodiment, when data read from the external memory device 2 is stored in the dual port memory 26 after the read request is issued, the local controllers 17 to 19
Is output to the local buffers 13 to 15. When a write request is made, a request to acquire a read / write port of the dual port memory 26 is issued when data to be written has accumulated in the local buffers 13 to 15, and when a read / write port has been acquired, the local buffer 13 to the local buffer are acquired. Data is written from the buffer 15 to the dual port memory 26.

As described above, according to the present embodiment, one port of the dual port memory is connected to the memory device, and the other port is connected to the plurality of buffers, so that the memory device and the internal memory can be connected. Asynchronous control in data transfer can be realized, and the external memory device 2 and the data processing device can operate at their own operating frequencies. Thus, even if the external memory device 2 is changed to a memory device having a different operating frequency, data transfer between the external memory device 2 and the inside of the apparatus may be performed in the same manner as before the change.

Even when an internal memory (on-chip memory) is added, data transfer between the external memory device and the added internal memory is performed between the external memory device and the existing internal memory. May be realized in the same manner as the data transfer of the above. Since not only the external memory device 2 can be changed but also the internal memory can be easily added, there is an effect that the degree of freedom in designing the memory architecture is increased.

(Fourth Embodiment) The fourth embodiment relates to an improvement in the case where the entry controller 113 integrally manages the data transfer between the master device and the external memory device 2 via the dual port memory 100. FIG. 15 is a diagram illustrating a configuration of a data processing device according to the fourth embodiment. As shown in the figure, the data processing device includes a dual port memory 100 (data unit 10).
1, tag unit 102), master device 103, master device 104, master device 105, local buffer 106, local buffer 107, local buffer 108, local controller 109, local controller 110, local controller 111, arbiter 112, entry controller 113, Read request queue 114, write request queue 1
15, a read wait queue 117, a read acknowledgment queue 118, a read acknowledgment queue 119, a read acknowledgment queue 120, an address selection circuit 121, and an address selection circuit 122.

The dual port memory 100 includes a data unit 101 and a tag unit 102. The data unit 101 includes two bank areas 101a and 101b, and each of the bank areas 101a and 101b includes 512 entry areas of 16 bytes. In this entry area, the external memory device 2-master device 103, 1
There are ones assigned to input / output buffers between the memory devices 04 and 105 (called a FIFO area, a total of 24 in the dual-port memory 100), and ones that the master device can use as a work area. Each entry area is provided with an entry address Entr_Addr, and each entry area is accessed by using this entry address Entr_Addr (entry areas existing in two bank areas use a common entry address Entr_Addr. Is accessed.)
Eight of the twenty-four FIFO areas are for reading from the external memory device 2, and the sixteen FIFO areas are for reading.
Allocated for writing to the external memory device 2. Each entry area includes 16 1-byte memory cells, and can store a total of 16 bytes of data.

The tag unit 102 also has 512 entries, and each entry is associated with each entry area of the data unit 101 on a one-to-one basis. Each entry of the tag unit 102 stores the external address Ext_Addr (read destination address or write destination address) in the external memory device 2 and identification information of the master device 103 that has requested access to the external address Ext_Addr. Have been. Tag unit 102
Each entry has a one-to-one data unit 1
Entry address Entr same as entry area 01
_Addr is assigned, and the designation of the access destination of the dual port memory 100 when performing data transfer between the external memory device 2 and the dual port memory 100 is performed by using the entry address Entr_Addr.

Master devices 103, 104, 105
Issues an access command. This access command is transmitted from the external memory device 2 to the master device 10.
3, 104 or 105, or write data from the master device 103, 104, 105 to the external memory device 2. The data read or data write is performed by the dual port memory 100. Data transfer between the FIFO area and the external memory device 2 and the dual port memory 1
00 FIFO area and master device 103, 10
4 and 105. Since any of these data reading or data writing uses the FIFO area in the dual port memory 100 as a relay point, the master devices 103, 104,
105 is an empty FIFO in the dual port memory 100
Only when it is clear that an area exists, an access command is issued. Since the presence / absence of an empty FIFO area in the dual port memory 100 is indicated in the usage information issued by the entry controller 113, the master devices 103, 104, and 105 monitor the usage information issued by the entry controller 113. Free in dual port memory 100
The access command is issued only when the FIFO area exists. If the use status information indicates that there is no empty FIFO area, the master device 103, 10
4 and 105 wait for an empty FIFO area to appear, and
After the FIFO area appears in the dual port memory 100, an access command is issued.

Local buffers 106, 107, 108
Is a buffer associated with each master device, and data rdat read from the external memory device 2.
It is used for input / output of a and input / output of data wdata to be written to the external memory device 2. By using this buffer, the difference between the bus width of 16 bytes for the dual port memory 100 and the bus width of the master devices 103, 104 and 105 can be absorbed. This buffer is a double buffer, and the master devices 103, 104, 10
5 can be performed in parallel with the access to the dual port memory 100, so that the speed of data transfer can be increased. Therefore, even if some master devices request data transfer at a high transfer rate, data input / output that satisfies such a transfer rate can be performed.

The local controllers 109, 110, 1
Reference numeral 11 is associated with each of the master devices 103, 104, and 105.
Local buffers 106, 10 for 04, 105
7, 108 and FI in the dual port memory 100
Between the FO area, data wdata to be written to the external memory device 2 or data rdata read from the external memory device 2 is transferred.

The details of writing data to the external memory device 2 are as follows. That is,
The usage status information monitored by the master devices 103, 104, and 105 includes the dual port memory 100
Address of empty FIFO area in
Since the Entr_Addr is indicated, the local controllers 109, 110, and 111 refer to the usage information to specify the location of the empty FIFO area, thereby temporarily storing the data wdata to be written to the external memory device 2. F
Store it in the IFO area.

The details of reading data from the external memory device 2 are as follows. That is, from the external memory device 2 to the dual port memory 1
00 is transferred to the local buffer 10.
In order to read out data up to 6, 107, and 108, the local controller 109, 110, 1
11 must know. Such an address, that is, a read destination address is included in a read completion notification issued from the memory controller 116, and the read completion notification is issued by the memory controller 116 and read acknowledgment via the read wait queue 117. The data is stored in the queues 118, 119, and 120. The local controllers 109, 110, and 111 can know where the data rdata read from the external memory device 2 is stored in the dual port memory 100 by extracting the entry address Entr_Addr from the read completion notification. . Then, if the location of the data rdata read from the external memory device 2 is known, the local buffers 106, 107,
108 and the entry address included in the read completion notification
By transferring data rdata read from the external memory device 2 to and from the FIFO area corresponding to Entr_Addr, the master device 103, 10
4. Data can be delivered to 105.

The arbiter 112 is the master device 10
The use arbitration of the dual port memory 100 is performed between 3, 104, and 105. The arbiter 112 performs such arbitration for the following reason. That is, data read from the external memory device 2 to the master device and data write from the master device to the external memory device 2 are both performed in the dual port memory 10.
As described above, the process is performed with 0 as a relay point.
Then, the data transfer is concentrated most between the dual port memory 100 and the local buffers 106, 107, and 108. Therefore, in the present embodiment, when each master device uses the dual-port memory 100, the arbiter 112 is given the right to determine which master device is permitted to use the dual-port memory 100. When the access command is issued, the arbiter 112 allows any one of the plurality of master devices 103, 104, and 105 to transfer data via the dual-port memory 100, and Data transfer via the dual port memory 100 is not permitted to 103, 104, and 105.
Thus, data transfer via one dual port memory 100 is performed efficiently.

The entry controller 113 is a bit string that individually indicates a FIFO area that has already been used for data storage (one that is being used) and one that has not been used for data storage (one that is unused). (Current state bit string), and if all the bits in the current state bit string are set to “1”, the use status information indicating that there is no empty FIFO area is notified to each master device. At the same time, if any bit in the bit string is set to off "0",
The entry address Entr_Addr corresponding to the bit is notified to each master device as use status information. FIG.
FIG. 6 is a diagram showing an example of a current state bit string. In this figure, the current state bit string is 32 bits
A bit string of data, and the 0th to 5th bits in the current state bit string are the entry address Entr_Add
r00 to entry address Entr_Addr05,
The 6th to 31st bits correspond to entry addresses Entr_Addr06 to entry address Entr_Addr31. This entry address Entr_Addr00 to entry address Ent
Since the 0th to 5th bits corresponding to r_Addr05 are all set to ON “1” in FIG. 16, the FIFOs of the entry addresses Entr_Addr00 to Entr_Addr05 are used.
The area is in use. This entry address Entr_Add
r06 to 6 to 31 corresponding to the entry address Entr_Addr31
Since the bits are all set to off "0" in FIG. 16, the FIFO areas of the entry addresses Entr_Addr06 to Entr_Addr31 are not used.
Thus, in the example of FIG. 16, the entry address Entr
Since the entry area of _Addr06 to entry address Entr_Addr31 is indicated as being unused, the entry controller 113 selects the first one of the empty entry addresses indicated in the current state bit string (in the example of FIG. , Entry address Entr_Add
r06) is notified to each master device as use status information.

An unused FIFO area is assigned to the master device 103.
The details of the processing to be assigned to are as follows. It is assumed that the master device 103 has issued the access command with reference to the output usage status information. If the arbiter 112 permits data transfer via the dual port memory 100 to the master device 103 which has issued the access command, the entry controller 113 transfers the entry address Entr_Addr to the transfer destination or the transfer destination. This entry address En is used to perform the original data transfer.
Request data including tr_Addr (there are types of read request and write request) is stored in the read request queue 114 and the write request queue 115. Here, a description will be given of the format of the request data in the present embodiment and how the data transfer using the request data is performed. The request data (there is a read request and a write request) in this embodiment differs from the access command in that the request data includes the entry address Entr_Addr in the dual port memory 100. As described above, in the tag area specified by the entry address Entr_Addr, the external address Ext_Addr to be accessed in the external memory device 2 is stored. By performing data transfer between the Entr_Addr and the external address stored in the tag area indicated by the entry address, data can be read from the external memory device 2 to the dual port memory 100 or read from the dual port memory 100. Data writing to the external memory device 2 is realized.

The request data is created and issued by the entry controller 113, and is divided into a read request and a write request according to the order in which the request data is issued. Stored. When the request data is issued to the memory controller 116, the entry controller 113 sets, in the current state bit string, the bit allocated to the notified entry area in use. On the other hand, in the tag area specified by the notified entry address Entr_Addr,
External address Ext_ issued from master device 103
Addr is stored. By the above processing, the FIFO area allocated to the master device 103 is allocated for storing the data rdata read from the dual port memory 100 and for storing the data wdata to be written to the external memory device 2.

The details of the processing for releasing the FIFO area to unused are as follows. For example, if data is read from the external memory device 2 to the FIFO area after issuing the read request, the entry controller 113 waits for data in the FIFO area to be transferred from the dual port memory 100 to the master device. If such transfer is performed, there is no need to store the data in the FIFO area, so the entry controller 113 changes the bit corresponding to the FIFO area in the current state bit string from in use to unused.

If data is written from the master device 103 to the FIFO area after the issuance of the write request, the entry controller 113 transfers the data in the FIFO area from the dual port memory 100 to the external memory device 2.
When the transfer is performed, the entry controller 113 changes the bit corresponding to the FIFO area in the current state bit string from used to unused.

As described above, by updating each bit in the current state bit string, the use state of each FIFO area is reflected on the current state bit in real time. As described above, since a plurality of FIFO areas are respectively allocated for reading and writing, when allocating an empty area to the master device 103, the entry controller 113 transmits an access command from the external memory device 2 to the master device 103. The FIFO area is allocated in consideration of whether the request is for reading data or writing to the external memory device 2.

When the master device issues an access command for requesting data reading from the external memory device 2, the entry controller 113 uses the FIFO area allocated for data reading for input / output in the data transfer. The FIFO area to be selected is selected, and the entry address Entr_Addr is output to the master device. When the master device issues an access command requesting data writing to the external memory device 2, a FIFO area to be used for input / output in the data transfer is selected from the FIFO area allocated for data writing. Outputs the entry address Entr_Addr to the master device.

As described above, the FIFO area is used for reading data from the external memory device 2,
Even if one of the data reading from the external memory device 2 and the data writing to the external memory device 2 is concentrated, the other process is prevented from being delayed. be able to.

The memory controller 116 extracts a plurality of request data stored in the read request queue 114 and the write request queue 115 one by one, and transfers data between the dual port memory 100 and the external memory device 2. When the data transfer between the external memory device 2 and the dual port memory 100 is data reading from the external memory device 2, the memory controller 116 stores the request data in the read wait queue 117. Then, the memory controller 116 waits for read data to be output from the external memory device 2 and outputs the read data. When the read data is stored in the data unit 101 of the dual port memory 100, the read data is stored in the read wait queue 117. Read acknowledgment queue 11
8, 119, and 120.

Read Acknowledge Queues 118 and 11
Reference numerals 9 and 120 store the request data output from the read wait queue 117 corresponding to each master device for each master device. When the request data for each master device is stored in each of the read acknowledge queues 118, 119, and 120, the local controllers 109, 110, and 111 issue the read command to request the external memory device 2-dual port. It is possible to know that the data reading between the memories 100 has already been completed. In this way, the local controller 109 that has noticed the transfer completion,
110 and 111 issue read commands to request data reading from the dual port memory 100 to the master devices 103, 104 and 105, and the dual port memory 100-local buffer 10 as described above.
If data transfer between 6, 107 and 108 is performed, data stored in the dual port memory 100 will be sequentially delivered to each master device.

The address selection circuit 121 receives the master device 103 as an access destination in the access command,
The external address Ext_Addr issued from 104 or 105 is selectively output. The master device 103 whose request has been granted by the arbiter 112 is connected to the external memory device 2
When requesting data transfer between the dual port memories 100, the address selection circuit 121 causes the external address Ext_Addr output by the master device 103 to be stored in the tag area so that the external address output by the master device 103 is stored. Output Ext_Addr to the tag area. When the master device 103 whose request has been permitted by the arbiter 112 requests data transfer between the master device 103 and the dual-port memory 100, the master device 103 transmits data between the data unit 101 and the master device. The output entry address Entr_Addr is output to the data unit 101.

When data transfer is performed between the dual port memory 100 and the external memory device 2, the address selection circuit 122 outputs the entry address Entr_Addr output from the entry controller 113 to the data unit 101 and the tag unit 102. On the other hand, dual port memory 100-master device 103, 10
When performing data transfer between the master devices 103, 104, 1, and 1 via the address selection circuit 121,
The entry address Entr_Addr output from the data port 05 is output to the data unit 101 of the dual port memory 100.

As described above, according to the present embodiment, the master device 103 is connected via the dual port memory 100.
-Data transfer between the external memory devices 2 can be performed. (Fifth Embodiment) In the fifth embodiment, the dual port memory 100 used for input / output between the external memory device 2 and the master devices 103 to 105 is used as a work area of the master devices 103, 104, and 105. Regarding improvement when using it. FIG. 17 is a diagram illustrating a data processing device according to the fifth embodiment.

In order to use the dual port memory 100 as a work area, the master devices 103, 104, and 105 according to the fifth embodiment require entry area tables 123, 124, and 12 used as work areas.
5 are held. Specifically, the table associates the entry address Entr_Addr for the work area with the identification information Id of the master device to which the work area is assigned.

The access command according to the fourth embodiment requests data reading from the external memory device 2 or data writing to the external memory device 2. However, the access command according to the fifth embodiment includes: Data read from the dual port memory 100 to the master device 103 or the master device 1
03 is a command requesting data writing to the dual port memory 100, that is, the dual port memory 1
The master device 103 according to the fifth embodiment is a command for requesting data reading or data writing for the dual port memory 100.
Is issued to the arbiter 112. Therefore, in FIG. 17, it is described that the entry address Entr_Addr is issued from each master device.

The arbiter 112 according to the fifth embodiment includes:
When an access command requesting access to the dual port memory 100 is issued by the master devices 103, 104, and 105, data transfer to the dual port memory 100 is performed to the master device 103 as in the fourth embodiment. It is determined whether to permit or not.

The local controllers 109, 110, and 111 according to the fifth embodiment include master devices 103-1.
05, an access command to the dual-port memory 100 is issued, and if data transfer to the dual-port memory 100 is permitted by the arbiter 112, the data is transferred between the entry area designated by the access command and the master device 103 to 105. Perform data transfer. Thereby, the master devices 103 to 1
Data writing from the entry area 05 to the entry area or data reading from the entry area to the master devices 103 to 105 is realized.

For example, one master device 103 issues an access command to write predetermined data to an entry area x allocated to the own device, and another master device 104 writes the data in the entry area x. It is assumed that an access command for reading data is issued. Thus, the two master devices 103, 10
4 writes data to and reads data from the entry area, the master devices 103 and 104
Data can be transferred via the entry area x.

As described above, according to the present embodiment, data can be transferred between the master devices 103 and 104 by reading and writing data between the master device and the dual port memory 100. Collaboration between devices is promoted. (Sixth Embodiment) This embodiment relates to an improvement in which each master device can freely execute a DMA transfer between the external memory device 2 and the dual port memory 100. FIG. 18 shows the configuration of the data processing device according to the sixth embodiment.

In FIG. 18, the data processing device includes a DM.
A controller 126 is provided, and in the sixth embodiment, the master devices 103, 104, and 105
A DMA command for performing a DMA transfer between the external memory device 2 and the dual port memory 100 is output to the DMA controller, and a DMA address is issued to the DMA controller 126 together with the DMA command. Here, the DMA address indicates an entry address Entr_Addr as a transfer source and a transfer destination, and an external address Ext_Addr. When an access command (referred to as a DMA command) requesting a DMA transfer is issued, the DMA controller issues an entry address En designated as a transfer source and a transfer destination in the access command.
It holds the tr_Addr and the external address Ext_Addr, and requests the arbiter 112 to permit data transfer in this DMA command as in the case of other access commands.
If access to the dual port memory 100 is permitted to the arbiter 112, the external address specified by the access command is stored in the tag area corresponding to the entry address Entr_Addr specified by the access command.
Ext_Addr is stored, and the relevant entry address Extr
_Addr along with the transfer direction, read request queue 1
14 or the write request queue 115, causing the memory controller 116 to perform data transfer between the entry area specified by the entry address Entr_Addr and the external area indicated by the external address Ext_Addr.

The memory controller 116 performs data transfer between the external memory device 2 and the dual port memory 100 as in the fourth embodiment. When such data transfer is performed, the memory controller 116 outputs a notification DMA_done to the effect that the requested data transfer is completed to each master device, and notifies each master device that the DMA command has been executed.

As described above, according to the present embodiment, the master devices 103 to 105 are
Like the data transfer between the external memory device 2 and the external memory device 2, the data transfer between the external memory device 2 and the dual port memory 100 can be commanded to the DMA controller. The data can be stored in the memory 100, and data can be read from the external memory of the master device at high speed.

(Seventh Embodiment) In the seventh embodiment, an arbiter 112 capable of adjusting the use permission of the dual port memory 100 for a certain master device.
Related to improvements. FIG. 19 shows the configuration of an arbiter 112 according to the seventh embodiment. As shown in FIG.
The arbiter 112 includes a ring register 131, a shift control unit 132, an arbitration unit 133, and a storage control unit 134.

The ring register 131 includes n registers connected in a ring shape.
The identification information about each master device is stored. In n cycles, the shift control unit 132 cyclically shifts the identification information stored in each of the n registers so as to identify each of the n identification information stored in the n registers as current information. Let it.

The arbitration unit 133, during the cycle in which the identification information on the master device x is specified as the current information among the n cycles,
When an access command is issued by x, data transfer via the entry area in the dual port memory 100 is permitted to the master device x. On the other hand, the arbitration unit 133 generates identification information x for the master device x.
Is the current information, and in the cycle in which the master device x is specified as current, if the master device x has not issued an access command, the priority Data transfer is permitted for the highest one that issued the access command.

Further, when the master device x does not issue an access command and no master device having a lower priority than the master device x has issued an access command,
Among the master devices having higher priorities than the master device x, data transfer is permitted to the device having the highest priority and issuing the access command.
For example, when the current is the master device x having the priority = 3, if the master device x having the priority = 3 issues an access command, data transfer to the master device x via the dual port memory 100 is permitted.
On the other hand, although this master device x has not issued an access command, the priority order is 4, 5, 6, 7, and so on.
If a master device with a lower priority than = 3 issues an access command, of these master devices,
Data transfer via the dual port memory 100 is permitted to the master device having the highest priority (in this case, the master device having priority = 4). Further, the master device x and the master device having a lower priority than the master device x have not issued the access command, but the master device having a higher priority than the priority = 3, such as the priority = 1, 2, has access. When the command is issued, the master device having the highest priority among these master devices (in this case, the master device having the priority = 1) is permitted to transfer data through the dual port memory 100. .

The storage control unit 134 transfers data for a specific master device (master device x) out of a plurality of master devices m times for n times (m is n> m).
When it is desired to permit the identification at a rate of (an integer satisfying), as shown in FIG. 20, the identification information x on the master device x is stored in m registers among the n registers. Here, identification information x is stored in m of n registers, and identification information x is specified as current information in m cycles of n cycles,
Access to the dual port memory 100 by the master device x is permitted at a rate of m cycles (n> m) for every n cycles. Therefore, the frequency of memory access by the master device x is adjusted.

As described above, according to the present embodiment, m cycles (n> m) for every n cycles for a certain master device
, The frequency of access can be adjusted, so that the access frequency can be set freely.
In this embodiment, data transfer via the dual port memory 100 is permitted as soon as an access command is issued from a specific master device, regardless of which master device identification information becomes current information. You may.

(Eighth Embodiment) The eighth embodiment is an embodiment in which the data processing apparatus is implemented as a media core processor that performs a plurality of media processes. FIG.
FIG. 18 is a diagram showing memory allocation of the external memory device 2 in the eighth embodiment. In the figure, the external memory device 2 has a coded stream buffer area 19
8, an image frame area 199 is allocated.

The encoded stream buffer area 198 is
This area is for storing the MPEG stream input from the outside without decoding. Here, the MPEG stream is a bit stream including a plurality of elementary streams. The elementary streams include a moving image stream and an audio stream. The moving image stream is composed of a plurality of macro blocks (MB). The moving picture stream is information-compressed based on the temporal correlation between the images, using the macroblock as a coding unit. At the time of decoding, motion compensation of the inter-frame prediction method is performed using the macro block as a decoding unit. A macroblock is composed of 16 × 16 pixel data. Here 16x horizontal
The 16 pixel data has a luminance block Y0, Y1, Y2, Y3 composed of 8 × 8 luminance data. And a red difference block Cr composed of eight vertical red difference data.

The image frame area 199 stores pixel data, still image data, and OSD pixel data obtained by decoding a moving image stream. FIG.
FIG. 21 is a diagram showing an internal configuration of a data processing device according to a ninth embodiment. In FIG. 22, ten master devices are mounted, and each master device performs video decoding processing,
Audio decoding processing, video output processing, computer
Various media processing such as graphics drawing processing is executed.

When each master device performs media processing, the external memory device 2 is used for various processing operations such as an MPEG stream decoding process. Next, the internal configuration of the data processing device when performing processing as a media core processor will be described. As shown in FIG. 22, the data processing device includes a stream unit 201, an I / O buffer 202, and a setup processor 20.
3. Bit stream FIFO 204, VLD 205, TE20
6, POUA 207, POUB 208, POUC 209, audio unit 210, IOP 211, VBM 212, video unit 213, HOST unit 214, RE 215, FILTER 21
Consists of six. Of these components, for the master device, the master device name (master0,1,
2, 3, 4,..., 8, 9). In this figure, the local buffer 106, the local controller 109,
The read acknowledgment queue 118 and the like are shown as one master peripheral circuit. When the connection relationship between the dual port memory 100 and the master device is omitted from the internal configuration of the data processing device, the internal configuration of the data processing device is represented as shown in FIG. As is clear from this figure, the external memory device 2 and the dual-port memory 100 include the master devices master0, 1, 2, 3, 4,.
··························································································································· デ ー タ ·

[0131] When an MPEG stream is extracted from a recording medium or a communication medium and input to the media core processor, the stream unit 201 separates the MPEG stream into a moving image stream and an audio stream and writes the separated stream into the I / O buffer 202. Setup processor (Setup) 203
A master device (master7) that decodes an audio stream multiplexed with an MPEG stream and stores uncompressed audio data in a master peripheral circuit and a dual port memory 1
00 to the external memory device 2. The audio stream is sequentially converted to a bit stream FIF by the IOP 211.
The setup processor 203 extracts the audio stream from the bit stream FIFO 204 and decodes the audio stream.

The variable code length decoding unit (VLD) 205 extracts a macroblock MB from the moving picture stream and outputs the four luminance blocks Y0, Y1,
Variable code length decoding is performed on Y2, Y3 and the two color difference blocks Cb, Cr. The video stream is sequentially supplied to the bit stream FIFO 204 by the IOP 211 and the VLD2
In step 05, the moving image stream is extracted from the bit stream FIFO 204, and the moving image stream is decoded.

Transform engine unit (TE) 206
Is a master device (master3), and the four luminance blocks Y0, Y having undergone variable code length decoding by the VLD 205.
Inverse quantization and inverse discrete cosine transform are performed on 1, Y2, Y3 and the two color difference blocks Cb, Cr, and the result is written to the external memory device 2 via the master peripheral circuit and the dual port memory 100.

Pixel operation unit A (POUA)
207 are four luminance blocks Y0, Y1, Y2, Y3 subjected to inverse quantization and inverse discrete cosine transform, and two color difference blocks Cb, C
r is written to the external memory device 2, these 4
Two luminance blocks Y0, Y1, Y2, Y3 and two color difference blocks C
b and Cr from the external memory device 2 and
The corresponding reference image is read from the image frame area 199 in the external memory device 2. Thereafter, half-pel processing was performed on the reference image, and the result was averaged, and inverse quantization and inverse discrete cosine transform were performed.
Two luminance blocks Y0, Y1, Y2, Y3 and two color difference blocks C
b and Cr are added together (the above processing is called motion compensation). Thereafter, the result of the motion compensation is written to the image frame area 199 of the external memory device 2 via the master peripheral circuit and the dual port memory 100.

The POUA 207 performs an on-screen display (OSD) drawing process. The OSD is a character font or computer graphics that is overlaid on a moving image according to an operator's instruction. The OSD is a counter for displaying the current time and data processing such as "play", "stop", and "record". The device is used to display the current processing content on the display screen. The POUA 207 performs data transfer between the dual port memory 100 and the master device, and the data transfer between the external memory device 2 and the dual port memory 100 is entrusted to the POUC 209.

Pixel operation unit B (POUB)
Reference numeral 208 denotes a master device (master2) that performs filtering processing on an image and performs enlargement / reduction processing, and performs data transfer between the dual port memory 100 and the master device. Like the POUA 207, data transfer between the external memory device 2 and the dual port memory 100 is left to the POUC 209.

Pixel operation unit C (POUC)
209 is a master device (mass) that performs input / output between the external memory device 2 and the dual port memory 100 by outputting the DMA command described in the seventh embodiment.
ter0). The audio unit 210 sequentially reproduces and outputs audio data stored in the I / O buffer 202.

The I / O processor (IOP) 211 has the following
It is a master device that performs three transfer processes. In the first transfer process, the MPEG stream sequentially input from the stream unit 201 and sequentially stored in the I / O buffer 202 is transferred to the coded stream buffer area of the external memory device 2 via the master peripheral circuit and the dual port memory 100. 198. The second transfer processing is performed according to the progress of the decoding processing by the Setup processor 203 and the VLD 205,
This is a process for supplying a moving image stream and an audio stream to the. That is, the IOP 211 is the bit stream FIFO 204
Video and audio streams stored in
It monitors how much is decoded by the Setup processor 203 and the VLD 205. If the predetermined amount is decoded, the moving image stream and the audio stream are read from the external memory device 2 so as to supplement the predetermined amount of the MPEG stream, and are supplied to the bit stream FIFO 204. As a result, underflow of the bit stream FIFO 204 is avoided, and the setup processor 203 and the VLD 2
05 will continue without interruption.

The third transfer processing is performed by the Setup processor 20.
3, the uncompressed audio data sequentially written to the external memory device 2 by the decoding process
This is a process of reading out data via the 0 and the master peripheral circuit and supplying it to the I / O buffer 202. If the uncompressed audio data is sequentially supplied to the I / O buffer 202, the audio data is sequentially reproduced and output by the audio unit 210.

The video unit (VU) 213 is a master device (master4), reads a few lines of pixel data from the image frame area 199 of the external memory device 2, and stores it in the video buffer memory (VBM) 212. Then V
A process of converting a few lines of pixel data read by the BM 212 into a video signal and outputting the video signal to a display device such as a television receiver connected externally is performed.

The host unit (HOST) 214 is a master device (master5) for performing control according to an instruction from a host microcomputer connected to the data processing device inside the data processing device. Rendering engine (RE) 215
Is a master device (master 9) for performing rendering processing in computer graphics, and performs control when a dedicated LSI is connected to the data processing device.

The filter (FILTER) 216 performs the enlargement / reduction processing of the still image data. Like RE, dedicated to data processing equipment
Master device that controls when LSI is connected (mast
er6). This concludes the description of the components of the data processing device. Then, in the data processing device performing processing as a media core processor, how to arbitrate access to the dual port memory 100 in the nine master devices Will be described. FIG.
FIG. 7 is a diagram showing how priorities are set for a plurality of master devices. According to this figure, the priority order for the master device is order 1: POUA20.
7, ranking 2: POUB208, ranking 3: TE206, ranking 4:
VU213, Rank 5: HOST unit, Rank 6: FILTER21
6, rank 7: Setup processor 203, rank 8: IOP21
It can be seen that 1, rank 9: RE215 is set. These priorities are the same as numerical values such as “1”, “2”, “3”, “4”,... Assigned to each master device. The arbiter 112 permits data transfer via the dual-port memory 100 to any of the master devices according to the procedure described in the ninth embodiment while referring to the priorities assigned to these master devices.

As described in the seventh embodiment, the number of times each master device is permitted is adjusted according to the number of pieces of identification information of each master device stored in each shift register. The number of times each master device is permitted is defined by storing the identification information of the master device. The register column in FIG. 24 indicates which master device identification information is stored in each of the 22 registers. In this figure, of the 22 registers, the POUA2
07 identification information "1" is stored in two registers POUB
208, the identification information “3” of the TE 206 in the two registers, and the identification information “4” of the VU 213 in the two registers.
Are stored respectively. As described above, since the identification information “1” of the POUA 207 is stored in the eleven registers, P
Data transfer for the OUA 207 is permitted at a maximum of 11 times in 22 cycles. The POUB 208 is permitted up to twice out of 22 cycles, TE is permitted up to twice, and VU is permitted up to twice.

Therefore, each master device is permitted to transfer data via the dual port memory 100 at the following ratio. POUA: POUB: TE: VU: FILTER: SETUP: IOP: RE = 11: 2: 2: 2: 1: 1:
As described above, according to the present embodiment, since each master device that performs media processing is connected to the dual port memory 100 via the master peripheral circuit, the read / write port of these master devices is Even if it becomes necessary to modify the bit width, such modification can be easily performed.

(Ninth Embodiment) Dual Port Memory 1
It relates to an improvement in the case of using a memory cell of 1 byte = 9 bits in 00. FIG. 25 is a diagram illustrating a configuration of an entry area according to the ninth embodiment. As shown in this figure,
In the ninth embodiment, the 16-byte entry area is
It consists of 16 memory cells of 1Byte = 9bit. These
If a memory cell of 1 byte = 9 bits is used, (1) delivery of signed 8-bit data and (2) delivery of unsigned 8-bit data can be performed at high speed as described below.

(1) Delivery of signed 8-bit data When 1 byte = signed 8-bit is set, the ninth bit is used as a sign bit. FIG.
FIG. 11 is a diagram illustrating bit assignment of a memory cell when byte = signed 8 bits is set. Here, among a plurality of master devices existing in the data processing device, one master device is a TE 206 that performs inverse quantization cosine transform (IDCT) in the MPEG decoding process, and the other master device is a motion compensation device in the MPEG decoding process. POUA to process
207. IDCT processing result is signed
Since these are represented as 8-byte data, these two master devices must transfer signed 8-bit data. Here, the dual port memory 100 is 1
Since the byte is composed of 9-bit memory cells, the TE 206 that performs IDCT writes signed 8-byte data to the dual-port memory 100, and the POUA 207 that performs motion compensation writes the code that has been so written. With
When the 8-byte data is read from the dual port memory 100 and used, the delivery of the signed 8-byte data is performed at high speed between these two master devices.

(2) Delivery of unsigned 8-bit data When 1 byte = 8 bits without sign, the ninth bit is used as a mask bit. FIG. 26 (b)
FIG. 4 is a diagram showing bit allocation of a memory cell when 1 byte = 8 bits without a sign is set. Here, when writing data from the dual-port memory 100 to the external memory device 2, of the 32 bytes of data included in the entry area, 1-byte data to be written to the external memory device 2 is located at the ninth bit. Off the mask bit to "0". On the other hand, for 1-byte data for which writing to the external memory device 2 is to be prohibited, the mask bit located at the ninth bit is set to “1”.

At the time of writing from the dual port memory 100 to the external memory device 2, 1-byte data whose mask bit is set to “0” is written to the external memory device 2. On the other hand, the one-byte data with the mask bit set to ON “1” is not written to the external memory device 2, and the original value of the external memory device 2 is maintained. FIG. 27 is a diagram showing how the external memory device 2 is written when the mask bit is set. The lower part of the figure shows an entry area composed of areas (1) to (5). Of these, areas (1) and (3)
It is assumed that the mask bit is set to 1 in 1-byte data forming (5), and the mask bit is set to 0 in 1-byte data forming regions (2) and (4). Then, the portion of the external memory device 2 corresponding to the areas (2) and (4) is overwritten by the contents of the entry area, but the parts corresponding to the areas (1), (3) and (5) are Will be removed from the overwrite using, and the original value will be maintained.

Each 1-byte data is transferred to the external memory device 2
Is set using a mask bit, so the mask bit can be applied to an application such as combining a character pattern with an image. Here, it is assumed that one screen of image data is stored in the external memory device 2. In order to combine the image data stored in the external memory device 2 with a character pattern, the master device must perform so-called Read & Modify & Write. That is, each master device once reads out (Read) the image data stored in the external memory device 2, fetches the image data, and performs processing for synthesizing with the character pattern (Modif
y), after combining the character patterns, the external memory device 2
A process of writing back (Write) must be performed. At this time, each master device has to perform two processes of reading the image data stored in the external memory device 2 and writing the read image data, so that the processing load increases.

Therefore, by using the mask bits, the image data stored in the external memory device 2 and the character pattern can be easily synthesized as follows.
When combining character patterns and image data,
Character data is stored in the dual port memory 100. This character data includes a background portion and a stroke portion. Here, among the 1-byte data stored in the dual-port memory 100, the mask bit is set to "1" for the background portion of the character, and the stroke portion of the character in the 1-byte data is set. The mask bit is set to off "0" for those corresponding to.

When data is written from the dual port memory 100 to the external memory device 2 with the mask bit set in this manner, a portion of the image of the external memory device 2 corresponding to the stroke portion of the character Is overwritten using the data stored in the dual-port memory 100, and the portion of the image of the external memory device 2 corresponding to the background portion of the character is overwritten using the data stored in the dual-port memory 100. Excluded from By setting a mask bit and writing the character pattern stored in the dual port memory 100 to the image data stored in the external memory device 2, it is possible to easily obtain a combined image in which the image and the character are combined. Can be.

Although the description has been given based on the above embodiment,
It is only presented as an example of a system that can be expected to have the best effect at present. The present invention can be modified and implemented without departing from the gist thereof. Representative modified embodiments include the following (a), (b), (c),.... (A) The data shown in FIG. 28 may be stored in the tag area of the dual port memory 100 shown in FIG. Here, an example is shown in which one command is composed of two tag areas. Tag2Valid located at bit 22 in FIG. 28 is a flag indicating whether or not the second tag information of one command is valid. The MB access bit located at the 23rd bit is a code indicating whether or not it is for storing a macroblock. Do at the 24th bit
The ne bit is a code indicating whether or not it is the last data of the transfer requested by the master device. The DMA mode bit in the 25th bit indicates that the transfer between memories is performed in the external memory device 2-
Data transfer between the dual port memories 100,
Indicates whether data transfer is between the external memory device 2 and the master device. The 16B / 32B access flag in the 26th bit indicates whether one of the two bank areas constituting one entry area (16 bytes) is valid or both (3 bytes)
2 bytes) are valid. 27th bit Tag1Va
lid is a flag indicating whether or not the first tag information of one command is valid. 28 to 30 bits are the master device ID, and POU DMA at 31 bits
The MODE flag is a code indicating whether or not the POU DMA MODE is turned on "1".

(B) Each master device may be connected to a control bus to exchange information between the master devices. The control bus is a bus for transmitting the entry address when each master device notifies each other of the entry address at the time of data writing according to a predetermined rule. When at least one or more of the plurality of master devices requests data writing to the external memory device 2, an entry address indicating a head of an area where data is written in the external memory device 2 is transmitted to the control bus, Other ones of the plurality of master devices request reading of data stored after the entry address transmitted to the control bus.

At least one of a plurality of master devices
When at least one of the master devices requests data writing to the external memory device 2, the end address indicating the end of the area where data is written in the external memory device 2 is transmitted to the control bus, and the One requests data writing from the address next to the end address transmitted to the control bus.

(C) In the third embodiment, a memory address server that performs integrated management of the use status of the external memory device 2 may be provided. The memory address server is
An external memory device 2 having an address table
It manages the usage status of each memory in a 1Kbit block as the minimum unit. Assuming that there are n blocks in the external memory device 2, the memory size is 1 Kb
It becomes it × n blocks. On the other hand, the address table is 2
The size is bit × n. 2 bits in address table
Indicates the use status of the block in the external memory device 2. Here, if the block in the external memory device 2 is not used, 2 bits in the address table become “00”. If the block is being written, 2 bits in the address table are "01", and if the block has been written, 2 bits in the address table are "10". When a block is unused but its use is reserved, 2 bits in the address table are “11”.

When any master device attempts to request data writing to the external memory device 2, the address of the area whose use status is set to unused is notified to the master device. When data is written to the external memory device 2 according to a request from the device, the usage status corresponding to the area is updated to “written”. At least one of the plurality of master devices
When one or more of the plurality of areas on the external memory device 2 request that the usage status of any one of the plurality of areas be released to unused, the memory address server responds to the request of any of the master devices to request that area. The usage status corresponding to is updated to unused. If each master device issues the access command as described above, the utilization efficiency of the external memory device 2 can be improved.

(D) In the third embodiment, access to the dual port memory 26 may be performed by one master device. In the present embodiment, when reading data from the external memory device 2, the master device 4 performs data reading from the area allocated to itself in the external memory device 2 to the dual port memory 26, and also executes the master device 5 to the master device 5. The data is read from the area assigned to No. 6 to the dual port memory 26. By such data reading, all the data of the master device 4 to the master device 6 have been read onto the dual port memory 26. Master device 5 to Master device 6
Acquires the data read from the external memory device 2 by performing a DMA transfer from the area indicated by the entry information to the local memory 8 to the local memory 9 of the device.

When writing data to the external memory device 2, the master device 4 writes data from the local memory 7 to the area assigned to itself in the dual port memory 26, and at the same time, the master device 4 on the dual port memory 26. The entry information about the fifth to the master device 6 is notified to the master device 5 to the master device 6. Thereafter, the master device 4 shifts from the area where the data for the master device 4 to the master device 6 is written in the dual port memory 26 to the area allocated for the master device 4 to the master device 6 in the external memory device 2. Performs a DMA transfer. As a result, data for the master device 4 to the master device 6 is written to the external memory device 2.

As described above, the data processing apparatus according to the present invention has two points.
A memo that is connected to a memory device at one point
Rivas, each with two or more points
Each master device at one or more of these points
Connected to multiple local buses and memory devices
Data read and memory device
Write data, and on each local bus,
Data transfer at the transfer rate required by the data device
Transfer on the memory bus
A transfer controller for performing data transfer at a rate,
The other point of the memory bus and each local bus
Having multiple buffers connected at one point,
Transfer rate difference between memory bus and local bus
Multiple locals that input and output data to absorb
Buffer means, and each local buffer means
Have the same configuration, and connect local buses with different bit widths.
A data processing device;
Synchronous clock signal with an operating frequency different from the operating frequency of
And the data processing device further comprises one port.
Read / write the memory device via the memory bus
Port and the other port is
Connected to the local buffer means
Frequency and operating frequency inside the data processor
In order to absorb the difference from the wave number, the memory bus and multiple rows
Dual for inputting and outputting data to and from the cull buffer
If the designer wants to change the bandwidth to be allocated to each master device, it is only necessary to change the transfer rate required by the local bus, so there is no need to redesign the entire data processing device. Absent. Since it is possible to change the allocation of the bandwidth to each master device without changing the memory device-local bus side, it is necessary to change the bandwidth for any part of the data processing device in the future. However, the designer does not pay much effort. Specifically, the data processing device according to the present invention is an MPEG stream decoding device.
If it is instructed to convert the MPEG stream decoding device to another device such as a receiving device for digital satellite broadcasting or the like, a plurality of master devices and a plurality of local buses may be redesigned, and a memory device and a local bus may be used. No modifications need to be made to the side. Regardless of how the bit width is assigned to each master device, this change may be made for multiple local buses, and there is no need to change the memory control for the same memory device before and after the bit width change. Bandwidth allocation change to the master device can be easily performed.

[0160]

[0161] it is possible to realize the asynchronous control of the data transfer between Matame memory device and the internal memory, a memory device and a data processing unit and each may be operated at a unique operating frequency. Therefore, when the operating frequency at which the performance of the memory device can be maximized is different from the optimal operating frequency for the data processing device, the memory device and the data processing device can be operated at the optimal operating frequency.

[0162]

[0163]

[0164]

[Brief description of the drawings]

FIG. 1 is a diagram supposing a case where a data processing device, which is a one-chip LSI, is assembled and used in a multimedia-related product together with an external memory device 2.

FIG. 2 illustrates a first embodiment of a data processing device.

FIG. 3 is a timing chart showing data transfer between an external memory device 2 and a bus 1;

FIG. 4 shows a case where a local buffer 13 is an external memory device 2.
5 is a timing chart showing the operation timing when data is written to the memory.

FIG. 5 shows a case where the local buffer 13 is an external memory device 2.
5 is a timing chart showing operation timings when data is read from a memory.

FIG. 6 shows that the local buffer 14 is an external memory device 2
Is a timing chart showing the operation timing when writing data to the memory.

FIG. 7 shows a case where the local buffer 14 is an external memory device 2.
5 is a timing chart showing operation timings when data is read from a memory.

FIG. 8 shows local buffers 13 to 15
FIG. 3 is a diagram showing a configuration in a case where a circuit provided between a bus and a bus 10 to a bus 12 is shared.

9 (a) Among the selectors shown in FIG. 8, 32 bit buffers 61 to 32 bit buffers 64 to 32 bit buses 57 to 32 bi
FIG. 3 is a diagram illustrating only those used at the time of reading to the t bus. (B) 32 bit buses 57 to 32b among the selectors shown in FIG.
32 bit buffer 61 to 32 bit buffer 64 from it bus 60
FIG. 3 is a diagram illustrating only those used at the time of writing data into the memory.

10A is a diagram showing the correspondence between the bit width of the bus 10 and the connection lines selected by the 4-input / 1-output selector 65 to the gate 68. FIG. (B) is a diagram illustrating which connection line is selected and output by the selectors 71 to 74 in a combination of the bit width of the bus 10 and the connection lines to which the first to fourth data are transferred.

FIG. 11A is a timing chart when the transfer rate is 32 bits. (B) A timing chart when the transfer rate is 64 bits. (C) is a timing chart when the transfer rate is 128 bits.

FIG. 12A is a timing chart when the transfer rate is 32 bits. (B) A timing chart when the transfer rate is 64 bits. (C) is a timing chart when the transfer rate is 128 bits.

FIG. 13 is a diagram showing a data processing device in which a plurality of master devices are provided on a bus 10.

FIG. 14 is a diagram showing a data processing device provided with a dual port memory 26;

FIG. 15 is a diagram illustrating a configuration of a data processing device according to a fourth embodiment.

FIG. 16 is a diagram illustrating an example of a current state bit string.

FIG. 17 is a diagram illustrating a configuration of a data processing device according to a fifth embodiment.

FIG. 18 is a diagram illustrating a configuration of a data processing device according to a sixth embodiment.

FIG. 19 is a diagram illustrating a configuration of an arbiter 112 according to a seventh embodiment.

FIG. 20 is a diagram illustrating an example of a case where identification information x on a master device x is stored in m registers among the n registers.

FIG. 21 is an external memory device 2 according to the eighth embodiment.
FIG. 6 is a diagram showing memory allocation of a.

FIG. 22 is a diagram showing an internal configuration of a data processing device according to a ninth embodiment.

FIG. 23 is a diagram illustrating an internal configuration of a data processing apparatus in which a connection relationship between a dual port memory 100 and a master device is omitted.

FIG. 24 is a diagram showing how priorities are set for a plurality of master devices.

FIG. 25 is a diagram showing a configuration of an entry area in the ninth embodiment.

FIG. 26 (a) is a diagram illustrating bit assignment of a memory cell when 1 byte = signed 8 bits is set. (B) is a diagram illustrating bit assignment of a memory cell when 1 byte is set to 8 bits without a sign.

FIG. 27 is a diagram showing how the external memory device 2 is written when a mask bit is set.

FIG. 28 is a dual-port memory 100 shown in FIG.
FIG. 8 is a diagram showing data to be stored in a tag area of FIG.

FIG. 29 is a configuration diagram illustrating a DMA transfer system that performs general DMA transfer.

FIG. 30 is a diagram illustrating an example of a bandwidth allocation technique realized by bit width division;

[Explanation of symbols]

 1 Bus 2 Memory Device 3 Memory Controller 4 DMA Master 5 DMA Master 6 DMA Master 7 Local Memory 8 Local Memory 9 Local Memory 10 Bus 11 Bus 12 Bus 13 Buffer 14 Buffer 15 Buffer 16 Arbiter 17-19 Memory I / F Controller 20- 22 Connection Circuit 24 DMA Master 25 Arbiter 26 Dual Port Memory 27 Control Bus 28 Memory Entry Server 100 Dual Port Memory 101 Data Unit 102 Tag Unit 103-105 Master Device 106-108 Local Buffer 109-111 Local Controller 112 Arbiter 113 Entry Controller 114 Read request queue 115 Write request queue 116 Memory controller 117 Read Rate queue 118-120 Read acknowledgment queue 121, 122 Address selection circuit 123-125 Entry area table 126 DMA controller 198 Encoded stream buffer area 199 Image frame area 201 Stream unit 202 I / O buffer 203 Setup processor 204 Bit stream FIFO 205 VLD 206 TE 207 POUA 208 POUB 209 POUC 210 Audio unit 211 I / O processor 212 VBM 213 Video unit 214 HOST unit 215 RE 216 FILTER

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Tetsuji Mochida 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-7-334564 (JP, A) JP-A-61-36859 (JP, A) JP-A-2-2455862 (JP, A) JP-A 8-241186 (JP, A) JP-A-4-15735 (JP, A) JP-A-9-146872 (JP, A) JP-A-11-126182 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 12/00-12/06 G06F 13/16-13/18 G06F 13/28-13/378

Claims (3)

(57) [Claims] 1. A data processing device connected to a plurality of master devices and one memory device for transferring data between the memory device and each master device, the data processing device having two points. A memory bus connected to a memory device at one of the points, each of which has two or more points, one of which
Performs multiple local buses connected to each master device at one or more points, reads data from the memory device, and writes data to the memory device. On each local bus, the transfer rate requested by each master device is A transfer controller that transfers data at a transfer rate required by the memory device on the memory bus, the other point of the memory bus, and each local bus.
Having multiple buffers connected at one point,
In order to absorb the difference in transfer rate between the memory bus and the local bus, a plurality of local buffer means for inputting / outputting data are provided. Each of the local buffer means has the same configuration, and has different bit widths. A local bus can be connected, a synchronous clock signal having an operating frequency different from the operating frequency of the data processing device is supplied to the memory device, and the data processing device further has one port connected to the memory device via the memory bus. Memory device
Connected to the read / write port of the
Connected to multiple local buffer means,
Operating frequency in the device and inside the data processing device
Memory bus so as to absorb the difference between
Input / output data to / from local buffer means
A data processing device comprising a dual port memory device . 2. The transfer controller further controls a plurality of master devices being transferred on a memory bus to take in a plurality of data requested to be read out into a dual port memory device and output the data to a local buffer means. The data processing device according to claim 1, wherein: 3. The transfer controller according to claim 2, further comprising: when the data requested by the plurality of master devices to be written to the memory device is output from the local buffer means, fetches the plurality of data into the dual port memory device; after storing the device, the data processing apparatus according to claim 1, wherein the controlling the dual port memory device so as to output the accumulated data to the memory bus.