JPH08314793A - Memory access control method and semiconductor integrated circuit and image decoding device using this method - Google Patents

Abstract

PURPOSE: To constitute an image decoding device with a minimum memory capacity by properly changing the priorities of plural memory access requests in accordance with then state and performing arbitration or the like of memory access in accordance with these priorities to eliminate an unnecessary capacity due to memory division. CONSTITUTION: This image decoding device decodes code data obtained by image compression to obtain the image data and is provided with a processing circuit 1, which processes data in a first form to data in a second form, and a memory 4 where both of data in the first form and data in the second form are stored in a time-division manner. A memory control circuit 2 changes priorities of memory access requests for data in the first form and data in the second form in accordance with then state and arbitrates and schedules the memory access in accordance with these changed priorities. Thus, concentration to specific memory access, the occurrence of a term of invalidation, etc., are prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control method, a semiconductor integrated circuit and an image decoding apparatus to which the method is applied, and more particularly, a semiconductor integrated circuit and an image for decoding encoded image data and displaying it. The present invention relates to a decoding device. 2. Description of the Related Art In recent years, multimedia equipment that processes all data such as video, audio, and characters as digital signals has been receiving much attention. In particular, video (image data) has an enormous amount of data compared to characters and voice, so color moving picture compression and decompression technology (encoding and decoding technology) is essential for multimedia. Has become.

By the way, in order to decode an image, a high-performance and large-capacity memory is required, and two systems of data, code data and image data, must be stored and managed. Therefore,
It is desired to provide a semiconductor integrated circuit and an image decoding device that can store code data and image data in one memory and reduce the amount of required memory.

[0003]

2. Description of the Related Art A conventional image decoding apparatus prepares separate memories for coded data (coded data that has been image-compressed) and image data (image data obtained by decoding coded data), or has a high-speed memory device. It has been proposed to connect the two in parallel to secure a high memory bandwidth (data transfer capability) and share the code data and image data memories in a time division manner. Furthermore, as a conventional image decoding device, it is considered to insert a buffer memory having a large capacity between a memory and an image decoding LSI (semiconductor integrated circuit).

These conventional image decoding devices (image decoding L
SI) causes an increase in the required number of memory devices and an increase in operating frequency, which is also a factor that complicates the image decoding apparatus.

[0005]

As described above, conventionally, the coded data of an image that has been image-compressed and coded is:
Even if the average code data amount is suppressed to be small, there is a feature that a large amount of code data is temporarily consumed depending on the content of the image. Therefore, even in the memory for code data, a high memory bandwidth corresponding to the maximum consumption amount of code data is required. In particular, when the resolution of an image to be decoded is increased to improve the image quality, the demand for memory bandwidth for code data and image data becomes strict, which is a major factor for increasing the circuit scale.

In view of the problems of the conventional image decoding device and the semiconductor integrated circuit described above, the present invention suppresses an increase in the circuit scale such as the capacity of the buffer memory and the memory bus width and an increase in the operating frequency, and is efficient. The purpose is to realize a memory system.

[0007]

According to the first aspect of the present invention, a plurality of accesses to the memory 4 are changed in priority order of each access according to a state at that time, and the changed priority order is set. There is provided a memory access control method characterized by performing arbitration and scheduling of memory access according to the above to prevent concentration of a specific memory access and occurrence of an invalid period.

Here, the memory 4 is a volatile semiconductor memory device that requires a refresh process, and the volatile semiconductor memory device is shared by data of different formats in a time division manner. Then, according to the first aspect of the present invention, arbitration and scheduling of memory access in the writing and reading processing of the data of each format and the refresh processing are performed, and concentration of specific memory access and invalid period are performed. Occurrences are prevented.

FIG. 1 is a block diagram schematically showing a main configuration of an image decoding apparatus according to the present invention. As shown in FIG. 1, according to a second aspect of the present invention, an image decoding apparatus for decoding image-compressed coded data to obtain image data, which processes data of the first format, A data processing circuit 1 for obtaining data in the second format, a memory 4 for storing both the data in the first format and the data in the second format in a time division manner, and the data in the first format and A memory control circuit 2 for changing the priority of the memory access request by the data of the second format according to the state at that time, and arbitrating and scheduling the memory access according to the changed priority. There is provided an image decoding device characterized by preventing concentration on a specific memory access and occurrence of an invalid period.

FIG. 2 is a block diagram schematically showing the structure of a main part of a semiconductor integrated circuit according to the present invention. 1 and 2
According to the third aspect of the present invention, as shown in FIG.
A data processing circuit 1 for processing data of the second format to obtain data of the second format, and a memory 4 for time-divisionally storing both the data of the first format and the data of the second format. However, the priority of the memory access request by the data of the first format and the data of the second format is changed according to the state at that time, and the arbitration and scheduling of the memory access are performed according to the changed priority. And a memory control circuit (2) for performing the semiconductor integrated circuit.

Specifically, the first format data is image-compressed code data, the second format data is image data obtained by decoding the code data, and
The data processing circuit 1 is a decoding circuit for decoding the image-compressed code data to obtain the image data.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION According to the memory access control method of the first embodiment of the present invention, in a plurality of accesses to the memory 4, the priorities of the accesses are changed according to the state at that time, and the changes are made. Arbitration and scheduling of memory access are performed according to the priority order. That is, the refresh process of the memory 4 configured by the volatile semiconductor memory device, and the write and read processes of data of different formats that share the volatile semiconductor memory device in a time-sharing manner, access priority is given in each state. The order is changed, and memory access is arbitrated and scheduled.

As a result, it is possible to realize an efficient memory system while suppressing an increase in circuit scale such as the capacity of the buffer memory and the memory bus width and an increase in operating frequency. In FIG. 1, the image decoding apparatus is, for example, an MPEG-2 (Moving Picture Experts Group-
It shows an image decoding device that decodes coded data compressed according to the standard 2), extracts image data, and outputs display data. Here, reference numeral 1 is a decoding circuit (data processing circuit), 2 is a memory control circuit, 3 is a display circuit, and 4 is a memory (dynamic random access memory).
Memory: DRAM) is shown.

As shown in FIG. 1, a memory (volatile semiconductor integrated circuit: DRAM, for example) 4 is time-divisionally shared (shared) by code data and image data. That is, as indicated by the reference symbol A, first, the supplied code data (image compressed code data: write code data A) is stored in the memory control circuit 2.
Is written in the memory 4 via. Further, the code data (write code data) A written in the memory 4 is
As indicated by the reference code B, it is read from the memory 4 and supplied as read code data B to the decoding circuit 1 via the memory control circuit 2. The decoding circuit 1 decodes the read code data B and outputs image data (expanded image data C). At this time, as will be described later,
For example, the read code data B is decoded with reference to the previous image data (for example, the image data of the immediately preceding field or frame).

Next, as indicated by the reference code C, the image data decoded by the decoding circuit 1 (write image data C) is the same as the code data was written through the memory control circuit 2. It is written in the memory 4. The image data (write image data) C written in the memory 4 is stored in the memory 4 as indicated by reference numeral E.
Read image data E is supplied to the display circuit 3 via the memory control circuit 2. Note that, as described above, among the image data C written in the memory 4, the previously read image data (or a part D of the previous image data) is the predicted reference image, as indicated by reference numeral D. The data D is read from the memory 4 and supplied to the decoding circuit 1 via the memory control circuit 2. Then, in the decoding circuit 1, it is used for decoding (decompression) processing of the read code data B.

As described above, the memory 4 is time-divisionally shared by code data (A, B) and image data (C, D, E) having different formats. here,
The memory (DRAM) 4 needs refresh processing in order to hold the stored contents. And memory 4
In the access (R) for the code data and the image data to the memory, and the access (R) for the refresh processing of the memory 4, the memory control circuit 2 accepts the memory access request (access request signal) and the corresponding access response (access It is designed to be performed in a time-sharing manner by returning a permission signal).

As described above, according to the memory access control method of the first embodiment of the present invention, the memory access is effectively performed by performing the memory access as follows, and the minimum necessary amount is used. Enables image decoding with memory capacity. Memory access is divided for each processing unit, and variable-length access control is performed to access only the required amount of data.

Memory access is arbitrated and scheduled according to its priority. The priority is not fixed but is changed according to the situation to prevent concentration or exclusion of a specific memory access and generation of an invalid period. The read priority of code data is set higher than that of other memory accesses.

Here, according to the first aspect of the present invention, the processing unit of memory access is reduced and the priority of the memory access of code data is increased, so that code data can be read at high speed. Is possible. In addition, since the average memory consumption per hour for compressed code data is naturally smaller than that for decompressed image data, the time ratio of memory access for code data to the whole is small. Get smaller.

Further, according to the first aspect of the present invention, the arbitration of access rights is changed (variable) according to the situation, not the fixed priority order but the memory access priority order that does not require urgent processing. As a result, it is possible to prevent the memory accesses from being concentrated in a specific period and being wasted in other periods, and the memory accesses to the items of low priority from being waited for a long period of time and being prevented from proceeding further. And, for example,
It is possible to reduce the fluctuation range of memory access for the worst case in which high-speed moving image processing that requires a large amount of data continues.

Here, since the consumption amount of code data is limited to a certain amount or less at the time of encoding, the maximum amount of memory access per image of the code data can be predicted. Similarly, the maximum amount of memory access for image data can be predicted by the image size and image format.
Then, by determining the maximum amount of memory access per image, it is possible to guarantee that the decoding operation is completed within a certain period of time of the image, usually within the display cycle. Therefore, it is possible to share the memory for image data and code data without significantly increasing the memory bandwidth.

As described above, FIG. 2 shows the essential structure of the semiconductor integrated circuit of the present invention.
An example of application to a semiconductor integrated circuit for image decoding conforming to the G-2 system is shown. Further, FIG. 3 is a diagram for explaining a characteristic operation in the image decoding apparatus which is the second embodiment of the present invention. As shown in FIG. 2, as the memory 4, a general-purpose DRAM (for example, a 4-Mbit DRAM 4
, Or 8) to operate in the high-speed page mode with the data bus width of 64 bits.
A memory bandwidth of about 1 Gbit / sec is ensured. This is a sufficient memory bandwidth as an average value for decoding an MPEG-2 system MP / ML (main profile / main level) image.

The problem here is the memory bandwidth required in the case of accidentally overlapping bad conditions, that is, in the worst case, which is the basic unit for decoding an image in the MPEG-2 system. Time is required for internal processing of an MB (macro block) having a size of 16 × 16 pixels. Therefore, as indicated by time T1 shown in FIG.
Since there is the minimum cycle (for example, 24 μsec.) Of memory access for writing the decoded image and reading the reference image, there is a possibility that an invalid period T2 in which no memory access is performed as shown in FIG. 3 occurs. .

Therefore, in the image decoding apparatus of the second aspect and the semiconductor integrated circuit of the third aspect according to the present invention, memory access that does not require an emergency, such as DRAM refresh processing (R) and code data writing processing, is performed. , The priority order of each memory access request is changed according to the state at that time so as to be executed between the reference image reading process and the decoded image writing process (time period T2 in FIG. 3), and according to the changed priority order. Memory access arbitration and scheduling. Specifically, the adaptive scheduling includes code data write processing (write code data A write processing), code data read processing (read code data B read processing),
Decoding image writing process (writing image data C writing process), reference image reading process (prediction reference image data D reading process in FIG. 1), display image reading process (reading image data E in FIG. 1) 6 of read processing) and DRAM refresh processing (R)
The priority of one memory access (A to E and R),
It is realized by changing each time according to the state at that time (for example, the contents of the memory access performed immediately before).

Specifically, in the present invention, first, the read processing of code data requires a high read speed temporarily, and therefore the memory access is given the highest priority. Further, in order to reduce the period of waiting for memory access, the reference image reading process is divided into a plurality of processes. In the MPEG-2 system, a plurality of parts (positions, positions,
Since the memory access is performed separately for each rectangular (quadrangular) area, the period for occupying the memory access is shortened because the memory access is referred to.

Next, the coded data requires a high reading speed temporarily depending on the content of the image to be decoded, but is averaged within one screen (one field or one frame) and consumed in that image. If the code amount can be read,
Image decoding can be completed. Therefore, when a high code data read speed is required, the memory access priority is set to prioritize the reference image read processing and the decoded image write processing, and the memory access to the image data is temporarily performed. I have to wait.

Here, the maximum amount of code data consumed for decoding one screen is determined by the bit rate defined in the MPEG-2 system and the size of the receiving buffer. Therefore, the sum of the periods in which the memory access to the image data is temporarily waited is obtained, and it is guaranteed that the decoding operation for one screen is completed within the display cycle.

As described above, the code data and the image data are not required even if a memory having a memory bandwidth obtained by adding the memory bandwidth required for the code data alone and the memory bandwidth required for the image data alone is prepared. This makes it possible to share and use the memory (4). As described above, according to the present invention, it is possible to realize an efficient memory system by suppressing an increase in the circuit scale such as the capacity of the buffer memory and the memory bus width and an increase in the operating frequency.

[0029]

Embodiments of an image decoding apparatus and a semiconductor integrated circuit according to the present invention will be described below with reference to the drawings. FIG. 4 is a block diagram showing an embodiment of the image decoding apparatus of the present invention. In the figure, reference numeral 200 is an image decoding circuit, 201 is a demodulation circuit, 202 is a demultiplexer, 203 is a voice decoding circuit, 2
Reference numeral 04 is a host processor, 205 is a graphic circuit, and 206 is a video encoder.

The demodulation circuit 201 is a circuit for obtaining bit stream data, and is a circuit for inputting bit stream data (video) from a signal input to the image decoding device, for example, a signal of a digital satellite broadcast, a cable television, a digital video disk or the like. , Audio, and data in which other signals are multiplexed) are demodulated. In addition, the demultiplexer 202 has audio and video code data of 1
Since it is multiplexed as one data (bit stream), it is separated into an audio (voice) signal and a video (image) signal. Here, for example, in MPEG, "MPEG-
The system is defined as "System".

The voice decoding circuit 203 is for audio (voice).
Is decoded into audio data (voice data). For example, in MPEG, the system is determined as "MPEG-Audio". This part is, for example, a DSP (Digital Signal Processo).
r). Image decoding circuit 200
Is for decoding bitstream data of video (video: image) and converting it to a video signal (video signal).
For example, in MPEG, the system is determined as "MPEG-Video". The image decoding circuit 200 includes, for example, an LSI (semiconductor integrated circuit 100) for a video decoder and a D
It is configured by a RAM (nonvolatile semiconductor memory device 4). The semiconductor integrated circuit (100) of the present invention corresponds to an LSI for a video decoder in the image decoding circuit 200.

The video encoder 206 has an image decoding circuit 20.
In order to display the digital representation of the video signal of 0 output on a general television set, NTSC (Nati
onalTelevision System Committee) method, or PA
Converts to an L (Phase Alternation by Line) type video signal. Further, the host processor 204 is a processor for controlling the entire image decoding device (decoder device). For example, in order to realize an advanced service such as VOD (Video On Demand), for example, 32 bits to 64 bits. High performance CPU is used. The graphic circuit 205 is a circuit for displaying a graphic screen such as program information and a menu screen.

FIG. 5 is a block diagram showing the configuration of an image decoding circuit as an embodiment of the semiconductor integrated circuit of the present invention.
In the figure, reference numeral 10 is a code data input control unit,
11 is a variable length decoding processing unit, 12 is an inverse quantization processing unit, 13
Is an inverse DCT converter, 14 is a predictive image adding circuit, 15 is a motion vector reproducing circuit, 16 is an input buffer, 17 is a code buffer, 18 is a predictive image buffer, 1
Reference numeral 9 is a decoded image buffer, and 20 is an image memory switching control circuit. Further, reference numeral 21 is a memory access arbitration circuit, 22 is an external DRAM control circuit, 23 is a FIFO memory management unit, 24 is an image memory address conversion unit, 31 is a display control unit, and 3
Reference numeral 2 indicates a display image buffer. Here, the image decoding circuit 200 includes an image decoding LSI 200 and a memory (DR
AM) 4 is provided.

As is clear from the comparison between FIG. 1 and FIG.
The decoding circuit (data processing circuit) 1 includes a code data input control unit 10, a variable length decoding processing unit 11, an inverse quantization processing unit 12,
Inverse DCT transform unit 13, predicted image addition circuit 14, motion vector reproduction circuit 15, input buffer 16, code buffer 1
7, a predicted image buffer 18, a decoded image buffer 19, and an image memory switching control circuit 20.

The code data input control unit 10 inputs a bit stream of code data, detects header data as necessary, discards unnecessary data and detects the beginning of a picture (picture header). Further, the variable length decoding processing unit 11 performs decoding (decoding) of a variable length code (Huffman code) included in the bit stream to convert it into a fixed length code and extracts various parameter values. Has become. Further, the inverse quantization processing unit 12
Converts the data (coefficient data) related to the image from the code data converted into the fixed length, and extracts the inverse DCT conversion data. Here, the inverse quantization means D at the time of encoding.
This corresponds to the process of quantizing the real number data resulting from the CT operation (dividing and rounding it to an integer value) to return it to a real value close to the original value.

The motion vector reproducing circuit 15 extracts a motion vector from the output of the inverse quantization processing unit 12,
In MPEG-2, in order to improve the efficiency of image compression, the contents of the image before that are referred to and the difference is used. Here, the information indicating the position of the image to be referred to is referred to as a motion vector, and the reference image is read using this motion vector.

The inverse DCT transform unit 13 performs an inverse transform of the discrete cosine transform (DCT). The DCT transform is performed at the time of encoding, and the coordinate axes of the 8 × 8 matrix are frequency-transformed by orthogonal transform. It is converted into a component and the inverse conversion is performed to return it to pixel data. Where DC
The operation of T-transform is mainly performed by matrix multiplication, and the inverse transform is referred to as IDCT (Inverse Discrete Cosin).
abbreviated as e Transform).

The predicted image addition circuit 14 adds the contents of the reference image obtained from the motion vector reproduction circuit to the pixel data obtained by the inverse DCT conversion unit 13 for each pixel as necessary, and finally Generate a decoded image. The image memory switching control circuit 20 manages addresses for allocating the decoded image, the reference image, and the display image on the memory (DRAM) 4 provided outside the semiconductor integrated circuit (image decoding LSI) 100. Here, since the decoded image becomes the reference image and the display image in the order of the images, the memory addresses assigned to the images can be switched in order.

As shown in FIGS. 1 and 5, the memory control circuit 2 includes a memory access arbitration circuit 21 and an external DR.
AM control circuit 22, FIFO memory management unit 2
3, and an image memory address conversion unit 24. The memory access arbitration circuit 21 receives each memory access request (for example, an access request corresponding to A to E shown in FIG. 1 and an access request for refresh processing), and arbitrates (arbitration) according to the priority order. I do. External DRAM control circuit 2
Reference numeral 2 controls the memory 4 provided outside the image decoding LSI 100. By operating the signal line of the DRAM 4 to execute memory access, continuous access in the high speed page mode is realized. There is.

The FIFO memory management unit 23 serves as a memory for coded data (bit stream), and uses L for image decoding.
FIFO on the DRAM 4 provided outside the SI 100
(First In First Out) Performs address management (update of write pointer and read pointer) to configure a buffer. The image memory address conversion unit 24 performs address conversion of the decoded image, the reference image and the display image,
The two-dimensional address information of the X-coordinate and the Y-coordinate indicating the position of the image is converted into a linear address indicating the position on the memory, and the address information designated by the image memory switching control circuit 20 is added as an offset value. Then, the address of the image memory is obtained.

As shown in FIGS. 1 and 5, the display circuit 3 includes a display controller 31 and a display image buffer 32. The display control unit 31 is a circuit that displays an image that has already been decoded as a display image, and outputs the display image at the timing of the NTSC system or the PAL system, for example.

Here, the image decoding LSI 100 shown in FIG.
In, each buffer (input buffer 16, code buffer 17, predicted image buffer 18, decoded image buffer 1
9, and the display image buffer 32) is a set of external D
In order to use RAM4 in a time-sharing manner, or external DR
It is a small-capacity buffer memory provided so as to correspond to each memory access in order to absorb the speed difference from AM4.

FIG. 6 is a functional block diagram showing an image decoding circuit 100 'as another embodiment of the semiconductor integrated circuit of the present invention. In FIG. 6, reference numeral 101 is an overall control unit, 102 is an internal clock generation unit, 103 is a host interface unit, and 104.
Is a parameter register unit, 105 is an input data control unit, 106 is a variable length decoding unit, 107 is an inverse quantization unit, 108 is an inverse discrete cosine transform unit, 109 is a filter unit, 110 is an addition unit, and 111 is a video interface unit. Reference numeral 112 denotes a memory control unit. Here, when the image decoding LSI 100 ′ shown in FIG. 6 is made to correspond to the image decoding LSI 100 shown in FIG. 5, the input data control unit 105 of FIG. 6 corresponds to the code data input control unit 10 and the input buffer 16 of FIG. The variable length decoding unit 106 corresponds to the variable length decoding processing unit 11 and the code buffer 17, and the filter unit 109 is the motion vector reproducing circuit 1.
5, prediction image buffer 18 and decoded image buffer 19
It corresponds to. Further, the video interface unit 111 of FIG. 6 corresponds to the display circuit 3 including the display control unit 31 and the display image buffer 32 of FIG. 5, and the memory control unit 112 includes the image memory switching control circuit 20 and the memory access arbitration. Circuit 21, external DRAM control circuit 2
2, corresponding to the FIFO memory management unit 23 and the image memory address conversion unit 24. The inverse quantization unit 107, the inverse discrete cosine transform unit 108, and the addition unit 110 in FIG.
Correspond to the inverse quantization unit 12, the inverse DCT transform unit 13, and the predicted image addition circuit 14 in FIG. 5, respectively.

The overall control unit 101 processes operation control of each block, error recovery, and interrupt to the host CPU. That is, the overall control unit 101 manages the number of pictures in the buffer memory, the picture structure management of the display / decoded image, and the macroblock address / number in synchronization with the display vertical synchronization signal to process the activation of each unit, Time returns according to host settings, and
The host CPU is notified of picture header detection / decoding end, display V-Sync, B-Picture Skip, buffer memory overflow / underflow, and decoding / system error interrupts via the parameter register unit 104.

The internal clock generator 102 has a built-in PLL macro and receives two kinds of clock signals (27/5) with a 27 MHz basic clock signal from the outside of the LSI as an input.
4 MHz) and distribute to each block. The host interface unit 103 has an interface function between different types of CPUs and the image decoding circuit 100 ', and accesses each block as necessary.

The parameter register unit 104 is a host CP.
Initial setting parameters from U, command register, M
The register is composed of registers for various parameters detected from the PEG bit stream. The value of each register is distributed to each internal block, but can be read from the host CPU. FIG. 7 is a diagram for explaining the operation of one embodiment (the image decoding LSI of FIG. 5) of the image decoding circuit according to the present invention.
9 illustrates an operation example of an image decoding LSI compliant with G-2. Note that in MPEG-2, reference image data may be read from different positions of different images, and reading is performed by dividing it into a maximum of four rectangles. In addition, reading the reference image by dividing it into luminance and color difference information is 4 × 2 = 8.
It can also be done in batches.

In FIG. 7, reference symbols A to E indicate the respective processes described with reference to FIG. 1, and reference symbol R indicates D.
The refresh process of the RAM 4 is shown. That is,
Reference numerals A to E correspond to the processes shown in Table 1 below.

[0048]

[Table 1]

As shown in FIG. 7, the read processing B of the code data and the read processing R of the display image are fixed to a high priority, so that the access request is accepted when the access request is generated. . Figure 7 (a)
Shows an example of an actual memory access. In the processing of one macroblock shown in FIG. 7B, the read processing B of code data is inserted in INS1 during the write processing C of the decoded image and the read processing D of the reference image. ,Also,
This shows a case where the code data read process B and the display image read process E are inserted in the INS2 during the two reference image read processes D.

As shown in FIG. 7 (c), processing of one macroblock requires internal processing time, and also processing time for filtering the reference image data. Therefore, the period until the longer of these two processing times ends, that is, "//////" in Fig. 7 (c)
Period is required, and if no memory access request occurs during this period, the period "///////" becomes an invalid cycle.

In the present invention, in order to suppress the occurrence of the above-mentioned invalid cycle, the writing process A and the refreshing process R of the code data having a margin in the access cycle are performed by the reading process D of the reference image and the writing process C of the decoded image. The priority is decided (changed as appropriate) so that it is performed in the period between. At this time, for example, if the priority order of the code data write process A and the refresh process R is fixed to be higher than the reference image read process D and the decoded image write process C, the read process D between the plurality of reference images may be performed. It comes in and the filtering processing time is extended backward. On the other hand, if the priority of the code data writing process A and the refresh process R is fixed lower than the reference image reading process D and the decoded image writing process C, the display image reading process E or the code data reading process B is performed. When a memory access with a higher priority is entered, the memory access of the read process D of the next reference image and the read process B of the code data occurs, and the memory access of the write process A of the code data and the refresh process R is performed. It will be held for a long time.

Therefore, in the present invention, as described above, the priority order of a plurality of accesses to the memory (4) is changed according to the state at that time. FIG. 8 is a block diagram showing an example of a memory access arbitration circuit in the image decoding LSI of FIG. As shown in the figure, the memory access arbitration circuit 21 includes a priority encoder to which access request signals (A to E, R) are input.
211, an access permission register 212 that outputs access permission signals (A to E, R), a feedback register 213, and a memory access end detection unit 214 that detects the end of memory access.

As shown in FIG. 8, the access request signal (A to E, R) is encoded by the priority encoder 211 to obtain the next memory access candidate.
The encoding process in the priority encoder 211 is always performed, and the one having the highest priority (priority) at that time is a candidate for the next memory access.

Further, the status of memory access is judged from the access request signal, and the candidates at the time when the memory access is completed (or when the memory access is not performed) are held in the access permission register 212. This time,
The candidate at the time when the memory access is completed is the reference image reading process D, the code data writing process A, or
If it is one of the refresh processes R, the candidate at the time when the memory access is completed is also held in the feedback register 213.

Further, the content of the feedback register 213 is fed back to the priority encoder 211 as a priority change signal, and the priority order of the access request signals (A to E, R) is changed. And
The access permission signals (A to E, R) whose priorities are changed according to the state at that time become the next candidates and are output from the access permission register 212.

FIG. 9 is a timing chart showing the operation of the memory access arbitration circuit of the present invention, and FIG. 10 is an access request signal in the memory access arbitration circuit of the present invention.
7 is a timing chart showing the relationship between an access permission signal and an access signal. As shown in FIG. 9, code data write processing A, code data read processing B,
In response to the access request for the decrypted image writing process C, the reference image reading process D, the display image reading process E, and the refresh process R, the access permission signals (AE, A to E, according to the above-described priority change). R) is output, and memory access is performed according to the access signal.

Specifically, referring to FIG. 10, the relationship between the access request signal, the access permission signal, and the access signal in the memory access arbitration circuit will be described by taking the code data read process B and the reference image read process D as an example. . As shown in FIG. 10, first, the access request signal of the code data read process B is output (high level).
H ”), and then when the access request signal of the reference image read process D is output, the code data read process B outputs the access request signal until the access permission signal is output, as indicated by P1. Is retained.
Here, also in the reference image reading process D, the output of the access request signal is held until the access permission signal is output.

Next, as indicated by P2, the memory access arbitration circuit (21) outputs an access permission signal (high level "H") to the access request signal having the highest priority at that time. It In the example of FIG. 10, the access permission signal is output in response to the access request signal of the code data read process B. Then, as indicated by P3, the access request signal of the code data read process B is withdrawn (low level “L”) after confirming the access permission signal for itself (B). Furthermore, P4
As shown by, the circuit receiving the access permission signal of the read processing B of the code data output at P2 outputs the access signal (high level “H”) and the memory access (read processing B of the code data) is performed. Be started.

Further, as indicated by P5, when the necessary memory access (code data read processing B) is completed, the access signal is canceled (low level).
Further, the access permission signal is withdrawn (low level) by detecting that the access signal has been withdrawn (end of memory access) and resetting the access permission register as indicated by P6.
L ″). At this point, all access permission signals are once reset.

Then, as indicated by P7, the memory access arbitration circuit detects a state in which no access permission signal is output, and sets the encoding result of the priority encoder in the access permission register. As a result, as shown by P7, the access permission signal is output for the access request signal having the highest priority at that time. In the example of FIG. 10, the access permission signal is output in response to the access request signal of the reference image reading process D. Further, as indicated by P8, the circuit that receives the access permission signal of the reference image read process D output in P7 outputs an access signal and the memory access (reference image read process D) is started.

FIG. 11 is a diagram showing the logical configuration of the priority encoder in the memory access arbitration circuit (21) of the present invention. FIG. 11 (a) shows the fixed priority encoder circuit PE, and FIG. 11 (b) shows The logical expression of an example which comprises the fixed priority encoder circuit PE is shown. In the logical expression of FIG. 11 (b), the symbol "^" indicates logical inversion (NOT), and the symbol "&"
Indicates a logical product (AND).

The fixed priority encoder circuit PE shown in FIG. 11 (a) has input signals (access request signals) A, B,
Output signals a, b, c, d, e, and r according to a predetermined priority order are output to C, D, E, and R. In FIG. 11B, the priority order “B>E>D>A>R>
FIG. 11A shows a logical expression for realizing “C”.
Fixed Priority Encoder Circuit PE of Figure 11 (b)
It is possible to set a predetermined priority order (B>E>D>A>R> C) by configuring a circuit corresponding to the logical expression of.

FIG. 12 is a diagram showing an example of the priority encoder section (priority encoder 211) in the memory access arbitration circuit (21) of the present invention. 12
As shown in FIG. 3, the priority encoder unit includes a plurality of fixed priority encoders PE-1 to PE-n.
(Corresponding to the fixed priority encoder PE in FIG. 11)
Of the fixed priority encoders PE-1 to PE-n, which is composed of a selector circuit SEL and a selector circuit SEL.
The output is selected by L. Specifically, the fixed priority encoder PE-1 has the priority order “B>
“E>D>A>R> C” is set, and the fixed priority encoder PE-n sets the priority order “B>E>C>D>A>.
"R" is set. The fixed-priority encoder PE-1 has the same circuit as the fixed-priority encoder PE shown in FIG. 11, but the fixed-priority encoder PE-n also has the priority "B>".
The circuit corresponds to a logical expression that realizes "E>C>D>A>R".

FIG. 13 is a diagram for explaining a specific example of the priority order changed in each processing state by the memory access arbitration circuit of FIG. In the figure, reference numeral F1
F5 to F5 respectively indicate the access processing performed immediately before, and indicate the priority order of the memory access request in each state. That is, FIG. 13 shows how the memory access arbitration circuit 21 shown in FIG. 8 changes the priority of each memory access request according to the state at that time.

That is, immediately after the reset, in F1, each memory access request is the read process B> of code data.
Display image reading process E> Reference image reading process D
> Code data write process A> memory refresh process R> decoded image write process C, and immediately after the reference image read process D, F2, B> E
>D>A>R> C and its priority is changed. Immediately after the reference image reading process D, F
2, the priority of the reference image reading process D (priority of the memory access request) is set high.
This is because the read processes D of the plurality of reference images are continuously accessed with as little space as possible.

Immediately after the write processing A of the code data F3, the priority order is changed to B>E>R>C>D> A, and further F immediately after the memory refresh processing R.
In 4, the priority order is changed to B>E>C>D>A> R, and immediately after the decoding image writing process C, in F5, B>E>D>A>R> C and the priority order thereof. Is to be changed.

As described above, according to the semiconductor integrated circuit (image decoding LSI) having the memory access arbitration circuit and the image decoding apparatus including the image decoding LSI according to the embodiment of the present invention, a plurality of memory access requests By appropriately changing the priority order according to the state at that time, and performing arbitration and scheduling of memory access according to the changed priority order, the circuit scale such as the capacity of the buffer memory and the memory bus width is increased and the operating frequency is increased. It is possible to suppress an increase in speed and realize an efficient memory system. In particular, the present invention greatly contributes to improving the performance of an image decoding device such as MPEG.

[0068]

As described above in detail, according to the present invention, all the data necessary for the image decoding operation can be stored in one memory, and the waste of the capacity due to the memory division is eliminated. The image decoding device can be configured with the minimum required memory capacity.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing a main part configuration of an image decoding apparatus according to the present invention.

FIG. 2 is a block diagram schematically showing a main part configuration of a semiconductor integrated circuit according to the present invention.

FIG. 3 is a diagram for explaining a characteristic operation in the image decoding device of the present invention.

FIG. 4 is a block diagram showing an embodiment of an image decoding apparatus of the present invention.

FIG. 5 is a block diagram showing a configuration of an image decoding circuit as an example of a semiconductor integrated circuit of the present invention.

FIG. 6 is a functional block diagram showing an image decoding circuit as another embodiment of the semiconductor integrated circuit of the present invention.

FIG. 7 is an image decoding circuit (LS for image decoding according to the present invention.
It is a figure for demonstrating operation | movement in one Example of I).

FIG. 8 is a block diagram showing an example of a memory access arbitration circuit in an embodiment of the image decoding circuit of the present invention.

FIG. 9 is a timing chart showing the operation of the memory access arbitration circuit of the present invention.

FIG. 10 is a timing chart showing a relationship among an access request signal, an access permission signal, and an access signal in the memory access arbitration circuit of the present invention.

FIG. 11 is a diagram showing a logical configuration of a priority encoder in the memory access arbitration circuit of the present invention.

FIG. 12 is a diagram showing an example of a priority encoder unit in the memory access arbitration circuit of the present invention.

FIG. 13 is a diagram for explaining a specific example of the priority order changed in each processing state by the memory access arbitration circuit of the present invention.

[Explanation of symbols]

1 ... Data processing circuit (decoding circuit) 2 ... Memory control circuit 3 ... Display circuit 4 ... Memory (DRAM) 10 ... Code data input control unit 11 ... Variable length decoding processing unit 12 ... Inverse quantization processing unit 13 ... Inverse DCT transform Part 14 ... Predicted image addition circuit 15 ... Motion vector reproduction circuit 16 ... Input buffer 17 ... Code buffer 18 ... Predicted image buffer 19 ... Decoded image buffer 20 ... Image memory switching control circuit 21 ... Memory access arbitration circuit 22 ... External DRAM control circuit 23 ... FIFO memory management unit 24 ... Image memory address conversion unit 31 ... Display control unit 32 ... Display image buffer 100, 100 '... Semiconductor integrated circuit (image decoding LSI) 101 ... Overall control unit 102 ... Internal clock generation unit 103 ... Host interface Unit 104 ... Parameter register unit 105 ... Input data control unit 106 ... Variable Decoding unit 107 ... Inverse quantization unit 108 ... Inverse discrete cosine transform unit 109 ... Filter unit 110 ... Addition unit 111 ... Video interface unit 112 ... Memory control unit 200 ... Image decoding circuit 201 ... Demodulation circuit 202 ... Demultiplexer 203 ... Audio Decoding circuit 204 ... Host processor 205 ... Graphic circuit 206 ... Video encoder 211 ... Priority encoder 212 ... Access permission register 213 ... Feedback register 214 ... Memory access end detection unit A ... Write code data (code data write processing) B ... Read code Data (read processing of coded data) C ... Write image data (write processing of decoded image) D ... Predictive reference image data (read processing of reference image) E ... Read image data (read processing of display image) PE, PE-1 ~ PE-n ... Fixed Priority En Over da circuit R ... refresh processing SEL ... selector circuit of the DRAM

Front page continued (72) Inventor Kimihiko Kazui 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Hideki Miyasaka 1015, Kamedotachu, Nakahara-ku, Kawasaki, Kanagawa Prefecture (72) Inventor Yasunori Ueno 2-3-3 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Fujitsu Digital Technology Stock Company In-house (72) Inventor, Koji Maruyama 3-22-8, Hakataekimae, Hakata-ku, Fukuoka, Fukuoka Fujitsu Kyushu Digital Technology Stock company

Claims (25)

[Claims] 1. A specific memory for a plurality of accesses to a memory, the priority of each access is changed according to the state at that time, and the arbitration and scheduling of the memory access are performed according to the changed priority. A memory access control method, characterized in that concentration of access and the occurrence of invalid periods are prevented. 2. The memory is a storage device that requires refresh processing, and the volatile semiconductor storage device is shared by data of different formats in a time-division manner. 2. The memory access control method according to claim 1, wherein arbitration and scheduling of memory access in refresh processing are performed. 3. The different types of data are image-compressed code data and image data obtained by decoding the code data, and access to the storage device is performed by writing code data, reading code data, and decoding. 3. The memory access control method according to claim 2, further comprising an image writing process, a reference image reading process, a display image reading process, and a storage device refreshing process. 4. A memory access with a sufficient access cycle, such as a refresh process of the storage device and a write process of the code data, is executed between the read process of the reference image and the write process of the decoded image. The memory access control method according to claim 3, wherein 5. The memory access control method according to claim 3, wherein the priority order of the read processing of the code data is set to the highest so as to achieve a high read speed. 6. The read process of the code data is prioritized over the read process of the reference image and the write process of the decoded image to improve the read speed of the code data. Memory access control method. 7. Immediately after reset, immediately after read processing of reference image, or immediately after write processing of decoded image, read processing of code data> read processing of display image> read processing of reference image> write code data 4. The memory access control method according to claim 3, wherein the priority order of the memory access is set so that processing> memory refresh processing> decoded image writing processing is performed. 8. Immediately after the code data write process, the code data read process> display image read process> memory refresh process> decoded image write process> reference image read process> code data write process. 4. The memory access control method according to claim 3, wherein the priority of the memory access is set so that 9. Immediately after the refresh processing of the memory, the read processing of the code data> the read processing of the display image> the write processing of the decoded image> the read processing of the reference image> the write processing of the code data> the refresh processing of the memory. 4. The memory access control method according to claim 3, wherein the priority order of memory access is set as described above. 10. The memory access of the code data and the image data is performed as a variable-length access control in which each memory access is divided into processing units and only a necessary data amount is accessed. The memory access control method according to claim 1, wherein 11. The priority order of each access to the memory is changed according to the content of the memory access performed immediately before.
Memory access control method. 12. An image decoding apparatus for decoding image-compressed coded data to obtain image data, comprising a data processing circuit for processing data of a first format to obtain data of a second format. A memory for storing both the first format data and the second format data, and the priority of memory access requests by the first format data and the second format data is changed, An image decoding device, comprising: a memory control circuit that performs arbitration and scheduling of memory access according to the determined priority order. 13. The memory is a storage device that requires refresh processing, the first format data is image-compressed code data, and the second format data is the code data decoded. Image data, and
13. The image decoding apparatus according to claim 12, wherein the data processing circuit is a decoding circuit that decodes the image-compressed coded data to obtain the image data. 14. The image decoding apparatus according to claim 13, wherein the memory control circuit performs arbitration and scheduling of memory access in the writing and reading processing of the code data and the image data and the refresh processing. 15. Arbitration and scheduling of memory access performed by the memory control circuit includes code data write processing, code data read processing, decoded image write processing, reference image read processing, display image read processing, and , 6 of memory device refresh processing
The image decoding device according to claim 14, wherein the image decoding device is adapted to perform one process. 16. The memory control circuit performs a memory access with a sufficient access cycle, such as a refresh process of the storage device and a write process of the code data, in a read process of the reference image and a write process of the decoded image. 16. The image decoding apparatus according to claim 15, wherein arbitration and scheduling of memory access are performed so as to be executed between them. 17. The memory control circuit sets the priority of the read processing of the code data to the highest priority, and performs arbitration and scheduling of memory access so as to achieve a high read speed. The image decoding device according to claim 15, wherein 18. The memory control circuit prioritizes the read process of the code data over the read process of the reference image and the write process of the decoded image to improve the read speed of the code data. The image decoding apparatus according to claim 15, wherein the image decoding apparatus is configured to perform arbitration and scheduling. 19. The memory control circuit, immediately after reset, immediately after read processing of a reference image, or immediately after write processing of a decoded image, read processing of code data> read processing of display image> read processing of reference image. 16. The image decoding apparatus according to claim 15, wherein arbitration and scheduling of memory access are performed so that a code data write process> a memory refresh process> a decoded image write process is performed. 20. Immediately after the code data write process, the memory control circuit reads the code data> the display image read process> the memory refresh process> the decoded image write process> the reference image read process> the code 16. The image decoding apparatus according to claim 15, wherein arbitration and scheduling of memory access are performed so as to perform a data writing process. 21. Immediately after the storage device refresh process, the memory control circuit reads code data> display image read process> decoded image write process> reference image read process> code data write process> memory 16. The image decoding apparatus according to claim 15, wherein arbitration and scheduling of memory access are performed so as to perform the refresh process of. 22. The priority of the memory access request by the first format data and the second format data is changed according to the content of the memory access performed immediately before. The image decoding device according to claim 12, wherein 23. The image decoding apparatus according to claim 12, further comprising a display circuit which reads out image data stored in the memory and outputs display data. 24. The image decoding apparatus according to claim 12, wherein the data processing circuit and the memory control circuit are integrated on a single chip. 25. A data processing circuit for processing data of the first format to obtain data of the second format, and a memory for storing both the data of the first format and the data of the second format. , A semiconductor product circuit in which a priority of memory access requests of both data is changed, and a memory control circuit which performs arbitration and scheduling of memory access according to the changed priority is integrated.