JPH1118080A - Method and device for decoding dynamic image - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a memory storage capacitance required for performing pan scan display by decoding only the encoded image data, corresponding to the inside of a pan scan area and writing them in a memory based on pan scan information. SOLUTION: While a macro block address shows the outside of the pan scan area, a whole control circuit 12 repeats processing such as supplying a macro block(MB) search starting instruction to a variable length decoding circuit 15, so that the DCT coefficient of the MB outside the pan scan area in a source image is not decoded and is not stored in a decoded data area 132 of a memory 13, either. Furthermore, while the macro block address shows the inside of the pan scan area, the whole control circuit 12 performs ordinary decoding operation. Namely, processing such as supplying an MB header decode starting instruction MBHDI to the variable length decoding circuit 15 is repeated, so that only the pan scan area in the source image is decoded and stored in the decoded data area 132 of the memory 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a moving picture decoding method and apparatus.

[0002]

2. Description of the Related Art In a moving picture decoding apparatus, when decoding a B picture (bidirectional predictive coded picture) coded by the MPEG system, an I picture (internal coded picture) stored in a decoded data area of a memory. Alternatively, two pictures, which are P pictures (forward predictive coded images), are read as reference images, a predicted image is generated, a decoded image is generated by adding the predicted image to the image data output from the inverse DCT circuit, and decoding of the memory is performed. Store in the data area. Then, the B picture is read out from the decoded data area of the memory for display in synchronization with the vertical synchronization signal. For this reason, the decoded data area of the memory includes two frames required for the reference image and
It has a storage capacity of three frames in total, one frame required for buffering B pictures.

[0003] This one frame differs depending on the size of the original image. It is preferable that the storage capacity of the memory be reduced as much as possible to reduce the manufacturing cost of the video decoding device. Therefore, the storage capacity of the memory is determined so that the size of the original image is three frames when the size of the original image is the maximum. In the pan-scan display in which one part of one image is extracted and displayed in an enlarged manner,
Conventionally, after storing decoded image data in a decoded data area of a memory, image data of a pan scan area is cut out from the decoded data area of the memory for display.

[0004]

For this reason, in the case of including image data of the MPEG system and other data such as menu information as in a DVD, the storage capacity is insufficient, and even pan-scan display is impossible. May occur. An object of the present invention is to provide a moving image decoding method and apparatus capable of reducing the memory storage capacity required for performing pan scan display in view of such a problem.

[0005]

According to the first aspect of the present invention, there is provided a method for encoding an image corresponding to a pan scan display area based on pan scan information included in control information separated from encoded image data. Only the image data is decoded and written to the memory. According to this moving picture decoding method, the memory storage capacity required for performing the pan scan display is reduced. For example, the storage capacity of the memory is limited to only the data of the MPEG system, and the storage capacity of the memory is only the data of the MPEG system. When data is included, there is an effect that even if normal display cannot be performed, pan scan display, which could not be performed conventionally, can be performed.

According to a second aspect of the present invention, the encoded image data is decoded, and the decoded image data corresponding to the pan scan display area is determined based on the pan scan information included in the control information separated from the encoded image data. Write only to memory. According to this moving picture decoding method, the above-described effect of the first aspect is obtained, and the control is simpler than that of the first aspect. However, since only the necessary parts need to be decoded in claim 1, claim 1 can perform processing at a higher speed than in case of claim 2.

According to a third aspect of the present invention, there is provided a moving picture decoding apparatus comprising: a memory having a first storage area and a second storage area; a decoding circuit for separating control information from encoded image data and decoding the encoded image data; Coded image data is written to the first area, the coded image data written is read from the first area and supplied to the decoding circuit, and the decoded image data decoded by the decoding circuit is stored in the second storage area. And a memory control circuit for reading out the written decoded image data for display, and a pan scan display area corresponding to the decoded circuit based on the pan scan information included in the separated control information. And a main control circuit for decoding only the decoded image data to be decoded.

According to a fourth aspect of the present invention, there is provided a moving image decoding apparatus comprising: a memory having a first storage area and a second storage area; a decoding circuit for separating control information from encoded image data and decoding the encoded image data; Coded image data is written to the first area, the coded image data written is read from the first area and supplied to the decoding circuit, and the decoded image data decoded by the decoding circuit is stored in the second storage area. And a memory control circuit for reading out the written decoded image data for display, based on the pan scan information included in the separated control information, the memory control circuit in the pan scan display area. A main control circuit for writing only the corresponding decoded image data into the second storage area.

In the moving picture decoding apparatus according to the fifth aspect,
, The decoding circuit converts the encoded image data into m ×
Decoding is performed in units of m pixels, and the main control circuit determines the m of the pan scan display area based on the pan scan information.
A horizontal decoding start point, a horizontal decoding end point, a vertical decoding start point, and a vertical decoding end point are calculated in × m pixel units, and the m × m pixel unit of the encoded image data is calculated based on the control information. Is determined as an encoded image data address, and the encoded image data address is not less than the horizontal decoding start point and not more than the horizontal decoding end point and not less than the vertical decoding start point and not more than the vertical decoding end point. Is performed by the decoding circuit only when

In the moving picture decoding apparatus according to claim 6,
In the above, the encoded image data is image data encoded by the MPEG system, and the unit of m × m pixels is a macro block. According to a seventh aspect of the present invention, in the moving image decoding apparatus according to the sixth aspect, the horizontal decoding start point HS and the vertical decoding start point VS are respectively set to HS = [(OH / 2−Hofs−PH / 2) / 16] VS. = [(OV / 2−Vofs−PV / 2) / 16], where [] is a rounded integer symbol for the numerical value in parentheses, and OH is the number of pixels in the horizontal direction of the original image. Number of pixels in direction Hofs: Number of pixels in the horizontal direction of the center of the pan scan area with respect to the center of the original image Vofs: Number of pixels in the vertical direction of the center of the pan scan area with respect to the center of the original image PH: Number of pixels in the horizontal direction of the pan scan area PV: Vertical of the pan scan area The number of pixels in the direction.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a video decoding device 10 according to an embodiment of the present invention. In this device 10, a video bit stream VBS separated from a multiplex bit stream is supplied to a memory control circuit 11.
The video bit stream VBS is encoded by the MPEG system. Based on the command from the overall control circuit 12, the memory control circuit 11 causes the video bit stream VB
S is temporarily stored in a coded data area 131 as a delay buffer of the memory 13 at a high speed, and the data in this area 131 is read out at a lower speed than at the time of storage.
Is supplied to the variable length decoding circuit 15 as encoded image data DAT0 via

The coded image data DAT0 is converted into quantized DCT coefficients by a variable length decoding circuit 15, then converted into DCT coefficients by an inverse quantization circuit 16, and then converted into image data DAT1 by an inverse DCT circuit 17. Is done. When the image data DAT1 is an I-picture, it passes through the motion compensation predictive decoding circuit 18 and passes through the memory bus 14 and the memory control circuit 11 to the memory 13 as decoded image data DAT2.
Is stored in the decoded data area 132. Image data DA
When T1 is a P picture or a B picture, the reference image data is read from the decoded data area 132 of the memory 13 by the memory control circuit 11 based on the picture coding type and the motion vector separated by the variable length decoding circuit 15. The data is supplied to the motion-compensated predictive decoding circuit 18 as data DAT3, a predicted image is generated from the data DAT3, and the image data DAT1 is added thereto to generate decoded image data DAT2.
4 and stored in the decoded data area 132 of the memory 13 via the memory control circuit 11.

The data in the decoded data area 132 is read out by the memory control circuit 11 in the order of images before encoding, supplied to the image display circuit 19 as display image data DAT4 via the memory bus 14, and subjected to format conversion and image conversion. Enlargement, analog conversion, and the like are performed to generate a video signal VS. In the pan scan display, as shown in FIG. 4, a pan scan setting area 21 which is a part of the original image 20 is cut out and enlarged by the image display circuit 19 in FIG. 1 to obtain a display image 22. The pan scan information is included in the encoded image data DAT0 as a part of the control information. That is, the number of horizontal pixels OH and the number of vertical pixels OV of the original image 20 are included in the sequence header, and the number of horizontal pixels PH and the number of vertical pixels PV of the pan scan setting area 21 are included.
In addition, the offset (Hofs, Vofs) of the center PC (PCX, PCY) of the pan scan area with respect to the center OC (OCX, OCY) of the original image is included in the picture header (extended and user data area).

A horizontal start point hs, a horizontal end point he, and a vertical start point vs of a pixel unit of the pan scan setting area 21 are displayed.
And the vertical decoding end point ve is obtained by the following equation. hs = OH / 2-Hofs-PH / 2 (1) he = OH / 2-Hofs + PH / 2 (2) vs = OV / 2-Vofs-PV / 2 (3) ve = OV / 2−Vofs + PV / 2 (4) In the present embodiment, in the case of the pan scan display, only the pan scan setting area 21 is decoded and stored in the decoded data area 132, so that the memory 13 is required. This is to reduce the storage area. In this case, since the variable length decoding circuit 15, the inverse quantization circuit 16, the inverse DCT circuit 17, and the motion compensation prediction decoding circuit 18 perform data processing in units of macroblocks of 16 × 16 pixels, the pan scan setting area 21 is Is converted into a pan scan area 21A in macroblock units as shown in FIG. 5, and the pan scan area 21A is decoded. The cells separated by dotted lines in FIG. 5 indicate macroblocks.

The horizontal decoding start point HS and the horizontal decoding end point H of each macroblock in the pan scan area 21A
E, vertical decoding start point VS and vertical decoding end point V
E is obtained by the following equation. HS = [hs / 16] (5) HE = [he / 16] (6) VS = [vs / 16] (7) VE = [ve / 16] (( 8) Here, [] is a symbol for converting a numerical value in parentheses to an integer by rounding up the decimal part.

FIG. 2 shows a schematic configuration of a characteristic portion related to the pan scan display in FIG. The presence / absence F of the coded data in the memory is supplied from the memory control circuit 11 to the overall control circuit 12.
Is low level 'L' when the encoded data area 131 is empty, and high level 'H' (decoding enable) otherwise. The following decoding start instruction and MB search instruction are output when the presence / absence F of the coded data in the memory is “H”, and when it is “L”, it is output after being waited for to become “H”.

The overall control circuit 12 outputs a decoded vertical synchronizing signal D
The picture decoding start command PDI is supplied to the variable length decoding circuit 15 in synchronization with VSYNC, and the variable length decoding circuit 15 responds to this by reading out from the coded data area 131 via the memory control circuit 11. Encoded image data DA
The picture header of T0 is decoded, and the obtained control information is supplied to the overall control circuit 12. When the decoding is completed, a picture header decoding completion notification PHDC is supplied to the overall control circuit 12. When the control information is the pan scan information PSI, the pan scan control circuit 121 uses
Based on the above equations (1) to (8), the MB search data HS,
HE, VS and VE are calculated.

When the macroblock address MBADR indicates outside the pan scan area 21A, the overall control circuit 12 issues an MB (macroblock) search start instruction MBS
I is supplied to the variable length decoding circuit 15. Variable length decoding circuit 1
5 responds by decoding the MB header and obtaining the resulting macroblock address increment MBA
INC is supplied to the overall control circuit 12, and then an MB header decoding completion notification MBHDC is supplied to the overall control circuit 12. The overall control circuit 12 sends the MB header decoding completion notification MBH
When the macroblock address MBADR indicates outside the pan scan area 21A in response to DC, the MB search start instruction MBSI is supplied to the variable length decoding circuit 15, and the above processing is repeated. As a result, the DCT coefficients of the MBs outside the pan scan area 21A in the original image 20 are not decoded and are not stored in the decoded data area 132 of the memory 13.

When the macroblock address MBADR indicates the inside of the pan scan area 21A, the general control circuit 12 performs a normal decoding operation. That is, the MB header decoding start command MBHDI is supplied to the variable length decoding circuit 15, and the variable length decoding circuit 15 decodes the MB header in response to this, and supplies the contents to the overall control circuit 12,
When header decoding is completed, MB header decoding completion notification MBH
DC is supplied to the overall control circuit 12. Overall control circuit 12
Responds to the MB header decoding completion notification MBHDC,
The coefficient decoding start instruction MBCDI is supplied to the variable length decoding circuit 15 and the motion compensation prediction decoding circuit 18 so that the variable length decoding circuit 1
5. In response to this, the inverse quantization circuit 16, the inverse DCT circuit 17, and the motion compensation prediction decoding circuit 18 (decoding circuit) decode the MB and store the decoded MB in the decoded data area 132 of the memory 13. The coefficient decoding completion notification MBCDC is supplied to the overall control circuit 12. The overall control circuit 12 is MB
In response to the coefficient decoding completion notification MBCDC, an MB header decoding start instruction MBHDI is supplied to the variable length decoding circuit 15 to the variable length decoding circuit 15, and the above processing is repeated.

In this way, only the pan scan area 21A of the original image 20 is decoded and stored in the decoded data area 132 of the memory 13. Pan scan control circuit 12
FIG. 3 shows an example of the configuration of FIG. Pan scan area calculation circuit 3
0 is the original image horizontal pixel number OH, the original image vertical pixel number OV, the pan scan area horizontal pixel number PH,
The MB search data HS, HE, VS, and VE shown in FIG. Is calculated. When the MB search data HS, HE, VS and VE are obtained, they are held in the registers 31 to 34 at the timing of the rise of the control signal S1, respectively. Outputs of the registers 31 to 34 are supplied to one input terminals of comparators 41 to 44 of the comparison circuit 40, respectively.

On the other hand, the macro block address generation circuit 5
At 0, the macroblock address increment MBAINC supplied to the register 51 and the output of the register 51 are added by the adder circuit 52, and the result is held as the macroblock address MBADR in the register 51 at the rising timing of the control signal S2. You. The contents of the register 51 are cleared to zero by the decoded vertical synchronization signal DVSYNC. The lower and upper bits of the output of the register 51 represent the horizontal position X and the vertical position Y of the macroblock unit shown in FIG. 5, respectively, and the horizontal position X is supplied to the other input terminals of the comparators 41 and 42. The vertical position Y is supplied to the other input terminals of the comparators 43 and 44. The comparator 41 outputs “H” when HS ≦ X.
And outputs 'L' otherwise. Comparator 4
2 outputs 'H' when X ≦ HE, and outputs 'L' otherwise. The comparator 43 outputs “H” when VS ≦ Y, and outputs “L” otherwise. The comparator 44 outputs “H” when Y ≦ VE, and outputs “L” otherwise.

In the comparison circuit 40, the outputs of the comparators 41 and 42 are supplied to an AND gate 45, and the comparators 43 and 4
4 is supplied to an AND gate 46, and the outputs of the AND gates 45 and 46 are supplied to a NAND gate 47.
The output of the NAND gate 47 is the position (X, Y) of the decoding MB.
Becomes "H" when the pixel does not exist in the pan scan area 21A of FIG. 5, and becomes "L" otherwise.

The output of the NAND gate 47 is the AND gate 6
0 is supplied to one input terminal, and the other input terminal of the AND gate 60 is supplied to the pan scan mode PSMOD. The output of the AND gate 60 is supplied to one input terminal of the AND gate 61, and the logical value of the output of the AND gate 60 inverted by the inverter 62 is obtained by the AND gate 63.
Is supplied to one of the input terminals. AND gates 61 and 6
3 is supplied with an MB header decoding & search start instruction MBHDSI.

Therefore, the pan scan mode and the macro block address MBADR are set in the pan scan area 21.
In the case of indicating outside of A, the MB header decoding & search start instruction MBHDSI is taken out from the AND gate 61 as the MB search start instruction MBSI. At this time, the MB header decoding start instruction MBHDI becomes inactive. Conversely, MB header decoding & search start command MBHD
SI is the MB header decoding start instruction M from AND gate 63
It is taken out as BHDI, and at this time the MB search start instruction MBSI becomes inactive.

Next, the operation of the moving picture decoding apparatus in the pan scan display will be described with reference to FIGS. The time in the parentheses below indicates the time in the figure. Picture decoding is started in synchronization with the decoded vertical synchronization signal DVSYNC. (T0) The overall control circuit 12 outputs the decoded vertical synchronization signal DVS
If the presence / absence F of the coded data in the memory is “H” (decoding enable) at the fall of the YNC, the picture decoding start command PDI is supplied to the variable length decoding circuit 15. As a result, the coded image data DAT0 is read from the coded data area 131 via the memory control circuit 11, the picture header is decoded, and the control information is separated and sent to the pan scan control circuit 121 of the overall control circuit 12. Supplied.

(T0.5) Pan scan area calculation circuit 3
Based on 0, HS, HE, VS and VE are calculated and held in registers 31 to 34, respectively. (T1) When the picture header decoding completion notification PHDC is supplied from the variable length decoding circuit 15 to the overall control circuit 12, the MB header decoding start instruction MBHDI is supplied from the overall control circuit 12 to the variable length decoding circuit 15 when decoding is enabled. You. In response to this, the variable length decoding circuit 15 decodes the header of MB1 and supplies it to the overall control circuit 12.

(T2) An MB header decoding completion notice MBHDC is supplied from the variable length decoding circuit 15 to the overall control circuit 12. Since the macroblock address MBADR indicates outside the pan scan area 21A, the overall control circuit 12 supplies the MB search start instruction MBSI to the variable length decoding circuit 15 when decoding is enabled in response to the MB header decoding completion notification MBHDC. . In response to this, the variable length decoding circuit 15 extracts a macroblock address increment MBAINC from the header of MB2 and supplies this to the pan scan control circuit 121.

The processing of (t1) and (t2) is performed at time t
This is repeated until k + 1. At time tk + 1, the macroblock address MBADR indicates the inside of the pan scan area 21A, the output of the AND gate 60 becomes “L”, the AND gate 61 is closed, the AND gate 63 is opened, and the MB header decoding starts. The instruction MBHDI becomes active. (Tk + 1) Variable length decoding circuit 15 to overall control circuit 12
In response to the MB header decoding completion notification MBHDC, the overall control circuit 12 sends the MB header to the decoding circuit when decoding is enabled.
A coefficient decoding start instruction MBCDI is supplied.

(Tk + 2) In response to the MB coefficient decoding notification MBCDC from the variable length decoding circuit 15 to the overall control circuit 12, the overall control circuit 12 supplies an MB header decoding start instruction MBHDI to the decoding circuit when decoding is enabled. .
Thus, the pan scan area 21 in the original image 20
Only A is decoded and stored in the decoded data area 132 of the memory 13.

FIGS. 8 and 9 show a normal decoding operation without performing the pan scan display, in association with FIGS. 6 and 7. FIG.
This operation is the same as when the entire range of the original image is the pan scan area when performing the pan scan display. In the present embodiment, in the case of the pan scan display, only the coded image data DAT0 in the pan scan area 21A is decoded and stored in the decoded data area 132 of the memory 13. Therefore, for example, the storage capacity of the memory 13 is equal to the data capacity of the MPEG system. When only the MPEG method and other data are included, such as a DVD, pan-scan display is possible even if normal display cannot be performed.

The present invention includes various other modifications. For example, the decoding may be performed outside the pan scan area 21A, and the decoded image data DAT2 may be stored in the decoded data area 132 of the memory 13 only in the pan scan area 21A. Since the size of one macroblock on the display screen is small, the above [] may be truncated or rounded off to the nearest decimal point.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a video decoding device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a characteristic unit in FIG. 1;

FIG. 3 is a diagram illustrating a configuration example of a pan scan control circuit in FIG. 2;

FIG. 4 is an explanatory diagram of pan scan information.

FIG. 5 is an explanatory diagram of a pan scan area.

FIG. 6 is a time chart at the time of pan scan.

FIG. 7 is a time chart at the time of a pan scan.

FIG. 8 is a time chart at the time of normal decoding.

FIG. 9 is a time chart at the time of normal decoding.

[Explanation of symbols]

 Reference Signs List 10 moving image decoding device 11 memory control circuit 12 overall control circuit 121 pan scan control circuit 13 memory 131 coded data area 132 decoded data area 14 memory bus 15 variable length decoding circuit 16 inverse quantization circuit 17 inverse DCT circuit 18 motion compensation circuit Reference Signs List 19 image display circuit 20 original image 21 pan scan setting area 21A pan scan area 30 pan scan area calculation circuit 31-34, 51 register 40 comparison circuit 41-44 comparator 50 macro block address generation circuit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Katsuki Miyawaki 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Hidenaga Takahashi 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Limited (72) Inventor Hirohiko Inagaki 2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Fujitsu Digital Technology Limited In-house

Claims (7)

[Claims] 1. A method for decoding only encoded image data corresponding to a pan-scan display area based on pan-scan information included in control information separated from encoded image data and writing the decoded image data to a memory. Video decoding method. 2. Decoding encoded image data and storing only decoded image data corresponding to a pan scan display area in a memory based on pan scan information included in control information separated from the encoded image data. A moving picture decoding method characterized by writing. 3. A memory having a first storage area and a second storage area; a decoding circuit for separating control information from encoded image data and decoding the encoded image data; The encoded image data written and written in the first area is read out from the first area and supplied to the decoding circuit, and the decoded image data decoded by the decoding circuit is written in the second storage area, and the decoded A memory control circuit that reads out image data for display, and a main control unit that causes the decoding circuit to decode only decoded image data corresponding to the pan scan display area based on the pan scan information included in the separated control information. A video decoding device, comprising: a control circuit. 4. A memory having a first storage area and a second storage area; a decoding circuit for separating control information from encoded image data and decoding the encoded image data; The encoded image data written and written in the first area is read out from the first area and supplied to the decoding circuit, and the decoded image data decoded by the decoding circuit is written in the second storage area, and the decoded A memory control circuit that reads out image data for display; and, based on the pan scan information included in the separated control information, only the decoded image data corresponding to the pan scan display area to the memory control circuit. 2. A moving picture decoding apparatus comprising: a main control circuit for writing data into two storage areas; 5. The decoding circuit decodes the encoded image data in units of m × m pixels, and the main control circuit performs a decoding based on the pan scan information.
Calculate a horizontal decoding start point, a horizontal decoding end point, a vertical decoding start point, and a vertical decoding end point of the mxm pixel unit of the pan scan display area, and calculate the encoded image based on the control information. The m × m pixel unit address of the data is obtained as an encoded image data address, and the encoded image data address is equal to or more than the horizontal decoding start point and equal to or less than the horizontal decoding end point and equal to or greater than the vertical decoding start point. The moving picture decoding apparatus according to claim 3, wherein the decoding circuit performs decoding only when it indicates that it is equal to or less than a direction decoding end point. 6. The moving picture decoding apparatus according to claim 5, wherein said coded picture data is picture data coded according to the MPEG system, and said m × m pixel unit is a macro block. 7. The horizontal decoding start point HS and the vertical decoding start point VS are respectively defined as HS = [(OH / 2−Hofs−PH / 2) / 16] VS = [(OV / 2−Vofs−PV) / 2) / 16], where [] is a rounded integer symbol for the numerical value in parentheses, and OH: the number of pixels in the horizontal direction of the original image OV: the number of pixels in the vertical direction of the original image Vofs: the number of pixels in the vertical direction of the center of the pan scan area with respect to the center of the original image Vofs: the number of pixels in the vertical direction of the center of the pan scan area PH: the number of pixels in the horizontal direction of the pan scan area PV: the number of pixels in the vertical direction of the pan scan area The moving picture decoding device according to claim 6.