JP2002251371A - Communication device and communication method in electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide communication device and the communication method in electronic equipment preventing the reading of erroneous data and permitting respective circuits to independently operate. SOLUTION: In the electronic equipment, an interface circuit 10 and a control circuit 30 are mounted on different substrates. The equipment is provided with a memory 20 having a plurality of faces 21 and 22 having writing side ports and reading side ports and a switch means which selects the face 21 or 22 as a face into which data to the writing side port can be written, selects the other face as that from which data from the reading side port can be read and switches the selected faces in accordance with output from the interface circuit 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic apparatus having a plurality of boards on which independently operating circuits are mounted and configured to enable communication between the boards. And a communication method for performing communication between a plurality of substrates.

[0002]

2. Description of the Related Art Conventionally, in electronic equipment such as telephone exchanges, a printed circuit board (hereinafter, referred to as a package) on which a large number of electronic components are mounted is generally mounted on a printed circuit board called a back wire board. Some systems are configured so that communication between each package is possible.

FIG. 3 shows an example of a system configuration for communication between packages. Here, an interface circuit 110 that collects line error information and the like, and a control circuit 1 that monitors and controls the interface circuit 110
The communication with the T.30 will be described. The interface circuit 110 and the control circuit 130 are mounted on separate packages 101 and 103. These packages 101 and 103 are mounted on a back wire board (not shown) and can communicate with each other. The interface circuit 110 includes a write processing unit 112 that writes data relating to line error information and the like to a dual port memory 120 described below. The control circuit 130 includes a read processing unit 132 that reads the data from the dual port memory 120. Have. On the package 101 on which the interface circuit 110 is mounted, a dual port memory 120 that mediates communication between the interface circuit 110 and the control circuit 130 is mounted. The dual port memory 120 is provided in the interface circuit 1
Write port 12 to which data is written by 10
1 and a read-side port 122 from which data is read by the control circuit 130. The interface circuit 110 transmits data at a constant cycle to the write port 121 of the dual port memory 120,
The control circuit unit 130 reads data from the read port 122 of the dual port memory 120 at a constant cycle. The cycle at which the interface circuit 110 writes data is different from the cycle at which the control circuit 130 reads data. The dual-port memory 120 enables the interface circuit 110 and the control circuit 130 to write and read data having different periods.

However, in such a conventional system, while the interface circuit 110 is writing data to the dual port memory 120, the control circuit 1
When the 30 reads data from the dual port memory 120, the control circuit 130 may read erroneous data. Hereinafter, this point will be described. Here, the interface circuit 110 has the numerals 1 to
It is assumed that data corresponding to 10 is sequentially written to addresses 1 to 4 of the dual port memory 120, and the control circuit 130 sequentially reads data from addresses 1 to 4 of the dual port memory 120. In this case, after the interface circuit 110 sequentially writes the data 1, 2, 3, and 4 at addresses 1 to 4 of the dual port memory 120, the control circuit 130 sets the addresses 1 to 4 of the dual port memory 120.
The data 1, 2, 3, and 4 are sequentially read from the address 4, and the interface circuit 110 sequentially writes the data 5, 6, 7, and 8 into the addresses 1 to 4, and then the control circuit 1
It is ideal that the data 30 sequentially reads data 5, 6, 7, and 8 from addresses 1 to 4. However, immediately after the interface circuit 110 writes the data 5 to the address 1 of the dual port memory 120, the control circuit 130
Starts reading data, data 5, 2,
3, 4 will be read.

Therefore, it has been conventionally proposed to provide an arbitration circuit for adjusting the timing of writing data by the interface circuit 110 and the timing of reading data by the control circuit 130.

FIG. 4 shows an example of a system configuration in which such an arbitration circuit 108 is provided. In this system configuration example, when the interface circuit 110 starts writing data, the arbitration circuit 1
08, a write request signal is transmitted. When the control circuit 130 starts reading data, the control circuit 130 transmits a read request signal to the arbitration circuit 108. Upon receiving the write request signal from the interface circuit 110, the arbitration circuit 108 confirms that the control circuit 130 has not read data (that is, has not received the read request signal), and then transmits the data to the interface circuit 110. Write permission is made for the same. In addition, the arbitration circuit 108 controls the control circuit 13
When a read request signal is received from 0, after confirming that the interface circuit 110 is not writing data (ie, not receiving a write request signal), the control circuit 130 is permitted to read. According to such a configuration, the interface circuit 1
10 cannot write data while the control circuit 130 is reading data from the memory 120, and the control circuit 130 cannot read data while the interface circuit 110 is writing data to the memory 120. Reading cannot be performed. Therefore, reading of erroneous data as described above can be prevented.

[0007]

However, when such an arbitration circuit 108 is provided, there are the following problems. That is, the interface circuit 110 and the control circuit 130 operate under the influence of each other under the permission of the arbitration circuit 108. Therefore, when an abnormality occurs in the communication state between the two circuits, It is not possible to identify whether there is an obstacle. For example, if the data reading by the control circuit 130 has stopped, the data reading has stopped due to a failure in the control circuit 130, or the arbitration circuit has failed because the data writing has not been completed due to a failure in the interface circuit 110. 1
08, it cannot be determined whether or not the read permission has not been issued. Therefore, there is a problem that when such a communication state abnormality between the circuits occurs, both the interface circuit 110 and the control circuit 130 must be replaced.

Further, since both the interface circuit 110 and the control circuit 130 must be provided with a processing unit for processing the transmission of a write request and the reception of a write permission, there is a problem that the respective circuit configurations become complicated. .

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a communication device and a communication method in an electronic device that prevent reading of erroneous data and enable each circuit to operate independently.

[0010]

In order to achieve the above object, a communication device in an electronic apparatus according to the present invention includes a first circuit and a second circuit which operate independently of each other mounted on separate substrates. An electronic device in which the separate substrates are configured to be able to communicate with each other, wherein the memory has a plurality of surfaces, each of which has a write-side port for writing data by the first circuit; A memory configured to have a read-side port for reading data by the two circuits, and one of a plurality of surfaces of the memory as a surface on which data can be written to a write-side port. While selecting another surface as a surface from which data can be read from the read-side port, and selecting each selected surface from the first circuit. And switching means for switching in response to a force, characterized by comprising.

In this case, when the first circuit is writing data to the memory, the first circuit transmits a first control signal indicating that data is being written to the switching means, and When reading data from the memory, the circuit transmits a second control signal indicating that data is being read to the switching means, and the switching means receives the second control signal. It is preferable that the switching be performed according to the first control signal except during the operation. Further, it is preferable that the memory and the switching unit are mounted on the same substrate as the first circuit.

Further, according to a communication method in an electronic device of the present invention, a first circuit and a second circuit that operate independently of each other are mounted on separate boards, and the separate boards can communicate with each other. A memory having a plurality of surfaces, each of which has a write-side port for writing data by the first circuit and a read-side port for reading data by the second circuit. And a memory configured to have a side port, and one of the plurality of surfaces of the memory is selected as a surface on which data can be written to a writing port, and the other surface is selected. Selecting as a surface from which data can be read from the read-side port, and switching each selected surface in accordance with the output from the first circuit. And butterflies.

In this case, when the first circuit is writing data to the memory, a first control signal indicating that data is being written is output from the first circuit, When the second circuit is reading data from the memory, a second control signal indicating that data is being read is output from the second circuit, and the second control signal is output. It is preferable that the switching be performed in accordance with the first control signal except during the interval.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on one embodiment shown in the drawings. FIG. 1 is a block diagram showing a device configuration for realizing a communication device and a communication method in an electronic device according to an embodiment of the present invention.
Indicates timings of various signals transmitted and received between circuits. In FIG. 1, an interface circuit 10 as a first circuit collects data such as line error information in a telephone exchange or the like.
The control circuit 30 as a second circuit monitors and controls the interface circuit 10. The interface circuit 10 and the control circuit 30 are mounted on separate packages 1 and 3, and the package 1 and the package 3 are mounted on a back wire board (not shown) (not shown) and can communicate with each other. . The interface circuit 10 includes a write processing unit 12 that writes data such as line error information to a dual port memory 20 described later.
0 has a read processing unit 32 for reading the data. When writing data by the write processing unit 12, the interface circuit 10 outputs a first control signal indicating that data is being output to a toggle circuit 25 described later. The control circuit 30 includes the read processing unit 3
When the data is read by using the second control signal 2, a second control signal indicating that the data is being read is output to a toggle inhibit circuit 27 described later. Although only one package 1 is shown in FIG. 1, a back wire board (not shown)
Has a plurality of packages 1 attached to it,
It is configured to be able to communicate with the package 3.

Interface circuit 10 and control circuit 30
A dual port memory 20 is mounted on the package 1 in order to mediate transmission and reception of data with the package 1. The dual port memory 20 has a first surface 21 and a second surface 22 having the same configuration. In this specification, the “surface” of the dual-port memory refers to a region that includes a write-side port and a read-side port and that can operate independently of each other. The first surface 21 has a write-side port 21 a to which data can be written by the interface circuit 10 and a read-side port 21 b to which data can be read by the control circuit 30. Like the first surface 21, the second surface 22 has a write-side port 22a to which data can be written by the interface circuit 10 and a read-side port 22b to which data can be read by the control circuit 30.
Both the first surface 21 and the second surface 22 have addresses 1 to 4 for holding data.

The dual port memory 20 stores a write port 21a and a second port 21a of the first surface 21 in response to a write surface set signal transmitted from a toggle circuit 25 described later.
One of the write-side ports 22a of the surface 22 is configured to be writable. Further, in the dual-port memory 20, one of the read-side port 21b of the first surface 21 and the read-side port 22b of the second surface 22 reads data according to a read surface set signal transmitted from an inversion circuit 26 described later. It is configured to be possible.

The package 1 has a toggle circuit 25 for outputting a write surface set signal to the dual port memory 20.
And an inverting circuit 26 for outputting a read surface set signal obtained by inverting the write surface set signal to the dual port memory 20. Further, the package 1 is provided with a toggle inhibit circuit 27 for inhibiting the operation of the toggle circuit 25 when the control circuit 30 is reading data from the dual port memory 20.

Each time the toggle circuit 25 receives the first control signal output from the interface circuit 10, the toggle circuit 25 changes the signal level of the write surface set signal output to the dual port memory 20 and the inversion circuit 26 to, for example, "Hig".
h "," Low "," High ", and" Low "are alternately switched (that is, toggle) The inversion circuit 26 receives the first control signal output from the toggle circuit 25, and The first control signal is inverted and output as a read surface set signal to the dual port memory 20. That is, the inverting circuit 26 includes the toggle circuit 25.
, The signal level of the write surface set signal is changed to, for example, "Low", "High", "Low", "H".
The toggle inhibit circuit 27 outputs a toggle inhibit signal to the toggle circuit 25 to inhibit the toggle operation while receiving the second control signal output from the control circuit 30.

When the signal level of the write surface set signal output from the toggle circuit 25 is "High", the dual port memory 20 enables the write port 21a of the first surface 21 to be writable, and the signal of the write surface set signal is output. When the level is “Low”, the writing port 22 a of the second surface 22 is configured to be writable. When the signal level of the read-out surface set signal output from the inverting circuit 26 is “High”, the dual-port memory 20 can read out the read-out port 21 b of the first surface 21, and outputs the read-out surface set signal. When the level is “Low”, the read-side port 22 b of the second surface 22 is configured to be readable. Thereby, in the dual port memory 20,
Writing data to the writing port and reading data from the reading port are performed in different aspects. That is, the toggle circuit 25, the inversion circuit 26, and the toggle prohibition circuit 27 are provided in the dual-port memory 20 in terms of the surface on which data can be written,
A switching means for switching between a surface from which data can be read and a surface from which data can be read is configured.

Next, a communication method between circuits in the system configured as described above will be described with reference to FIG.

Before starting to write data to the dual port memory 20, the interface circuit 10
The first control signal is output to the toggle circuit 25 (ie,
The signal level of the first control signal is “High”). At this point, if the control circuit 30 has not read data, the toggle prohibition circuit 27 does not output the toggle prohibition signal, and the toggle circuit 25 sets the signal level of the write surface set signal to “High”. . The dual port memory 20 enables writing to the write-side port 21 a of the first surface 21 based on the write surface set signal transmitted from the toggle circuit 25. Next, the interface circuit 10 connects to the first port of the dual port memory 20.
Data is written to the write-side port 21a of the surface 21. Note that, since the signal level of the write plane set signal output from the toggle circuit 25 has become “High”, the inversion circuit 26 sets the signal level of the read plane set signal to “Low”.

The interface circuit 10 has a write-side port 21 a on the first surface 21 of the dual-port memory 20.
In the case where the control circuit 30 starts reading data while writing data to the read surface, the read surface set signal output from the inverting circuit 26 is “Lo” as described above.
w ", the dual-port memory 20 enables reading from the reading-side port 22b of the second surface 22. Therefore, the control circuit 30 sets the reading-side port 22b of the second surface 22 of the dual-port memory 20 to When the control circuit 30 starts reading data, it outputs a second control signal to the toggle prohibition circuit 27 (that is, the signal level of the second control signal is set to “High”). Therefore, the toggle prohibition circuit 27 outputs a toggle prohibition signal for prohibiting the toggle operation to the toggle circuit 25. The control circuit 30 outputs the data from the read-side port 22b of the second surface 22 of the dual port memory 20. When the reading is completed, the second control signal is stopped (that is, the signal level of the second control signal is set to “Low”), so that the toggle is prohibited. Road 27 stops the toggling inhibit signal, cancels the prohibition of the toggle operation by the toggle circuit 25.

When the interface circuit 10 starts writing data again after the data reading by the control circuit 30 is completed, as described above, the toggle circuit 2
5 is not prohibited, the toggle circuit 25 sets the signal level of the write surface set signal to “Low” based on the first control signal output from the interface circuit 10, and sets the second level of the dual port memory 20 to “Low”. Face 2
2 enables writing to the write-side port 22a. Next, the interface circuit 10 communicates with the write-side port 22a of the second surface 22 of the dual-port memory 20.
Write data to The signal level of the write surface set signal output from the toggle circuit 25 is "L".
As a result, the inverting circuit 26 sets the signal level of the read surface set signal to “High”, whereby the dual port memory 20 reads data from the read side port 21b of the first surface 21. Is possible.

On the other hand, when the interface circuit 10 starts writing data again while the control circuit 30 is reading data, the interface circuit 1
0 outputs the first control signal to the toggle circuit 25 (that is, the signal level of the first control signal becomes “High”), but the toggle operation of the toggle circuit 25 is prohibited, so that the write surface setting is performed. The signal level of the signal is "Hig
h ", the dual-port memory 20 continues to be able to write data to the write-side port 22a of the second surface 22. Thereby, the interface circuit 10 allows the second port memory 20 of the dual-port memory 20 to be written. Data is written to the write-side port 22a of the surface 22. That is, the first surface 21 of the dual port memory 20 is written.
Then, since the reading of data by the control circuit 30 is still continued, the writing of data by the interface circuit 10 is performed on the second surface 22.

As described above, the data writing by the interface circuit 10 and the data reading by the control circuit 30 are performed on different surfaces of the dual port memory 20, so that the interface circuit 10 and the dual port memory 20 are independent. Erroneous data reading does not occur.

The embodiment of the present invention has been described with reference to the drawings. However, it is apparent that the present invention is not limited to the matters described in the above embodiments, and that changes, improvements, and the like can be made based on the description in the claims. For example, in the above embodiment, the dual port memory 20
Has two surfaces (the first surface 21 and the second surface 22), but may have three or more surfaces.

[0027]

As described above, according to the present invention, erroneous data reading does not occur even if the first circuit and the second circuit operate independently of each other. As described above, since the first circuit and the second circuit operate independently of each other, if an abnormality occurs in the communication state between the two circuits, it is easy to determine which circuit has a failure. Will be able to do it.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration to which a communication device and a communication method in an electronic device according to an embodiment of the present invention are applied;

FIG. 2 is a timing chart of data communication between an interface board and a control board in the system configuration shown in FIG. 1;

FIG. 3 is a block diagram illustrating an example of a communication method between boards in a conventional electronic device.

FIG. 4 is a block diagram for explaining another example of a communication method between boards in a conventional electronic device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Package 3 Package 10 Interface circuit 20 Dual port memory 21 1st surface 22 2nd surface 25 Toggle circuit 26 Inverting circuit 27 Toggle inhibition circuit 30 Control circuit

Claims (5)

[Claims] An electronic device in which a first circuit and a second circuit that operate independently of each other are mounted on separate substrates, and the separate substrates are configured to be able to communicate with each other. A memory, wherein each surface has a write-side port for writing data by the first circuit and a read-side port for reading data by the second circuit. And selecting one of the plurality of surfaces of the memory as a surface on which data can be written to the write port and reading data from the other port on the other surface. Switching means for selecting each of the selected surfaces as an appropriate surface, and for switching each of the selected surfaces in accordance with the output from the first circuit. That communication device. 2. The first circuit, when writing data to the memory, transmits a first control signal indicating that data is being written to the switching means, Transmits a second control signal indicating that data is being read to the switching means when data is being read from the memory, and the switching means has received the second control signal. 2. The communication device according to claim 1, wherein the switching is performed in accordance with the first control signal except during a period. 3. The memory and the switching means,
2. The communication device according to claim 1, wherein the communication device is mounted on the same substrate as the first circuit. 4. An electronic apparatus in which a first circuit and a second circuit that operate independently of each other are mounted on separate boards and the separate boards are configured to be able to communicate with each other, the electronic apparatus having a plurality of surfaces. A memory, wherein each surface has a write-side port for writing data by the first circuit and a read-side port for reading data by the second circuit. One of the plurality of surfaces of the memory is selected as a surface on which data can be written to the write port, and the other surface can be used for reading data from the read port. A communication method in an electronic device, wherein the communication method is selected as possible surfaces, and each selected surface is switched according to an output from the first circuit. 5. When the first circuit is writing data to the memory, the first circuit outputs a first control signal indicating that data is being written from the first circuit, When the circuit is reading data from the memory, a second control signal indicating that data is being read is output from the second circuit, and a signal is output while the second control signal is being output. Except for the first
The communication method according to claim 4, wherein the switching is performed according to a control signal.