JP2016004368A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor capable of more quickly performing reading/writing of data than the case of alternately switching and performing the reading operation and the writing operation without increasing a circuit scale.SOLUTION: The data processor includes a reconfiguration control means for configuring a memory 18a and a memory 18b on a reconfigurable circuit, and for respectively reconfiguring the memory 18a and the memory 18b as a read-out memory and a write memory. The data processor executes processing of reading the data from the read-out memory; writing the data in the write memory in parallel with the reading of the data; and reconfiguring parallelism at the writing side in accordance with data amounts or parallelism at the reading side.

Description

  The present invention relates to a data processing apparatus.

  Patent Document 1 describes a line buffer circuit that can perform a read operation and a write operation at high speed without increasing the circuit scale.

  That is, data for a predetermined pixel is collectively written in one memory (single port memory), and after writing processing, data for the next predetermined pixel for writing to the memory is input. Previously, data for a predetermined pixel is collectively read from the memory, thereby reducing the memory usage.

JP 2009-246488 A

In the configuration in which data writing to the memory and data reading from the memory are alternately performed, the writing time, the reading time, and the switching control time are separately required, so that the total processing time increases. . That is, assuming that the time required for writing data is Tβ, the time required for reading data from the memory is Tα, and the write / read switching control time is Td, Tβ is required for writing first, and then the switching control time Td is required. Next, Tα is required for reading, and then the switching control time Td is required. Therefore, the total Tβ + Td + Tα + Td = Tβ + Tα + 2Td
Will be required.

  An object of the present invention is to provide a data processing apparatus that can read / write data at a higher speed than when the read operation and the write operation are alternately switched without increasing the circuit scale. There is.

  According to the first aspect of the present invention, the first memory and the second memory are configured on a reconfigurable circuit, and the first memory and the second memory are alternately reconfigured and operated as a read memory and a write memory, respectively. A data processing device comprising: a reconfiguration control means for performing data reading; a reading means for reading data from the read memory; and a writing means for writing data into the write memory in parallel with the data reading.

According to the second aspect of the present invention, when the amount of data read by the reading unit is X, the degree of parallelism of reading is n, and the amount of data written by the writing unit is L,
X / n ≧ L / n ′
The data processing apparatus according to claim 1, further comprising a parallelism control unit that controls a parallelism n ′ of the writing unit.

  According to the first aspect of the present invention, it is possible to read / write data at a higher speed without increasing the circuit scale and compared with the case where the read operation and the write operation are alternately switched.

  According to the second aspect of the present invention, the writing time can be further suppressed within the reading time.

It is a conceptual lineblock diagram of an embodiment. It is a block diagram of a conventional apparatus. It is a configuration block diagram of an embodiment. It is a timing chart (the 1) of an embodiment. It is a timing chart (2) of an embodiment. It is a processing flowchart of an embodiment. It is a timing chart (the 3) of an embodiment. It is a timing chart (the 4) of an embodiment. It is a conceptual block diagram of 2nd Embodiment. It is a timing chart of a 2nd embodiment. It is a block diagram of the configuration of the second embodiment. It is a processing flowchart of a 2nd embodiment.

  Hereinafter, an embodiment will be described with reference to the drawings, taking as an example the case of processing print data.

<First Embodiment>
FIG. 1 is a conceptual configuration diagram of a data processing apparatus according to the present embodiment. The data processing apparatus according to the present embodiment reduces the memory capacity by limiting the amount of data held in the buffer memory to the amount necessary for each processing unit, and reconfigures the internal logic circuit configuration at high speed (in one clock cycle). By using a dynamically reconfigurable processor (DRP), data writing and data reading are performed in parallel.

  That is, a memory (first memory) 18a and a memory (second memory) 18b are provided as buffer memories, and these memories 18a and 18b are switched and used by DRP. At a certain timing, the memory 18a is configured as a read memory and the memory 18b is configured as a write memory, and data is read from the memory 18a and written to the memory 18b using the input pixel data and the write data. At the next timing, the memory 18a is configured as a write memory and the memory 18b is configured as a read memory, and data is written to the memory 18a and data is read from the memory 18b. Further, at the next timing, the memory 18a is configured as a read memory and the memory 18b is configured as a write memory, and data is read from the memory 18a and written to the memory 18b. That is, the first memory and the second memory are alternately functioned as a read memory and a write memory, respectively. Such a switching process is repeated.

  The capacity of the memory 18a and the memory 18b may be a capacity necessary to hold the data of the processing unit. When the processing unit is one line of one page, it is necessary to hold the data for one line. Capacity is sufficient. By reconfiguring the memory for reading and the memory for writing alternately by DRP, reading and writing can be performed simultaneously in parallel, and the processing is faster than when switching between writing and reading alternately and executing them sequentially. To do.

  The memory 18a and the memory 18b can be realized by a DRP core. DRP cores are well known, and are briefly described. The DRP core includes a plurality of circuit elements (PE: processor element) for configuring a logic circuit and wiring resources for configuring connections between these PEs. The circuit operates as a logic circuit having various configurations by changing the connection between them. By making one of the plurality of configuration data stored in the storage unit valid (active), PE settings and rewiring between PEs are performed according to the configuration data, and a desired processing circuit is configured. The The configuration data is set as configuration data A and configuration data B. By enabling the configuration data A, a read circuit using the memory 18a and a write circuit using the memory 18b are configured, and by enabling the configuration data B, the memory A writing circuit using 18a and a reading circuit using memory 18b are configured.

  The memory 18a and the memory 18b are, at a certain timing, the memory 18a serves as a read memory for the nth line, the memory 18b serves as a write memory for the (n + 1) th line, and at the next timing, the memory 18b serves as a read memory for the (n + 1) th line. Since 18a serves as a write memory for the (n + 2) -th line, it is basically desirable to have the same capacity, but the present invention is not necessarily limited to this.

  FIG. 2 is a conceptual configuration diagram of a conventional apparatus for reference, that is, a configuration diagram when reading and writing are alternately performed on one memory. A write / read switching control unit 11 and a write / read memory 18 are provided. The writing / reading switching control unit 11 collectively writes data for a predetermined pixel into the memory 18, performs a writing process, switches to reading, and reads the data for the predetermined pixel from the memory 18 at once.

  3A and 3B are block diagrams of the configuration of the data processing apparatus according to the present embodiment. The data processing apparatus includes a read side input control unit 10, a write side input control unit 12, a read address generation unit 14, a write address generation unit 16, a data storage unit (1), and a data storage unit (2). ), An output control unit 20, and a reconstruction control unit 22. The data storage unit (1) and the data storage unit (2) function as the memory 18a and the memory 18b in FIG. 1. In FIG. 3 (a), the data storage unit (1) reads the data storage unit (1) 18a of the read memory. The data storage unit (2) functions as the data storage unit (2) 18b of the write memory. In FIG. 3B, the data storage unit (2) functions as the data storage unit (2) 18b of the read memory, and the data storage unit (1) functions as the data storage unit (1) 18a of the write memory. Each unit can be realized by a DRP core or a CPU and DRP mixed chip as described above.

  In FIG. 3A, the input control unit 10 outputs the read data to the read address generation unit 14 and the data storage unit (1) 18a.

  The input control unit 12 outputs the write data to the write address generation unit 16 and the data storage unit (2) 18b.

  The read address generation unit 14 generates a read address according to the read data, reads the data from the data storage unit (1) 18a, and outputs the data to the output control unit 20.

  The write address generation unit 16 generates a write address according to the write data and writes the input data to the data storage unit (2) 18b.

  On the other hand, in FIG. 3B, the input control unit 10 outputs the read data to the read address generation unit 14 and the data storage unit (2) 18b.

  The input control unit 12 outputs the write data to the write address generation unit 16 and the data storage unit (1) 18a.

  The read address generation unit 14 generates a read address according to the read data, reads the data from the data storage unit (2) 18b, and outputs the data to the output control unit 20.

  The write address generation unit 16 generates a write address according to the write data and writes the input data to the data storage unit (1) 18a.

  The reconfiguration control unit 22 reconfigures the data storage unit (1) and the data storage unit (2) by switching the configuration data, and alternately changes FIG. 3 (a) and FIG. 3 (b). That is, data is read from the data storage unit (1) 18a and written to the data storage unit (2) 18b as shown in FIG. 3A at a certain timing, and changed to the configuration shown in FIG. 3B at the next timing. Then, the data is read from the data storage unit (2) 18b and the data is written to the data storage unit (1) 18a. In FIG. 3A, data reading from the data storage unit (1) 18a and data writing to the data storage unit (2) 18b are performed in parallel. Also in FIG. 3B, reading of data from the data storage unit (2) 18b and writing of data to the data storage unit (1) 18a are performed in parallel. Specifically, the data of the first line is supplied from the input control unit 12 to the data storage unit (2) 18b, and the data of the first line is stored in the data storage unit (2) 18b. Next, the reconfiguration control unit 22 changes the configuration data, reconfigures the configuration shown in FIG. 3A to the configuration shown in FIG. 3B, generates a read address from the read address generation unit 14, and generates a data storage unit. (2) The first line data is read from 18b. In parallel with the reading, the data on the second line is supplied from the input control unit 12 to the data storage unit (1) 18a, and the data on the second line is stored in the data storage unit (1) 18a. Next, the reconfiguration control unit 22 changes the configuration data, reconfigures the configuration shown in FIG. 3B to the configuration shown in FIG. 3A, generates a read address from the read address generation unit 14, and generates a data storage unit. (1) The data of the second line is read from 18a. In parallel with the reading, the data of the third line is supplied from the input control unit 12 to the data storage unit (2) 18b, and the data of the third line is stored in the data storage unit (2) 18b. Thereafter, the process is repeated until the last line in the same manner. Of course, writing / reading may be performed by dividing data for one line into a plurality of times. In the figure, arrows 24 indicate how the functions of one data processing apparatus are alternately switched by dynamic reconfiguration.

  Next, the write / read timing of this embodiment will be described more specifically.

  FIG. 4 schematically shows the write / read timing of this embodiment. For comparison, the writing / reading timing in the conventional configuration shown in FIG. 2 (that is, the configuration in which writing and reading are alternately executed sequentially for one writing / reading memory 18) is also shown. 4A shows the timing of the conventional configuration, and FIG. 4B shows the timing of this embodiment. As an example, the capacity of the write / read memory 18 is 100 bytes, and the capacity of both the data storage unit (1) and the data storage unit (2) is 25 bytes. For simplification, it is assumed that the data amount of one line as a processing unit is 100 clocks.

  As shown in FIG. 4A, conventionally, one line of data is first written to the write / read memory 18 at 100 clocks (clk), and then from the write / read memory 18 at 100 clocks (clk). Read line data. Data write / read processing for one line is performed in a total of 200 clocks. In practice, there is a finite switching time between the writing process and the reading process, but this is omitted here.

  On the other hand, as shown in FIG. 4B, in this embodiment, ¼ of the data for one line is written in the data storage unit 2 in 25 clocks by the configuration of FIG. Next, the configuration is changed to the configuration of FIG. 3B, and data is read from the data storage unit (2) at 25 clocks, and at the same time, data is written to the data storage unit (1) at 25 clocks. Next, the configuration is changed again to that shown in FIG. 3A, and data is read from the data storage unit (1) at 25 clocks, and at the same time, data is written to the data storage unit (2) at 25 clocks. Data write / read processing for one line is performed at 125 clocks. In practice, there is a finite switching time for reconfiguration, but this is omitted here.

  Therefore, the time required for writing and reading is 200 clocks in the past, but in this embodiment, 125 clocks are sufficient, the memory usage is reduced to 1/2, and the processing time is also 125/200 = 5. Reduced to / 8.

  FIG. 5 schematically shows the write / read timing of this embodiment. This is a case where the capacity of both the data storage unit (1) and the data storage unit (2) is 50 bytes.

  FIG. 5A is a conventional timing chart. Like FIG. 4A, data is written to the write / read memory 18 at 100 clocks (clk), and then the write / read memory at 100 clocks (clk). Read data from 18.

  On the other hand, as shown in FIG. 5B, in the present embodiment, ½ of the data for one line is written in the data storage section (2) with 50 clocks by the configuration of FIG. Next, the configuration is changed to the configuration of FIG. 3B, and data is read from the data storage unit (2) at 50 clocks, and at the same time, data is written to the data storage unit (1) at 50 clocks. Next, the configuration is changed again to that shown in FIG. 3A, and data is read from the data storage unit (1) at 50 clocks, and at the same time, data is written to the data storage unit (2) at 50 clocks. Data write / read processing for one line is performed at 150 clocks.

  Therefore, the time required for writing and reading is conventionally 200 clocks, but in this embodiment, only 150 clocks are required. The memory usage is the same and the processing time is reduced to 150/200 = 3/4. .

  FIG. 6 is a process flowchart of the present embodiment. First, a pixel value is input and memory data is input (S101a, S101b). In S101a and S101b, the alphabet (a, b) following the step number (S101) means that these processes are executed in parallel. That is, S101a and S101b are executed in parallel. The same applies to the subsequent steps.

  Next, the read address generator 14 generates a read address, and the write address generator 16 generates a write address (S102a, S102b). Data is read from the memory using the generated read address, and data is written to the memory using the generated write address (S103a, S103b). In the configuration of FIG. 3A, data is read from the data storage unit (1) 18a and written to the data storage unit (2) 18b.

  Then, it is determined whether data reading and data writing are completed (S104a, S104b), and further, it is determined whether both data reading and data writing are completed (S105). This is because reading and writing of data are performed independently of each other. Normally, both are completed almost simultaneously, but writing is completed first, and then reading is completed. Note that writing may be completed after reading is completed, but this case will be described later.

  When both are completed, it is determined whether or not all the lines of the page to be printed are completed (S106). If all the lines are not completed, the configuration data is changed and dynamic reconfiguration is performed ( S107). That is, the configurations of FIG. 3A and FIG. 3B are interchanged alternately. Then, the processes of S101a and S101b to S105 are repeated until the processing of all lines is completed.

  In the present embodiment, as described above, data reading and writing are executed in parallel. Therefore, if the data writing time is within the data reading time, the data writing process is hidden in the data reading process. Is possible. That is, apparently, data can be continuously and sequentially output from the output control unit 20.

  FIG. 7 is a timing chart in a typical case where the data writing time is within the data reading time.

When reading the data on the nth line and writing the data on the (n + 1) th line in parallel, between the read time Tα and the write time Tβ,
Tα ≧ Tβ
If the relationship is, the writing process is concealed in the reading process, and the switching time for dynamic reconfiguration is Td, the time T required to complete the process for all lines (N lines) is:
T = (Tα + Td) × N
It becomes. Of course, T is not affected by Tβ.

However, as shown in FIG. 8, it takes time to write the (n + 1) line for some reason,
Tα <Tβ
In this relationship, the writing process cannot be concealed by the reading process, and the writing time is limited, and the total processing time increases. That is, the time T required to complete the processing of all lines is
T = (Tα + Td) × N + (Tβ−Tα) × N
Thus, the overhead of the second term on the right side becomes overhead and the performance of the data processing apparatus is degraded.
Specifically, this relationship is
(I) Read data size per time is smaller than write data size (ii) Parallel degree on read side is higher than parallel degree on write side (iii) When input data format is object (vector) format Etc.

  Therefore, when Tα <Tβ, it is desirable to control Tα ≧ Tβ by variably controlling the parallelism on the data writing side. Hereinafter, an embodiment in this case will be described.

Second Embodiment
FIG. 9 is a schematic diagram for controlling the degree of parallelism on the data writing side. Assuming that the parallelism of the read side circuit 50 is n, n parallel data are collectively read and output. If the data amount on the read side is X, the read time is defined by X / n. On the other hand, if the parallelism of the write side circuit 60 is n ′, n ′ parallel data is written in a lump. When the amount of data on the writing side is L, the writing time is defined by L / n ′. Therefore, when the write-side data amount L per time is given, using the read-side data amount X and the read-side parallelism n,
X / n ≧ L / n ′
The degree of parallelism n ′ of the write side circuit 60 may be controlled so that That is, when the parallelism of the default read-side circuit 50 and the write-side circuit 60 is n, the read-side data amount X, the read-side parallelism n, and the write-side data amount L are used. Dynamic reconfiguration is performed so as to change the degree of parallelism from n to n ′. Specifically, as shown in FIG. 3, since the input control unit 12 controls the data on the write side including the parallelism, the configuration data related to the parallelism of the input control unit 12 is read out with the data amount X on the read side and the read data. What is necessary is just to change and reconfigure | reform according to the parallel degree n of the side and the data amount L of the writing side. In the figure, the configuration data when the parallel degree n ′ data is written is represented as Next1stLUT (lookup table), Next2ndLUT,.

FIG. 10 is a timing chart when the parallelism on the writing side is dynamically reconfigured. When the parallelism on the reading side is n, the reading time is Tα = X / n. On the other hand, if the amount of write data per time is L, the write time is Tβ = L / n when the degree of parallelism remains n, and Tα <Tβ, and the overall processing speed is limited by the write time. However, using the read side data amount X, the read side parallelism n, and the write side data amount L,
X / n ≧ L / n ′
So that the parallelism on the writing side is reconfigured from n to n ′. Thereby, the writing process is concealed in the reading process by setting the writing time to be equal to or shorter than the reading time, and a decrease in the overall processing speed is suppressed. That is, first, data is written at Tβ = L / n ′, reconfiguration is performed at the switching control time Td, data is read out at Tα = X / n, and Tβ = L / n. Data is written at ', reconfiguration is performed again at the switching control time Td, data is read at Tα = X / n, and data is written at Tβ = L / n'. The time T required to complete the processing of all lines (N lines) is:
T = (Tα + Td) × N
And overhead (Tβ−Tα) × N is reduced.

  FIG. 11 is a configuration block diagram of the present embodiment. In addition to the configuration of FIG. 3, a calculation unit 32 that calculates the parallel degree (number of parallelism) on the writing side using input data supplied from the external memory 30 is provided.

  Write data is stored in the external memory 30, and the calculation unit 32 calculates the write-side parallelism n ′ using the write-side data amount L, the read-side data amount X, and the read-side parallelism n, The number of input bits is output to the input control unit 12. Note that the default parallelism is set to the same value on both the reading side and the writing side.

  The input control unit 12 outputs write data, but the number of bits is reconfigured according to the number of bits from the calculation unit 32. A plurality of bit numbers are stored in the memory (lookup table) as the configuration data of the input control unit 12, and for example, 16 bits, 32 bits, 48 bits, and the like are stored. Generally, it can be expressed as 16 bits × N. By validating one of these bits and invalidating the other, the number of bits of the input control unit 12 is reconfigured. When 16 bits are validated, the input control unit 12 outputs the parallelism of the write data as 16, that is, 16-bit data.

  In FIG. 11, the configuration of the data processing apparatus is configuration A, the data storage unit (1) 18a is configured as a read memory, and the data storage unit (2) 18b is configured as a write memory. The input control unit 12 uses the input bit number data from the calculation unit 32 to supply the number of bits on the writing side to, for example, 32 bits to the data storage unit (2) 18b. At this time, data is read out in parallel from the data storage unit (1) 18a.

  Next, the configuration of the data processing apparatus is set as configuration B, and the data storage unit (1) 18a is configured as a write memory while the data storage unit (2) 18b is configured as a read memory. The input control unit 12 uses the input bit number data from the calculation unit 32 to supply the number of bits on the writing side to, for example, 48 bits to the data storage unit (1) 18a. At this time, data is read from the data storage unit (2) 18b in parallel.

  In this embodiment, the memory function of the data processing apparatus is dynamically reconfigured, and the function of the input control unit 12 is also dynamically reconfigured. In this embodiment, the calculation unit 32 is configured separately from the reconfiguration control unit 22, and the reconfiguration control unit 22 includes the function of the calculation unit 32, and the reconfiguration control unit 22 dynamically reconfigures the memory function. While configuring, the function of the input control unit 12 may be reconfigured.

  FIG. 12 is a process flowchart of the present embodiment. The process of S201 is further added to the process flowchart of FIG.

That is, the calculation unit 32 analyzes the read-side parameters and determines the read-side data amount X and the read-side parallelism n. Next, the write side data input bit number is determined using the write side data amount L. That is,
X / n ≧ L / n ′
The degree of parallelism n ′, that is, the number of input bits is determined so that As is apparent from the above inequality, the number of input bits adaptively changes in accordance with fluctuations in the read side data amount X or the write data amount. After determining the number of input bits, the number of output bits of the input control unit 12 is reconfigured (S201).

  The processing after S201 is the same as the processing of S101a and S101b to S107 in FIG. 3, and the data storage unit (1) and the data storage unit (2) are alternately replaced to execute data reading and data writing in parallel. .

  As described above, in the present embodiment, the write processing time can be always suppressed below the read processing time regardless of the data amount on the read side, the degree of parallelism, and the data amount on the write side. Even if data writing is executed in parallel, the overhead of writing can be eliminated.

  In this embodiment, the parallelism n on the reading side is fixed, but the parallelism n on the reading side may be variably controlled as necessary. In other words, this embodiment does not exclude the aspect in which both the parallelism on the write side and the parallelism on the read side are variable.

10 input control unit (read side), 12 input control unit (write side), 14 read address generation unit, 16 write address generation unit, 18a data storage unit (1), 18b data storage unit (2), 20 output control unit 22 Reconfiguration controller.

Claims (2)

A reconfiguration control unit configured to configure the first memory and the second memory on a reconfigurable circuit, and to perform control to reconfigure and operate the first memory and the second memory alternately as a read memory and a write memory;
Reading means for reading data from the reading memory;
Writing means for writing data to the write memory in parallel with reading of data;
A data processing apparatus comprising: When the amount of data read by the reading means is X, the degree of parallelism of reading is n, and the amount of data written by the writing means is L,
X / n ≧ L / n ′
The data processing apparatus according to claim 1, further comprising: a parallelism control unit that controls a parallelism n ′ of the writing unit.

Images