JPH05250316A - Inter-device interface system - Google Patents

Abstract

PURPOSE:To miniaturize an electronic device by remarkably decreasing the number of interface signals while maintaining the interface performance of a conventional parallel data system. CONSTITUTION:The 8-bit parallel data of a UNITA 105 which operates with a clock(CLKA) 102 having a period four times as long as the period of the clock(CLKB) 103 of a UNITB 106 are set in a parallel register(PARAA) 107. Switching circuits (SELU) 108 and (SELL) 109 convert at every four bits of the PARAA 107 into serial data at the timing of the CLKB. The respective serial data are transferred to the UNITB 106 by serial data lines (SIRIU) 114 and (SIRIL) 115 and converted into 8-bit parallel data by shift registers (SFTRU) 110 and (SFTRL) 111 and a parallel register(PARAB) 112.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device-to-device interface system, and in particular, those electronic devices are operating based on clocks having different cycles, and a device operating from a clock having a long cycle can be used with a clock having a short cycle. The present invention relates to an inter-device interface method for transferring data to an operating device.

[0002]

2. Description of the Related Art Electronic devices, particularly computer devices, are required to have higher speed processing capability, and as a means for increasing the speed of a central processing unit of a computer which is particularly required to operate at high speed, the operation clock has a short cycle, that is, There is a method of using a high frequency clock. On the other hand, the access performance of the memory chip and the access performance of the I / O device have not been improved as much as the central processing unit of the computer. Therefore, the memory control device and the I / O control device generally operate with a clock having a long cycle, that is, a low frequency in order to cope with this gap.

In such a case, a device that operates with a high frequency clock and a device that operates with a low frequency clock, such as an interface between the central processing unit and the memory control unit or the central processing unit and the I / O control unit, operate. It is necessary to control the interface with the device. A conventional control method of such an inter-device interface will be described with reference to FIG.

FIG. 3 is a block diagram showing an inter-device interface between a device (UNITA) 205 operating with a long cycle clock and a device (UNITB) 206 operating with a short cycle clock. This interface controls the timing by having the UNITB 206 operating with the short cycle clock recognize the timing of the long cycle clock. Specifically, it is as follows.

In the figure, 201 is a clock generator (CLPK).
G), a clock with a long cycle (CLKA) 202 is distributed to UNITA 205, and a clock with a short cycle (CLA)
KB) 203 is distributed to UNITB 206. Further, a timing identification signal (DEF) 2 for notifying the UNITB 206 of the timing of CLKA 202 having a long cycle
04 is sent out.

FIG. 4 is a time chart of the operation of the inter-device interface of FIG.

First, UNITB 206 to UNITA 2
The data transfer to 05 will be described. Data set in the data transmission register (SDRB) 210 of the UNITB 206 is performed at the timing a when DEF = “1”.
Therefore, the value "β" of SDRB is the timing b of the next DEF.
Up to, ie, during the long cycle of CLKA, SD
It is stored in the RB. UNITA can capture the output of SDRB at timing c.

Next, UNITA 205 to UNITB 2
The data transfer to 06 will be described. In this case, the UNITB 206 receives the data stored in the data transmission register (SDRA) 207 at the timing of CLKA when the timing identification signal DEF = “1”.
RB) 209.

Next, a method of reducing the number of interface signals will be described.

The demand for miniaturization and high density of computer devices is increasing more and more, and this has been considerably improved by the adoption of LSI and the like. Further, as a means of miniaturization by improving the logic, a serial interface method for reducing the number of interface signals is put up as a general technique. This serial interface method will be described with reference to FIGS.

In FIG. 5, a device (UNITA) 605 is a device operating with a long cycle clock (CLKA) 602, and a device (UNITB) 606 is a short cycle clock (CLKA).
B) A device that operates in 603. See also UNITB60
6 receives a timing recognition signal (DEF) 204 to recognize the timing of CLKA and controls the interface operation between the devices. Conversion from parallel data to serial data in UNITA 605 is performed by a shift register (SFTRA) 608, and conversion of received data in UNITB 606 from serial to parallel is performed by a shift register (SFTRB) 609. The inter-device interface line SIRI 611 is a 1-bit serial interface.

The transfer timing of the serial interface of FIG. 5 is as shown in FIG. The data stored in the parallel data register (PARA) 607 of the UNITA 605 is serially transmitted to the UNITB 606 bit by bit at the timing of CLKA. UNITB60
In 6, data is received serially bit by bit at the timing of DEF, and after receiving all bits, it is set as parallel data in the parallel data register (PARAB) 610.

[0013]

Among the conventional interface systems between devices described above, the parallel interface system has a drawback that it hinders miniaturization and high density.

In addition, the serial interface method can significantly reduce the number of signals as compared with the parallel interface method, but it requires a data transfer time that is twice as many as the number of bits to be transmitted, and the interface performance is extremely degraded. There are drawbacks. That is, the serial interface can be used only for an interface that does not require high performance.

[0015]

According to the inter-device interface system of the present invention, there is provided a first device which operates at a timing of a first clock and a second device which has a cycle of 1 / n times the first clock. In the inter-device interface method with the second device operating at the clock timing, the first
First switching means in the first device for converting parallel data of a predetermined bit length transmitted from the device of the above to the second device into serial data in units of m bits where m ≦ n, The serial data converted by the first switching means is transmitted to the second device m
A serial data interface line for each bit unit, and serial data transmitted by these serial data interface lines are received at the timing of the second clock and converted into parallel data of the predetermined bit length in the second device. Data conversion control means in the second device, which executes a second switching means, a data switching instruction to the first switching means and a data switching instruction to the second switching means at the timing of the second clock. And a data switching instruction line for transmitting a data switching instruction from the data conversion control means to the first switching means to the first device, and the predetermined bit length within one cycle of the first clock. The parallel data of the above is divided into m-bit unit serial data, Transmitting the lock of the timing from the first device to the second device.

The first switching means switches the first parallel data register for inputting the parallel data of the predetermined bit length, and sequentially selects each bit of the first parallel data register in units of m bits. Circuit, and the second switching means includes shift registers each having an m-bit length for inputting serial data from the serial data interface line, and each bit of these shift registers. It may be configured to include a second parallel data register having the predetermined bit length.

[0017]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, reference numeral 105 denotes a first device (U which operates with a first clock (CLKA) 102 having a long cycle.
NITA). Further, 106 is the first clock (C
The second device (UNIT) that operates with the second clock (CLKB) 103 having a cycle of 1 / n times that of the LKA) 102.
B). UNITB 106 is C of UNITA 105
The timing identification signal (DEF) 104 for recognizing the timing of the LKA 102 is received to control the inter-device interface with each other.

Reference numeral 107 denotes a parallel data register (PARAA) in which transmission data from UNITA 105 is set.
Is. The data stored in the PARAA 107 is stored in two switching circuits (SELU) 108 / (SELL) 109.
Is converted into serial data and transmitted to the UNITB 106. The UNITB 106 sequentially receives this by the two shift registers (SFTRU) 110 / (SFTRL) 111, restores it to parallel data, and stores it in the parallel data register (PARAB) 112. The flow of one data transfer operation has been described above.

The detailed operation will be described below with reference to the time chart of FIG. 1 and 2 to simplify the explanation
Then, the second clock (CLKB) 103 is a clock having a cycle ¼ that of the first clock (CLKA) 102. Further, the inter-device transfer data is 8-bit length data. Therefore, PARA 107 and PARAB 112 are 8-bit registers.

In the switching circuit for converting the output of PARAA 107 into serial data, CLKB is 1 / of CLKA.
In consideration of the quadruple period, the SELU 108 for converting the upper 4 bits of the PARAA 107 and the SELL 109 for converting the lower 4 bits are each composed of a switching circuit in units of 4 bits. In these switching circuits, the value of the switching signal (CNTL (0), (1)) 116 is "00" → "0" as shown in the time chart of FIG.
By switching from 1 ”→“ 10 ”→“ 11 ”, S
The ELU 108 outputs the PARAA bit output (3) →
Similarly, (2) → (1) → (0), the SELL 109 similarly sequentially selects (7) → (6) → (5) → (4) and serial data (SIRIU) 114, (SIRIL) 115.
Convert to. The CNTL (0) and (1) are generated by the data conversion control unit (CNT) 113 of UNITB. Therefore, the conversion in SELU 108 and SELL 109 is performed at the timing of CLKB.

That is, the transmission data stored in the PARAA 107 is SRIU1 in units of 4 bits within one cycle of CLKA at the timing of CLKB which is a quarter cycle.
14, converted to SIRIL115, and sent to UNITB.

In UNITB, SIRIU114, SI
Each time the RIL 115 switches at the timing of CLKB, the SIRIU 114 is received by the bit (3) of the SFTRU 110 and the SIRI 115 is received by the bit (7) of the SFTRL 111. Then, the data of each shift register is (3) → (2) → (1) → in the SFTRU110.
(0) and in SFTRL (111), (7) → (6) →
By serially shifting from (5) to (4), serial data is captured in each shift register. All bits of serial data are SFTRU110 and SFTRL111
This value is captured by the PARAB 112 at the timing of the parallel data set signal (SET) 117.
Is set to.

The data conversion control unit CNT113 receives the timing identification signal (DEF) 104 from the CNTL (0),
(1) The switching of the signal 116 and the generation of the SET signal 117 are controlled.

In the inter-device interface system of FIG. 1 described above, 8-bit data transfer from UNITA 105 to UNITB 106 can be performed in one cycle of the first clock (CLKA), and this is done by serial data line 2 bits. (SIRIU, SIRIL) and switching control line 2 bits (CNTL (0), (1)), which is a total of four hardware interface lines.

In the case of the conventional parallel interface system shown in FIG. 3, eight hardware lines are required although the performance is the same. In the case of the serial interface method shown in FIG. 5, only one hardware line is required,
Eight times the transfer time was required. The system of the present invention can reduce the number of hardware interface lines while maintaining the same performance as that of the conventional parallel interface system.

[0028]

As described above, the present invention relates to an interface between a first device and a second device that operate on each of a first clock and a second clock whose clock period is n: 1. In the data transfer from the first device operating with the first clock with a long cycle to the second device operating with a second clock with a short cycle, it is set in the transmission unit of the first device. Converting parallel transmission data having a predetermined data length into serial data at the timing of the second clock under the control of the second device;
This conversion into serial data is performed by dividing it into units of the number of bits of serial data that can be transferred to the second device within one cycle of the first clock, that is, m units of m ≦ n. The second device serially receives the serial data divided into bit units at the timing of the second clock and converts the serial data into parallel data having a predetermined data length, thereby maintaining the interface performance of the conventional parallel data method. By serializing the interface, there is an effect that the number of interface signals can be significantly reduced, and as a result, there is an effect that the electronic device can be downsized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart of the operation of the embodiment shown in FIG.

FIG. 3 is a block diagram showing an example of a conventional inter-device interface method.

FIG. 4 is a timing chart of the operation of the conventional example shown in FIG.

FIG. 5 is a block diagram showing another example of a conventional inter-device interface method.

FIG. 6 is a timing chart of the operation of the conventional example shown in FIG.

[Explanation of symbols]

101 Clock Generation Unit (CLKPKG) 102 First Clock (CLKA) 103 Second Clock (CLKB) 104 Timing Identification Signal (DEF) 105 Notifying Timing of First Clock 105 First Device (UNITA) 106 Second Device (UNITB) 107 parallel data register (PARA) 108 switching circuit (SELU) 109 switching circuit (SELL) 110 shift register (SFTRU) 111 shift register (SFTRL) 112 parallel data register (PARAB) 113 data conversion control unit (CNT) ) 114 serial data line (SIRIU) 115 serial data line (SIRIL) 116 switching circuit control signal (CNTL (0-1)) 117 parallel data set signal (SET)

Claims (3)

[Claims] 1. A first device that operates at the timing of a first clock and a second device that operates at the timing of a second clock that is a cycle of 1 / n times the first clock. In the inter-device interface method of
First switching means in the first device for converting parallel data of a predetermined bit length transmitted from the device of the above to the second device into serial data in units of m bits where m ≦ n, The serial data converted by the first switching means is transmitted to the second device m
A serial data interface line for each bit unit, and serial data transmitted by these serial data interface lines are received at the timing of the second clock and converted into parallel data of the predetermined bit length in the second device. Data conversion control means in the second device for executing a second switching means, a data switching instruction to the first switching means and a data switching instruction to the second switching means at the timing of the second clock. And a data switching instruction line for transmitting a data switching instruction from the data conversion control means to the first switching means to the first device, and the predetermined bit length within one cycle of the first clock. The parallel data of the above is divided into m-bit unit serial data, Inter device interface system, characterized by transmitting from the first device in the lock of the timing to the second device. 2. The first switching means sequentially selects a first parallel data register for inputting parallel data of the predetermined bit length and each bit of the first parallel data register in units of m bits. 2. The inter-device interface device according to claim 1, further comprising a switching circuit that operates. 3. The second switching means includes shift registers each having an m-bit length for inputting serial data from the serial data interface line, respectively.
3. The inter-device interface device according to claim 1, further comprising a second parallel data register having the predetermined bit length for receiving each bit of these shift registers.